HK1169503A

HK1169503A - Jitter reduction method and apparatus for distributed synchronised clock architecture

Info

Publication number: HK1169503A
Application number: HK12110223.4A
Authority: HK
Inventors: 彼得．格雷厄姆．福斯特; 亚历克斯．库兹涅佐夫
Original assignee: 克罗诺洛吉克有限公司
Priority date: 2009-05-20
Filing date: 2010-05-20
Publication date: 2013-01-25

Description

Jitter reduction method and apparatus for distributed synchronous clock architecture

RELATED APPLICATIONS

This application is based on and claims the benefit of united states application No. 61/179904 filed on 20/5/2009, the content of which is hereby incorporated by reference in its entirety.

Technical Field

The present invention relates to a method and apparatus for providing a version 3 Universal Serial Bus (USB) architecture (or USB3.0) based synchronization and timing system with connectivity, particularly, but by no means exclusively, for providing clocking, data acquisition and automation and control of test and measurement equipment, instrumentation interfaces and process control equipment, synchronized to any degree necessary in a local environment or distributed scheme.

Background

The USB specification of version 2.0 and the USB specifications including version 2.0 are intended to facilitate interoperation of devices from different vendors in an open architecture. USB 2.0 data is encoded using differential signaling in the form of the difference between the signal levels of two wires (i.e., where the two wires carry information). The USB 2.0 specification is intended as an enhancement to PC architecture, spanning portable environments, desktop and home environments.

However, USB is user-intensive, and therefore the USB 2.0 specification lacks a mechanism for synchronizing devices to any high degree of accuracy. Several proposals have attempted to address this and other deficiencies. For example, U.S. patent No. 6,343,364 (Leydier et al) discloses an embodiment for frequency locking a USB communication stream directed to a smart card reader. This document discloses a local, free running clock that is compared to the USB SYNC and packet ID streams; its period is updated to match this frequency, producing a local clock at a nominal frequency of 1.5 MHz. This provides a degree of synchronization sufficient to read the smart card information into the host PC, but this approach is directed to smart card readers and thus does not address synchronization between devices.

WO 2007/092997(Foster et al) discloses a synchronous USB device that allows for the generation of an accurate clock frequency on the USB device, regardless of the accuracy of the clock in the host PC. The USB SOF packets are decoded by the USB device and processed as a clock carrier signal, rather than serving as a clock reference.

The carrier signal, once decoded from the USB communication stream, will be combined with a scaling factor (scaling factor) to produce synchronization information to synthesize a local clock signal with precisely controlled clock frequency. In this manner, the frequency of the local clock signal may be more accurate than the somewhat indeterminate frequency of the carrier signal.

This arrangement is said to be able to generate a local clock signal up to any high frequency, for example a clock frequency of tens of megahertz, thus being able to ensure that the local clock of each device connected to a given USB is synchronized in frequency. 10/620,769 also discloses a method and apparatus to further synchronize multiple local clocks in phase by measuring the propagation time of the signal from the host to each device and providing clock phase compensation at each USB device.

Us patent application 12/279,328(Foster et al) discloses synchronizing the local clocks of a plurality of USB devices with a time reference received from another interface. In one embodiment, the USB device contains a local clock that is synchronized with a time stamp provided externally over the Ethernet using IEEE-1588 protocol. In yet another embodiment, the clock of the USB device is synchronized to a time reference from a Global Positioning System (GPS) synchronized clock.

All of the above systems are applicable to conventional USB 2.0 and are equally limited in several areas. USB 2.0 is limited in range due to device response timeouts. This is the time window during which the USB host controller allocates the reception of a signal from a given USB device in response to a request from the USB host controller. The physical length of USB 2.0 is therefore close to 25 m.

The USB3.0 specification was released 11 months 2008, which also focused on consumer applications. The USB3.0 specification makes significant changes to the USB architecture. In particular, the above-described background art synchronization configuration would not be applicable to the new 5Gb/s protocol (called "SuperSpeed USB") because it abrogates the broadcast mechanism for SOF packets.

USB3.0 defines two parallel and independent USB buses on the same connecting cable. First, the USB 2.0 bus (for later compatibility) remains unchanged and provides low-speed (1.5Mb/s), full-speed (12Mb/s), and high-speed (480Mb/s) protocols. The second bus-for 5Gb/s traffic-provides super speed USB. These buses operate independently, except that the operation of the bus to a given USB device is mutually exclusive. That is, if a super speed connection is possible, the USB 2.0 bus is disconnected from the device.

The dual bus architecture of USB3.0 is schematically depicted at 10 in fig. 1. The personal computer 12 including the USB host controller 14 is connected to the USB3.0 hub 16 through a first USB3.0 slave cable (compliant cable) 18; the USB3.0 device 20 is connected to the downstream port 22 of the USB3.0 hub 16 by a second USB3.0 slave cable 24.

The USB host controller 14 includes both a USB 2.0 host 26 and a superspeed host 28. The two hosts 26, 28 are independent of each other, and each host 26, 28 is capable of connecting up to 127 devices (including hubs). The USB3.0 slave cable is a composite cable and comprises a USB 2.0 slave cable and a series of shielded wires capable of transmitting super-high speed signals. Thus, the USB3.0 slave cable 18 includes a USB 2.0 slave cable 30 and shielded wires 32.

The USB3.0 hub 16 contains a USB 2.0 hub function 34 and a superspeed hub function 36, each of which is directly connected to its respective host 26, 28 by the composite cable 18. The USB3.0 device 20 contains a USB 2.0 device function 38 and a superspeed device function 40, each connected back to the hub function 34, 36 of its respective USB3.0 hub 16 by the composite cable 24.

At the enumerated USB3.0 device 20, the super speed host 28 checks for the presence of a super speed device function (40). If a super speed device is found, a connection is established. If a superspeed device is not found (as would be the case if only a USB 2.0 device were connected to the port 22), the USB 2.0 host 26 checks for the presence of a USB 2.0 device function (38) in the device 20. Once the host controller 14 determines which device function is connected, it indicates to the USB3.0 hub 16 that communication is only enabled to the downstream port 22 corresponding to whether the USB 2.0 device function 38 or the superspeed device function 40 is attached. This means that only one of the two parallel buses is in operation with a terminal device, such as the USB3.0 device 20, at any one time.

Furthermore, superspeed USB has a different architecture than USB 2.0 bus. Due to the high bit rate, a relatively high speed communication system consumes a large amount of energy. The design requirement for ultra-high speed USB is lower power consumption to extend battery life of the user device. This has led to changes in the previous broadcast design of USB 2.0: superspeed is not a broadcast bus, but rather directs communication packets to specific nodes in the system and cuts off communication on idle links.

This significantly affects any extension of the synchronization arrangement of, for example, U.S. patent application No. 12/279,328, whose method and apparatus for synchronizing devices is based on a broadcast clock carrier signal delivered to each device over a bus that is not suitable for superspeed USB.

The superspeed hub function functions as a device-to-host (or upstream port) and a host-to-device (or downstream port). This means that the superspeed hub function acts to buffer and schedule transactions on its downstream ports, rather than just acting as a repeater. Similarly, the superspeed hub function also functions to schedule transactions on upstream ports. Thus, heavily loaded hub functions add significant non-deterministic delay in the transmission of packets through the system. This also prevents the use of USB 2.0 isochronous profiles such as that of U.S. patent application No. 12/279,328 to operate on superspeed USB.

The immature isochronous synchronization of USB 2.0 is significantly improved in the USB3.0 specification. Opening an isochronous communication pipe between the host controller and the USB device guarantees a fixed bandwidth allocation of the communication pipe in each service interval. The isochronous protocol of USB3.0 contains so-called Isochronous Timestamp Packets (ITP) that are sent to each isochronous endpoint at slightly regular intervals and contain a timestamp of the start of an ITP transaction by the USB host physical layer (Phy) in the time domain of the host controller. The isochronous timestamp packet is accurate to about 25 ns. Superspeed USB shuts down idle links to conserve power, but in order to receive isochronous timestamp packets, the links must be active. Therefore, the host controller must ensure that all links to the device are in a fully active mode (referred to as power state U0) prior to transmission of the isochronous timestamp packet.

Unfortunately, the isochronous timestamp packets may be delayed in propagation along the USB network. USB3.0 also does not provide a method of determining the transit time of packets in superspeed USB, and therefore there is no way to accurately know the phase relationship between time domains on different USB devices. A phase difference of a few hundred nanoseconds is expected to be the optimum, making it impractical for instrumentation or other precision timing requirements with superspeed USB.

United states patent No. 5,566,180 (Eidson et al) discloses a method of synchronizing clocks in which a series of devices on a communication network communicate their local times to each other and the network travel time is determined by a group of messages. Further disclosures by Eidson (U.S. patent nos. 6,278,710, 6,665,316, 6,741,952, and 7,251,199) extend this concept, but are directed only to synchronization configurations in which a constant flow of synchronization messages is passed between each node of a distributed instrument network via the internet. Such continuous sending of messages consumes bandwidth and limits the accuracy of possible synchronization to a few hundred nanoseconds in a point-to-point arrangement and to a lower accuracy (typically microseconds) in a conventional switched subnet.

It should be understood that the terms "clock signal" and "synchronization" are used in this disclosure to refer to clock signals, trigger signals, delay compensation information, and propagation time measurement information. It should also be understood that in the present disclosure the "notion of time" is used to denote the time of occurrence (epoch) or "actual time" and may also be used to refer to a combination of a clock signal and an associated time of occurrence.

Disclosure of Invention

It is a general object of the present invention to achieve accurate synchronization of multiple USB devices to a predefined maximum according to the USB3 specification.

Thus, according to a first broad aspect, the present invention provides a method of reducing jitter in a local clock of a synchronised USB device, the synchronised USB device being attached to a USB hub, the method comprising:

observing a USB data stream (whether a super speed USB data stream or a non-super speed USB data stream) using the USB hub, the data stream having a data stream bit rate;

the USB hub decoding a periodic signal structure in the USB data stream;

said USB hub generating an event signal in response to decoding said periodic signal structure; and

said USB hub locking the frequency of its local clock to said periodic event signal (so that the periodic event signal provides a reference to which the phase locked loop local clock of the USB hub synchronizes its frequency);

wherein the clock of the USB hub is adapted to be a clocking source of the circuitry of the USB hub at substantially an integer multiple of the frequency of the bit rate.

Synchronous USB devices typically operate by locking a local clock to a periodic data structure contained within a data stream. Typically, a USB start of frame (SOF) packet is used as a periodic data structure, which in the case of high-speed USB occurs at a frequency of 1kHz or 8 kHz. Such a relatively low frequency signal is used by the USB device to lock the local clock of the attached USB device using the PLL architecture. The frequency of the local clock is typically in the range of tens of MHz.

Synchronization of multiple USB devices can be compromised because a standard USB hub processes and forwards data from an upstream port to a downstream port. It is another object of the present invention to provide a method for reducing jitter in the local clock of a synchronized USB device.

USB hubs contain their own free-running clock that is used to decode data from the bus and then repeatedly clock data on the output ports (upstream or downstream). As a result, a periodic clock carrier signal, such as a start of frame (SOF) token, transmitted from the host to all devices typically has a greater timing jitter when leaving the hub than when it arrives at the hub.

With a USB high speed hub operating at 480Mb/s, the random phase relationship between the local hub clock and the SOF packets can produce an output SOF jitter of up to one bit time or about 4ns depending on the repetitive clocking configuration employed. Such large indeterminate jitter on the reference clock signal is problematic for phase locked loop control systems and significantly increases the final clock stability. Cascading hubs exacerbates this problem, with each layer potentially adding 4ns of jitter.

In addition, there is a beat effect between the local hub clock rate and the bit rate of the USB data stream (or the rate of the host clock (or the SOF rate)). If there is a large difference in the frequencies of the two clocks, the output SOF jitter of the hub is random in nature when observed over multiple cycles, and this effect can be filtered out using simple electrical filters or statistical techniques. The beat effect occurs when the frequency of the local hub clock approaches the frequency of the host clock, or one becomes close to an integer multiple of the other. When the frequency of one clock is in close proximity to a multiple of another frequency, it appears that the clock of the hub will drift in and out of phase with the leading edge of the SOF token. The result is that when the clocks are in the in-phase condition, there is minimal output phase error, but since the signals are almost completely out of phase, the output phase error will be maximized.

Thus, due to the periodic phase relationship between the host clock and the respective hub clocks, the synchronized clocks of USB devices on different USB hubs will exhibit a significant beat effect. This effect will be manifested as a periodic variation in jitter between USB devices that coincides with the beat frequency of the two clocks.

It should be noted that there are two cases where clock jitter is minimized. In the first case, the two clocks are perfectly synchronized and locked together, or have a constant phase relationship (integer multiple relationship) between the clocks. Under these conditions, there is no repetitive timing error over time. In the second case, the relationship between the two clocks has a long distance from the integer multiple. Under these conditions, the repetitive timing errors are random in nature, but can be easily filtered out using low-pass electrical filters or statistical methods. The worst possible scenario is when the two clocks are nearly resonant (nearly the same frequency) to a range of integer multiples. At this time, a beat frequency occurs, and the jitter significantly varies with the beat frequency. Consider the case where there is a half hertz difference in clock rate. This produces a two second beat effect of the clocks in and out of phase, resulting in a two second periodic increase in clock jitter.

Thus, the method allows for reduced timing jitter in a synchronous USB architecture. The system uses a hub repeater unit whose local oscillator is synchronized to the time reference of the host controller. The synchronization of the local oscillator of the hub provides a constant phase relationship between the USB data stream and the repetitive clocking device resulting in minimal repetitive clocking phase error.

This aspect is applicable to ultra-high speed USB data streams, but is also applicable to high speed USB systems operating at 480 Mb/s.

In one embodiment, USB data flows are observed at an upstream port of the USB hub.

IN an embodiment, the signal structure includes more than one OUT token, IN token, ACK token, NAK token, STALL token, PRE token, SOF token, SETUP token, DATA0 token, DATA1 token, or programmable sequence bit pattern IN a USB DATA packet.

In particular embodiments, the periodic signal structure includes more than one start of frame packet token.

In one embodiment, the periodic signal structure includes more than one superspeed USB isochronous timestamp packet.

In one embodiment, the method includes the local clock of the USB hub employing statistical techniques or electrical filters to reduce jitter of the local clock of the USB hub.

In particular embodiments, the frequency of the clock of the USB hub is synchronized to be approximately an integer multiple of the USB bit stream data rate (in order to over-clock and track the bit rate for sampling and forwarding of the USB data stream). In this way, there is a constant phase relationship between the bit rate of the USB data stream and the clock used to forward the USB data stream, thereby minimizing jitter in the forwarding of the USB data stream by the USB hub. This allows a synchronized USB device, adapted to synchronize its local clock with a periodic signal structure in the USB data stream, to reduce jitter of its local synchronization clock.

In an embodiment, the clocks of the USB hubs are synchronized to have a frequency that is approximately a half integer multiple (e.g., 1.5 times, 2.5 times, 3.5 times, etc.) of the bit rate to track the bit rate. On average, therefore, there is a random phase relationship between the bit rate of the USB data stream and the clock used to forward the USB data stream. This results in the largest possible round-robin forwarding jitter of the USB data streams of the USB hub. However, when a synchronized USB device adapted to synchronize its local clock to a periodic signal structure in the USB data stream uses statistical techniques (or a simple electrical low pass filter) to reduce timing jitter, the randomization of the USB hub forwarding jitter produces minimal jitter in the USB device local clock.

In a second broad approach, the present invention therefore provides an apparatus for reducing timing jitter in a synchronous USB architecture, the apparatus comprising:

a USB hub circuit having a local clock, an upstream port, a plurality of downstream ports, circuitry for communicating to a host controller through the upstream port and to a USB device through the downstream port;

a monitor (e.g. in the form of a monitoring circuit) adapted to observe a USB data stream having a bit rate (whether a super speed USB data stream or a non-super speed USB data stream);

a decoder (e.g. in the form of decoding circuitry) adapted to decode a periodic data structure in the USB data stream;

a signal generator (e.g. in the form of a signal generating circuit) adapted to generate an event signal in response to decoding the periodic data structure;

circuitry (e.g., in the form of phase-lock circuitry) adapted to lock the frequency of the clock of the USB hub circuitry relative to the frequency of the event signal;

wherein the clock of the USB hub circuitry is adapted to be a clocking source for the hub circuitry of the USB hub circuitry at substantially a multiple of the frequency of the bit rate of the USB data stream.

Accordingly, the present invention also provides an apparatus for reducing timing jitter in a synchronous USB architecture.

In one embodiment, the monitor is adapted to observe the USB data stream at the upstream port.

IN an embodiment, the periodic signal structure includes more than one OUT token, IN token, ACK token, NAK token, STALL token, PRE token, SOF token, SETUP token, DATA0 token, DATA1 token, or programmable sequential bit pattern IN the USB packet.

In one embodiment, the clocks of the USB hub circuits are synchronized to be approximately an integer multiple of the USB bit stream data rate (in order to over-clock the sampling and forwarding of the USB data stream) and track the bit rate.

In an embodiment, the clocks of the USB hub circuits are synchronized to approximately a half integer multiple of the bit rate (e.g., 1.5 times, 2.5 times, 3.5 times, etc.) to track the USB bit stream data rate. According to this embodiment, a free-running oscillator that is approximately a half integer multiple of the bit rate would also be a suitable solution.

In a third broad aspect, the present invention provides a method of reducing jitter in a local clock of a synchronised USB device attached to a USB hub, said USB hub having a local clock and repeater circuitry, the method comprising:

controlling a frequency of the local clock of the USB hub;

wherein the clock is adapted to source the clocking of the repeater circuitry of the USB hub substantially at a multiple of the frequency of the bit rate.

The method may comprise controlling said frequency of said local clock of said USB hub to be around a centre frequency which is the frequency of the USB data stream bit rate.

In one embodiment, the controlling the frequency uses a control signal of sine wave, sawtooth or triangular waveform.

In another embodiment, the controlling the frequency uses noise as a control signal.

In a fourth broad aspect, the present invention provides an apparatus for reducing timing jitter in a synchronous USB architecture, the apparatus comprising:

a clock; and

a clock controller or clock controller circuit;

wherein the clock controller or clock controller circuit is adapted to control the clock by adjusting a supply voltage of the clock.

In a fifth broad aspect, the present invention provides an apparatus for reducing timing jitter in a synchronous USB architecture, the apparatus comprising:

a clock having a frequency;

a feedback stabilizer adapted to stabilize a frequency of the clock by feedback control;

a clock controller or clock controller circuit;

wherein the clock controller or clock controller circuit is adapted to control the clock by placing a perturbation signal into a feedback stabilizer of the clock.

In a sixth broad aspect, the present invention provides a method of reducing jitter in a local clock of a synchronised USB device attached to a USB hub in a USB network, the method comprising:

determining a layer of the USB hub within the USB network;

setting a frequency of a clock of the USB hub according to the layer of the USB hub within the USB network so as to avoid matching a frequency of a data bit rate of a USB data stream to within a predefined level, wherein the USB data stream is directly upstream of the USB hub.

In one embodiment, the predefined level is 1 kHz. In another embodiment, the predefined level is 100 kHz.

In particular embodiments, determining the layer of the USB hub includes querying a routing string address of the USB hub.

In another embodiment, determining the layer of the USB hub comprises querying, with software, an operating system of a USB host controller to which the USB network is connected for information about a physical connection layer of the USB hub.

In particular embodiments, determining the layer of the USB hub includes measuring a frequency of the USB data stream at an upstream port of the USB hub.

In a seventh broad aspect, the present invention provides an apparatus for determining the bit rate of a USB data stream received at an upstream port of a USB hub, the apparatus comprising:

a clock having a known or determinable frequency;

circuitry for observing the USB data stream from the upstream port of the USB hub; and

circuitry for comparing the frequency of the clock to the USB data stream to determine the bit rate.

In an eighth broad aspect, the present invention provides a system for reducing jitter in a local clock of a synchronized USB device attached to a USB hub, the system comprising:

a monitor adapted to observe a USB data stream having a bit rate;

a decoder adapted to decode a periodic data structure in the USB data stream;

a signal generator adapted to generate an event signal in response to decoding the periodic data structure;

a USB hub or USB hub circuit having a clock;

circuitry for comparing the frequency of said clock of said USB hub or USB hub circuitry to said USB data stream, thereby to determine said bit rate; and

circuitry adapted to lock the frequency of said clock of said USB hub or USB hub circuitry relative to the frequency of said event signal;

wherein the clock of the USB hub or USB hub circuitry is adapted to act as a clocking source for the USB hub substantially at a multiple of the frequency of the bit rate of the USB data stream such that a constant phase relationship between the clocking source and the USB data stream reduces jitter in the local clock of the USB device.

In one embodiment, the frequency of the clock of the USB hub or USB hub circuitry is substantially synchronized with an integer multiple of the bit rate with a constant phase relationship between the USB data stream and the clock of the USB hub or USB hub circuitry.

In another embodiment, said frequency of said clock of said USB hub or USB hub circuitry is substantially synchronized with a half integer multiple of said bit rate, wherein there is a rapidly varying phase relationship between said USB data stream and said clock of said USB hub or USB hub circuitry upon receipt of each subsequent said periodic signal structure.

It should be noted that all the individual features of each of the above aspects of the invention may be combined according to application and desire.

Furthermore, it should be noted that the present invention also provides devices and systems arranged to perform each of the methods of the invention described above.

In addition, the device according to the invention may be embodied in various ways. For example, the device may be constructed in the form of multiple components located on a printed circuit or printed wiring board, on a ceramic substrate, or at a semiconductor-grade, i.e., single silicon (or other semiconductor material) chip.

Drawings

In order that the invention may be more clearly defined, embodiments will now be described, by way of example, with reference to the accompanying drawings, in which:

FIG. 1 is a diagram of a dual bus architecture of a USB3 according to the background art;

FIG. 2 is a graphical representation of the beat frequency of device time jitter as a function of changing clock mismatch when a USB data stream is clocked at a USB hub, in accordance with the background art;

FIG. 3 is a schematic diagram of a jitter minimizing USB hub according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a USB hub incorporating circuitry for controlling the repetition clocking frequency of the USB hub, according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of control signals applied to a clock of the USB hub of FIG. 4;

FIG. 6 is a schematic diagram of a USB network according to an embodiment of the present invention; and

fig. 7 is a diagram of the repetition timing frequency of the various hub layers of fig. 6.

Detailed Description

The synchronized USB device locks the local clock to periodic signal structures found within the USB data stream. Any jitter in the timing of these periodic signals reduces the local clock phase accuracy of the USB device. Due to the periodic phase relationship between the host clock and the various hub clocks, the synchronized clocks of USB devices on different USB hubs will exhibit a significant beat frequency effect. This effect will be manifested as a periodic variation in jitter between USB devices that coincides with the beat frequency of the two clocks.

Referring to fig. 2, a graph 50 represents this effect of USB hub clock rate based on clock jitter observed in synchronized USB devices.

Graph 50 illustrates beat frequency (f) relative to clock mismatch (δ) between host controller clock (or bit time of USB data stream) and USB hub clock_b). When one clock is an integer multiple of the frequency of the other clock (e.g., at 52), there is a constant phase relationship between the clocks and no beat effect is observed. As the mismatch increases away from integer multiples (i.e., either side of the preferred match 52), the periodic increase in inter-device jitter becomes apparent with a relatively slow beat frequency. As the mismatch further increases, the beat frequency increases to a level 54 (or "filter level") which beats very fast for the low pass filter to suppress periodic jitter, as is achieved according to this embodiment.

Fig. 3 is a schematic diagram of a USB hub 60 according to another embodiment of the present invention. According to this embodiment, clock jitter locked to a periodic signal contained in a data stream, in particular a USB data stream, can be reduced by using a synchronized clock within the entire channel, more particularly in a USB hub for repeatedly clocking data to a downstream port. The USB hub 60 includes an upstream port 62 for communicating with a host controller (not shown), a plurality of downstream ports 64 for communicating with downstream hubs and devices (not shown), a USB hub chip 66, and a synchronizer 68 containing a local clock 70.

The USB hub chip 66 has a superspeed hub function 72 and a non-superspeed hub function 74 (although in some variations of this embodiment, the USB hub chip 66 may contain only non-superspeed hub functions). In use, the superspeed hub function 72 receives superspeed communications 76 from the upstream port 62 and passes them to the downstream port 64, and vice versa. Likewise, non-super speed hub function 74 receives non-super speed communications 78 from upstream port 332 and passes them to downstream port 334, and vice versa.

Synchronizer 68 is operable to monitor at detection point 80 for ultra-high speed communications on ultra-high speed channel 76, non-ultra-high speed communications on non-ultra-high speed channel 78, or both ultra-high speed communications 76 and non-ultra-high speed communications on channels 76 and 78 to lock its local clock 70 to the host controller clock rate by any suitable technique. Local clock 70 of synchronizer 68 provides a local clock signal 82 that resonates with the data rate of the USB data streams on channels 76 and 78, and this local clock signal 82 is used by USB hub chip 336 to clock and forward the USB data streams to downstream port 64.

In this embodiment, the local clock 70 resonates with the bit rate of the USB communications, which results in a constant phase relationship between those communication signals and the sample and forward functionality of the USB hub chip 66. This results in a minimal packet enclosing jitter on repetition, which in turn allows for more accurate phase locking by the attached synchronization means.

According to another variation of this embodiment, clock signal 82 may be adjusted to have a small frequency offset from the clock carrier signal detected at 80. In this way, the relative phase between the host controller's clock and the local clock will change in time. Thus, the phase error associated with the hub for repeated clocking through the USB data stream will vary in time. However, the frequency of this periodic variation of the phase error can be set by the host (by setting a slight frequency offset). Then, a low-pass filter whose cutoff frequency is set to remove time variation in timing jitter may be used in the synchronous USB device attached downstream of the port (refer to fig. 2).

Fig. 4 is a schematic diagram of a jitter reduction device 100 according to an embodiment of the present invention. Device 100 includes a USB hub 102, USB hub 102 having an upstream port 104, a plurality of downstream ports 106, a USB hub chip 108 (containing a superspeed hub function 110 and a non-superspeed hub function 112), a clock 114, and a clock controller 116.

USB hub chip 108 receives a superspeed USB data stream 118 and a non-superspeed USB data stream 120 from upstream port 104, which are retimed by superspeed hub function 110 and non-superspeed hub function 112, respectively, to downstream port 106. The clock 114 provides a clocking signal to the clock input pin 122 of the USB hub chip 108.

The conventional clock of the background art USB includes a simple crystal oscillator circuit that typically runs at 12MHz or 48MHz (and is not done by a clock controller (as opposed to clock controller 116)). Conventional clocks are free running oscillators with a typical clock frequency tolerance of 50 parts per million (ppm) to 100 ppm.

By contrast, the device 100 includes a clock controller 116, the clock controller 116 generating control signals 124 to which the clock 114 depends, thereby providing the clock controller 116 with a mechanism for controlling the frequency and phase of the clock 114. Thus, the device 100 has a somewhat more precise clock 114 in which the frequency and/or phase may be controlled.

In this embodiment, the control signal 824 is a periodic function, such as (but not limited to) a triangular wave, a sawtooth function, or a sine wave function. Fig. 5 is a schematic diagram 130 of an exemplary control signal 124, including a sawtooth function 132, a trigonometric function 134, and a sine wave function 136.

According to the embodiment of fig. 4, in use, the control signal 124 produces a "chirp signal" or periodic variation in the frequency of the clock 114. These periodic fluctuations in frequency, if very rapid, have the effect of randomizing the phase of the clock 114 relative to the USB data stream observed at the upstream port 104.

In a variation of this embodiment, the control signal 124 is a "noise" signal (see exemplary noise signal 138 in fig. 5), meaning that the signal is random in time. This electrical noise, when placed in the clock 114, will cause random fluctuations in frequency that have the effect of randomizing the phase of the clock 114 relative to the USB data stream observed at the upstream port 104. There are various forms of electrical noise, the most common being "white noise" with a flat power spectral density. There are many other definitions of noise techniques, such as "pink noise", "brownian noise", etc., with different spectral densities, but generally any noise signal can be placed into clock 114.

The frequency stability of an electrical oscillator is typically affected by variations in the supply voltage. In this embodiment, control signal 124 controls the supply voltage circuitry of clock 114. In another variation of this embodiment, the control signal 124 is placed into the frequency control circuit of the clock 114. In general, the control signal 124 is adapted to be placed into any part of the circuitry of the clock 114 so that it can directly affect the frequency of the clock 114.

In another variation of this embodiment, clock 814 is controlled at a fixed frequency, but with a specified offset from the nominal high speed USB rate of 480Mb/s (240 MHz). If the offset frequency is large enough, any time variation difference in the frequency of the clock 114 and the USB data stream bit rate at the upstream port 104 will be a frequency that can be removed (filtered) from the clock of the attached resonant USB device.

This method is applicable to a first USB hub attached to a USB host controller, but not to a subsequently attached downstream hub. This can be understood with reference to the drawings, which are explained with the aid of embodiments. Consider a USB network shown schematically at 140 in fig. 6. Referring to FIG. 6, the USB network 140 includes a USB host controller 142 attached to a multi-layer star USB network that includes USB hubs 144, 144' and USB devices 146.

USB host controller 142 at a nominal high-speed USB bit rate F of 480Mb/s_USB(or ultra-high bit rate of 5 Gb/s) data 148. The first layer with attached USB hub 144 is configured at a nominal bit rate F_USBWith a small but constant offset F between_offsetTo run its clock (compare with the clock 114 of the USB hub 102 of fig. 4). At this point 150 the bit rate of the USB data stream is F_USB+F_offset. The frequency shift F_offsetLarge enough to allow any high frequency components to be filtered from the resonant clock of the USB device 146 attached at that point.

In the next attachment layer, the USB hub 144' is at a bit rate (i.e., F) at a point 150 away from the first layer USB hub 144_USB+F_offset) At least F_offsetRun their respective clocks (compare to the clock 114 of the USB hub 102). This may thus be, for example, F_USBOr (F)_USB+2×F_offset) However, for practical reasons, it may be preferred to use (F)_USB-F_offset) The USB hub 144' is running, as in this embodiment at point 152. In the next attachment layer, for convenience, USB hub 144 "is labeled F_USB+F_offsetAnd (5) operating.

In this way, the USB hub only needs to know its hierarchy within the multi-layer star topology in order to set its clock offset above or below the nominal USB bit rate. This allows for a very simple control circuit for each USB hub to set its respective clock slightly faster or slower without the complexity of periodic or noisy control signals.

FIG. 7 is a diagram of the frequency interval 160 for the USB data transmission of FIG. 6. USB host controller 142 nominal USB data rate F of 480Mb/s_USBThe data 162 is transmitted. Odd-level hubs (i.e., first, third, fifth, etc.) with a positive offset 164 from the nominal USB data rate, i.e., F_USB+F_offsetAnd (5) operating. Even level hubs (i.e., second level, fourth level, etc.) to nominal USB numbersNegative offset 166 in terms of rate, i.e. F_USB-F_offsetAnd (5) operating. However, it will be readily apparent to those skilled in the art that it is also fully acceptable to use a negative offset for odd layer hubs and a positive offset for even layer hubs.

This embodiment of the invention is more advantageous in the case of ultra-high speed USB. The superspeed hub is assigned a pseudo "address" by a "routing string" contained in the header of each packet. Each hub automatically knows its location within the hierarchy and can therefore automatically select its frequency offset to be positive or negative.

In the case of a non-superspeed USB hub, the location of the hub must be identified by the software layer and additional circuitry employed to receive messages from the host controller, informing them of their location in the hierarchical network. In a preferred embodiment, this may take the form of a USB device located entirely within the hub and connected to one of the downstream ports of the hub. A clock controller (e.g., clock controller 116 of fig. 4) can then be incorporated into such an internal USB device.

In another embodiment, the USB hub (compare with USB hub 102 of fig. 4) initializes its clock 114 to the nominal frequency of the USB data stream bit rate. The clock controller 116 then compares its rate to the bit rate of the USB data stream. If the offset is properly selected (as described above), it may be determined whether the data stream at the upstream port 104 of the USB hub 102 is at the nominal USB bit rate F_USB(implicitly hub at level 1), F_USB+F_offsetOr F_USB-F_offset(this implies that it is an even or odd hub layer, depending on the chosen scheme). Hub layer 1 is a special example. This simple test of the bit rate of the data received at the upstream port 104 is sufficient to determine whether the clock controller 116 should set the frequency of the clock 114 to F_USB-F_offset or F_USB+F_offset。

In yet another embodiment, an adaptive clock is used by the USB hub to repeatedly clock data from the upstream port to the downstream port. In this approach, the USB hub (compare USB hub 102 of FIG. 4) has a clock 114 that samples the USB data stream. The clock 114 can lock onto the phase of the USB data stream packets very quickly, typically within the sync field at the beginning of the packet. Once the phase of the packet is determined relative to the clock 114, the phase most closely aligned with the synchronization pattern is then used to clock the packet through to the downstream port 106.

Modifications falling within the scope of the invention may be readily effected by those skilled in the art. It is therefore to be understood that the invention is not limited to the particular embodiments described by way of example hereinabove, and that combinations of the various embodiments described herein will be readily apparent to those skilled in the art.

In the foregoing description of the invention and in the claims that follow, the word "host controller" encompasses all forms of USB host controllers, including standard USB host controllers, mobile USB (USB-on-the-go) host controllers, and wireless USB host controllers, except where the context requires otherwise due to express language or necessary implication.

In the preceding description of the invention and in the claims which follow, except where the context requires otherwise due to express language or necessary implication, the word "comprise" or variations such as "comprises" or "comprising" is used in an inclusive sense, i.e. to specify the presence of the stated features but not to preclude the presence or addition of further features in various embodiments of the invention.

Moreover, any reference herein to background art is not intended to imply that such background art forms or forms part of the common general knowledge in any country.

Claims

1. A method of reducing jitter in a local clock of a synchronized USB device attached to a USB hub, said USB hub having a local clock and repeater circuitry, the method comprising:

observing a USB data stream using the USB hub, the data stream having a data stream bit rate;

the USB hub decoding a periodic signal structure in the USB data stream;

the USB hub locking a frequency of the local clock of the USB hub to the periodic event signal;

wherein said local clock of said USB hub is adapted to source the timing of said repeater circuitry of said USB hub at substantially an integer multiple of the frequency of the data stream bit rate.

2. A method as claimed in claim 1, comprising said USB hub observing said USB data stream at an upstream port of said USB hub.

3. The method of claim 1 or 2, wherein the periodic signal structure comprises more than one start of frame packet tokens.

4. The method of claim 1 or 2, wherein the periodic signal structure comprises more than one superspeed USB isochronous timestamp packet.

5. A method as claimed in any one of claims 1 to 4, wherein the frequency of the clock of the USB hub is substantially synchronised to an integer multiple of the USB bit stream data rate, with a constant phase relationship between the USB data stream and the clock of the USB hub.

6. A method as claimed in any one of claims 1 to 4, wherein said frequency of said clock of said USB hub is substantially synchronised to a half integer multiple of said USB bit stream data rate, with a rapidly varying phase relationship between said USB data stream and said clock of said USB hub as each subsequent said periodic signal structure is received.

7. A method as claimed in any one of claims 1 to 6, comprising employing statistical techniques or electrical filters by said local clock of said USB hub to reduce jitter of said local clock of USB hub.

8. An apparatus for reducing timing jitter in a synchronous USB architecture, the apparatus comprising:

a USB hub circuit having a local clock, an upstream port, a plurality of downstream ports, circuitry for communicating with a host controller through the upstream port and communicating with a plurality of USB devices through the plurality of downstream ports;

a monitor adapted to observe a USB data stream having a bit rate;

a decoder adapted to decode a periodic data structure in the USB data stream;

circuitry adapted to lock the frequency of said local clock of said USB hub circuitry relative to the frequency of said event signal;

wherein the local clock of the USB hub circuit is adapted to source the clocking of the USB hub circuit at substantially a multiple of the frequency of the bit rate of the USB data stream.

9. An apparatus as claimed in claim 8, wherein the monitor is arranged to observe the USB data stream at the upstream port of the USB hub circuit.

10. An apparatus as claimed in claim 8 or 9, wherein the frequency of the local clock of the USB hub circuitry is substantially synchronised to an integer multiple of the USB bit stream data rate, with a constant phase relationship between the USB data stream and the local clock of the USB hub circuitry.

11. An apparatus as claimed in claim 8 or 9, wherein said frequency of said local clock of said USB hub circuitry is substantially synchronised to a half integer multiple of said USB bit stream data rate, with a rapidly varying phase relationship between said USB data stream and said local clock of said USB hub circuitry on receipt of each subsequent said periodic signal structure.

12. A method of reducing jitter in a local clock of a synchronized USB device attached to a USB hub, the USB hub having a local clock and repeater circuitry, the method comprising:

controlling a frequency of the local clock of the USB hub;

wherein said clock is adapted to source the clocking of said repeater circuit of the USB hub substantially at a multiple of the frequency of the bit rate.

13. A method as claimed in claim 12, comprising controlling the frequency of the local clock of the USB hub to be around a centre frequency which is the frequency of a USB data stream bit rate.

14. The method of claim 12 or 13, wherein the controlling the frequency uses a control signal of sine wave, sawtooth or triangular waveform.

15. The method of claim 12 or 13, wherein the controlling the frequency uses noise as a control signal.

16. An apparatus for reducing timing jitter in a synchronous USB architecture, the apparatus comprising:

a clock; and

a clock controller or clock controller circuit;

17. An apparatus for reducing timing jitter in a synchronous USB architecture, the apparatus comprising:

a clock having a frequency;

a clock controller or clock controller circuit;

18. A method of reducing jitter in a local clock of a synchronized USB device attached to a USB hub in a USB network, the method comprising:

determining a layer of the USB hub within the USB network;

19. The method of claim 18, wherein the predefined level is 1 kHz.

20. The method of claim 18, wherein the predefined level is 100 kHz.

21. The method of any of claims 18 to 20, wherein the determining the layer of the USB hub comprises:

i) inquiring the routing character string address of the USB hub;

ii) querying with software an operating system of a USB host controller to which the USB network is connected for information about a physical connection layer of the USB hub; or

iii) measuring a frequency of the USB data stream at an upstream port of the USB hub.

22. An apparatus for determining the bit rate of a USB data stream received at an upstream port of a USB hub, the apparatus comprising:

a clock having a known or determinable frequency;

23. A system for reducing jitter in a local clock of a synchronized USB device attached to a USB hub, the system comprising:

a monitor adapted to observe a USB data stream having a bit rate;

a decoder adapted to decode a periodic data structure in the USB data stream;

a USB hub or USB hub circuit having a clock;

24. A system as recited in claim 23, wherein the frequency of the clock of the USB hub or USB hub circuitry is substantially synchronized with an integer multiple of the bit rate with a constant phase relationship between the USB data stream and the clock of the USB hub or USB hub circuitry.

25. A system as recited in claim 23, wherein said frequency of said clock of said USB hub or USB hub circuitry is substantially synchronized with a half integer multiple of said bit rate, with a rapidly varying phase relationship between said USB data stream and said clock of said USB hub or USB hub circuitry upon receipt of each subsequent said periodic signal structure.