HK1170867B - Data processing unit and signal receiver including the data processing unit - Google Patents

Description

Data processing unit and signal receiver comprising a data processing unit

Technical Field

The present invention relates to a data processing unit for a receiver of information-carrying signals. The processing unit includes a clock and/or data recovery circuit and a processor circuit. The processing unit is arranged within the signal receiver, in particular, first for performing a coherence check (coherence check) of the data signal.

The invention also relates to a receiver for an information-carrying signal, comprising a data processing unit capable of evaluating the consistency of data in a data signal.

Background

The data signal consistency check by the data processing unit can be applied to any type of receiver, even for direct reception of unprocessed data signals in a wired manner or on a channel. Such data signals are typically defined by a sequence of bits (bits) over time. "data consistency" essentially means the reliability of modulated or unmodulated data picked up by a data receiver.

When data is extracted from an incoming radio frequency signal, which is transmitted by a transmitter, typically a digital radio frequency receiver produces a demodulated data signal on a demodulator output. The modulation of data in a radio frequency signal on a carrier frequency can be of various types. Which may be Frequency Shift Keying (FSK), Amplitude Shift Keying (ASK) or ON-OFF keying (OOK).

In conventional receivers, there are several steps to determine whether the information contained in the received radio frequency signal is deemed appropriate, i.e. whether the data is correct and can be used by the receiver. If the frequency of the received radio frequency signal is first converted via at least one mixer unit and by means of an oscillating signal from a local oscillator, the frequency of the intermediate signal at the output of the mixer unit must be within a specific frequency range. The strength or power of the received radio frequency signal must also be greater than the noise level, which is a characteristic of the receiver. The strength or power may be checked via a received signal strength indicator. When data is processed in the receiver, error calculations may also be made based on the demodulated data signal after data demodulation. Such error calculations must provide values below a specified threshold (CRC).

The receiver must then also synchronize the data clock with its local clock based on the data signal. This must be done in order to enable the data in the radio frequency signal picked up by the receiver to be digitally processed. Generally, with conventional receivers of this type, complete packet acquisition is performed taking into account the correct data transitions (transitions) in the data signal. The error calculation of all data can be performed as previously shown. If the data in the received radio frequency signal is observed to be incorrect after all data processing, then everything is reset to enable the receiver to pick up other radio frequency signals. This constitutes a disadvantage since all data has to be processed for a long time before the receiver is reset in case of incorrect data.

Disclosure of Invention

It is therefore an object of the present invention to provide a data processing unit for a receiver of information-carrying signals, which is capable of checking the consistency of the data signals quickly and immediately before performing all subsequent data processing operations, and which overcomes the disadvantages of the prior art.

Accordingly, the present invention relates to a data processing unit for a data signal receiver, comprising:

a clock and data recovery circuit clocked by a local clock signal and comprising a digital phase-locked loop in which a digitally controlled oscillator is arranged, the digitally controlled oscillator generating at an output at least one pulse signal, the phase and frequency of the pulse signal being adaptable based on a data signal received at an input of the clock and data recovery circuit, and

a processor circuit connected to the clock and data recovery circuit,

the data processing unit is characterized in that the processor circuit is arranged to be able to calculate a variance and a mean value over time of the digital input signal of the numerically controlled oscillator for determining the coherence of the data signal if the calculated mean value and variance are below a predetermined coherence threshold, and to be able to perform a reset of the receiver if the calculated mean value and variance of the digital input signal of the numerically controlled oscillator are above the predetermined coherence threshold,

it is characterized in that the numerically controlled oscillator supplies an in-phase pulse signal and a quadrature pulse signal at the output,

characterized in that the digital phase locked loop comprises a first clock counter receiving the data signal on an input and clocked by a local clock signal for oversampling the data signal, wherein the first counter is arranged to be reset on a reset input on each pulse of a quadrature pulse signal supplied by the digitally controlled oscillator, the output signal value of the first counter at reset after a binary transition of the data signal enabling the digitally controlled oscillator to be adapted.

One advantage of such a data processing unit of the invention is that it can quickly determine whether the data in the data signal received at the clock and data recovery input is correct and not noisy or incorrect data. To do this, the processor unit calculates the mean and variance (variance) of the digitally controlled oscillator input signal in the digital phase locked loop of the clock and data recovery circuit. This calculation is performed on each pulse of the pulse signal from the numerically controlled oscillator after a binary transition in the data signal. If the mean and variance over time of the input signal are close to 0, this directly means that the data signal has consistency. Under these conditions, all subsequent operations may be performed in the processing unit. If the opposite occurs, the receiver can be immediately reset or triggered via the data processing unit.

The invention therefore also relates to a receiver of an information-carrying signal, comprising:

-an antenna for receiving a data carrying signal,

-at least one low noise amplifier for amplifying and filtering the signal picked up by the antenna,

a local oscillator for supplying a high frequency oscillating signal,

at least one mixer unit for mixing the received filtered and amplified signal with a high-frequency oscillating signal supplied by a local oscillator, so as to generate an intermediate signal having a frequency equal to the difference between the frequency of the high-frequency oscillating signal and the carrier frequency of the received signal,

at least one low-pass filter for filtering the intermediate signal,

-a demodulator receiving the filtered intermediate signal for supplying a data signal to a data processing unit according to the invention, said processing unit comprising: a clock and data recovery circuit clocked by a local clock signal and including a digital phase locked loop having a digitally controlled oscillator; a processor circuit connected to the clock and data recovery circuit and configured to calculate a mean and a variance of the digital input signal of the numerically controlled oscillator over time to determine the consistency of the data signal if the calculated mean and variance are below a predetermined consistency threshold.

Drawings

Objects, advantages and features of a data processing unit for a receiver of information-carrying signals will become more apparent from the following description, given on the basis of at least one non-limiting embodiment shown in the accompanying drawings, in which:

fig. 1 shows a simplified view of an embodiment of a data signal receiver, e.g. an FSK signal receiver, comprising a data processing unit according to the present invention;

FIG. 2 shows various electronic units of a clock and data recovery circuit of a data processing unit according to the invention; and

fig. 3 shows a time diagram of various signals of the clock and data recovery circuit of the data processing unit according to the invention.

Detailed Description

In the following description, all components of the data signal receiver known to a person skilled in the art will be presented only in a simplified manner. The receiver may be, for example, an FSK signal receiver, but any other type of receiver that can use a data processing unit according to the invention is conceivable.

Fig. 1 shows a data signal receiver. This signal receiver is for example a Radio Frequency (RF) signal receiver having a data processing unit 15 according to the invention which is capable of calculating a data signal D_OUTThe consistency of (c).

The radio frequency signal receiver 1 may be a conventional FSK RF signal receiver in which the RF signals received by the antenna 2 may be subjected to frequency conversion in two different orthogonal branches. Each branch comprises a mixer 4, 5 for frequency conversion with an oscillating signal provided by a local oscillator 6. The local oscillator 6 may comprise a frequency synthesizer supplying an in-phase oscillating signal S_IAnd quadrature oscillation signal S_Q. Such a frequency synthesizer is typically connected to a quartz oscillator 7 which supplies a determined reference frequency signal for the synthesizer's frequency and phase locked loop.

In a first branch, a first, e.g. high-frequency, mixer 4 combines the RF signal received by the antenna 2 and amplified by a Low Noise Amplifier (LNA) 3 with an in-phase oscillator signal S_IMixing is carried out to provide an intermediate in-phase signal I_INT. In a second branch, a second, e.g. high-frequency, mixer 5 combines the filtered and amplified RF signal with a quadrature oscillator signal S_QMixing is performed to supply an intermediate quadrature signal Q_INT. Intermediate signal I_INTAnd Q_INTMay be, for example, a direct frequency converted baseband signal. These intermediate signals I_INTAnd Q_INTEach is then filtered in a respective low pass filter 8, 9 to provide a filtered signal. The filtered signals then pass through respective amplifier limiters 10, 11, respectively, before data demodulation in a conventional demodulator 12.

The demodulator 12 supplies a data signal D based on the filtered and amplified intermediate in-phase signal and the filtered and amplified quadrature signal_OUTWhich is a binary signal or data stream. Two intermediate in-phase and quadrature signals I_INTAnd Q_INTIs necessary for data demodulation. For example, in the case of frequency shift keying of data of a received RF signal, they can be distinguished between frequency deviation signs (frequency deviation signs).

Demodulator 12 may be a simple D-type flip-flop receiving, for example, an intermediate in-phase signal I at input D_INTAnd from the intermediate quadrature signal Q_INTA clock is provided on its clock terminal. Using such flip-flops and depending on the state of the respective data bit, the flip-flop outputs a binary data signal D_OUTUp is at level 1 or level 0.

The RF signal receiver further comprises a data processing unit 15 which receives the binary data signal D from the demodulator 12_OUT. The binary data signal is supplied to a clock and data recovery circuit 16, which is clocked by a local clock signal CLK. The clock and data recovery circuit mainly comprises a digital phase locked loop in which a digitally controlled oscillator (NCO) is arranged, as explained in more detail below with reference to fig. 2, 3. The data processing unit 15 also comprises at least one processor circuit 17 connected to the clock and data recovery circuit 16. Processor circuit capable of calculating a binary input word NCO of a numerically controlled oscillator_INOr the variance and mean of the digital input signal over time. The variance and mean over time can be easily calculated by, for example, the well-known moving average algorithm and moving maximum-minimum algorithm. Thus, the calculation allows to extract a coherency indication of the data in the received RF signal. If the variance and mean over time, which are calculated by the processor circuit 17, exceed a predetermined threshold, the data in the received RF signal is deemed incorrect and the receiver may be immediately reset. The same happens if the data signal is only related to noise.

The processor circuit 17 may also receive a recovered clock signal R from a clock and data recovery circuit_HAnd a recovered data stream signal R_D. The processing unit may thus perform data processing based on these recovered signals via the processor circuit if the data in the signal received by the receiver is deemed correct. The processing unit may thus form part of a data acquisition system, which comprises a memory for fast action in the system. The recovered clock and data signals may be stored in a memory.

The local clock signal CLK, which clocks the clock and data recovery circuit 16 and the processor circuit 17, may be derived based on a reference frequency signal from the quartz oscillator 7 of the local oscillator 6. A certain number of frequency dividers, not shown, may enable the frequency of the reference frequency signal to be divided in order to supply the local clock signal CLK.

By way of non-limiting example only, the reference signal frequency may be on the order of 26MHz, while the local clock signal frequency CLK may be chosen to be 1 MHz. However, this local clock signal CLK must be established with a frequency: it must be at least 10 times, preferably 100 times, the data stream frequency of the data signal. For example, in the case of a data stream of 10 kbits/sec, the local clock signal CLK may have a frequency in the order of 1 MHz. This allows a binary data signal D_OUTOversampled (oversampled) as explained below with reference to fig. 2, 3.

FIG. 2 illustrates a data processingThe clock and data recovery circuit 16 of the physical unit. Thanks to this circuit, the data and clock of the data signal can be retrieved or recovered from the data signal received by the receiver. To do this, the data and clock recovery operation of the data signal involves removing any transient pulses (transitions) in the received signal and recovering the transmitted bit stream. According to a particular code, the data signal D_OUTConsisting of a sequence of bits that can contain a maximum of 4 consecutive bits of the same value before a bit transition of a different value. This allows the clock and data recovery circuit 16 of the data processing unit to function correctly.

The clock and data recovery circuit 16 includes a digital phase locked loop. Data signal D_OUTI.e. the data stream is oversampled using the local clock signal CLK. Such a local clock signal CLK is derived from the quartz oscillator of the local oscillator, as mentioned above. In a digital phase locked loop, a circuit comprising: a Numerically Controlled Oscillator (NCO) 25 which generates two quadrature pulse signals I on its output_PAnd Q_P(ii) a Two counters 21 and 24. The NCO oscillator 25 and the two counters 21 and 24 are clocked by a local clock signal CLK. The two counters are capable of counting or counting down depending on the level of the data signal on the circuit input. Both counters have a sign and can be reset. They also contain a final bit lock to prevent any "flipping".

If the data signal D_OUTAt a high level to define a "1" data bit, the two counters 21 and 24 count for a duration corresponding to at least the data bit duration. However, when the data signal D_OUTAt low level to define a "0" data bit, the two counters 21 and 24 count down, at least for the duration of the data bit. The first counter 21 is a clock counter and the second counter 24 is a data bit counter.

The first counter 21 is a clock counter which accumulates the data stream on both sides of the bit transition. Bit transitions involve a change of the data signal from a "0" state to a "1" state or a change of the data signal from a "1" stateChange of state to "0" state. If successive bits are in the same "0" or "1" state, the data signal D is during the transition from one bit to another successive bit_OUTThere is no bit transition. Quadrature pulse signal Q_PWhich is generated by the numerically controlled oscillator 25, is supplied to the reset input Q of the first counter_R. If pulse Q_PAnd the frequency and phase of the data signal D at the input of the circuit 16_OUTExact alignment of (1), output H_OUTIs still zero at each reset instant after a binary transition in the data signal. However, at the output I supplied to the numerically controlled oscillator 25_PIs recovered clock signal R_HDuring recovery, any drift results in the input Q of the counter 21_RA positive or negative error on the output of the clock counter 21 at reset.

In quadrature pulse signal Q_PThe polarity of the error E, which is partly shown in fig. 3, is directly related to the value of the data signal bit to be processed. This error is thus multiplied in multiplier 22 by the output signal B of the second bit counter 24_OUTWhich takes into account the value of the data signal bit to be processed. This produces an error that is independent of the value of the data bit. If the pulse signal I is on the output of the numerically controlled oscillator 25_P、Q_PIs lower than the clock frequency of the data signal, under the condition that the data bit is '1', the error is at the output H_OUTThe upper is positive and negative under the condition that the data bit is "0". Thus, if the error is positive when the data bit is "1", the output H_OUTSuch an error in (c) has to be multiplied by the output B of the second counter 24_OUTThe value of +1, if the error is negative when the data bit is "0", is multiplied by the output B_OUTThe value of "-1".

If the pulse signal I is on the output of the numerically controlled oscillator_PAnd Q_PThe same holds true for the case where the generation frequency of (2) is higher than the data signal clock frequency. However, in this case, it is different from the former mentioned aboveThe error of the plane, if it is positive when the data bit is "0", is output H_OUTThe error in (c) has to be multiplied by the output B of the second counter 24_OUTThe "-1" above, if the error is negative when the data bit is a "1", is multiplied by the output B_OUTUpper value "+ 1".

The output signal of the multiplier 22 is filtered in a digital loop filter 23. In the loop filter, a D flip-flop element may be provided, which is controlled by the quadrature pulse signal Q of the oscillator 25 digitally_PA clock is provided. This flip-flop element enables the loop filter to supply a digital input signal or a binary word NCO to the numerically controlled oscillator 25_IN. The digital input signal is a quadrature pulse signal Q following binary transitions in the data signal_PAre supplied on each pulse. Only the previous value of the digital input signal is supplied to the numerically controlled oscillator 25 if no binary transition has been made in two consecutive bits of the data signal. Digital input signal or binary word NCO supplied by loop filter_INDescribes the output value H_OUTI.e. the error E attenuated or weighted by the loop filter 23 when the counter 21 is reset. Following a binary transition, the input signal NCO_INAccording to quadrature pulse Q_PThe data from the output of the first clock counter 21 corrects the frequency and phase.

The signal is attenuated by a factor of, for example, 0.25 by loop 23. Of course, if the data from the received radio frequency signal is correct, the error E is in the quadrature pulse signal Q following each binary transition in the data signal_PBecomes zero at the instant of each pulse. NCO via digital input signal_INThe mean and variance of the signal are calculated so that it can be seen immediately that both the mean and variance over time of the signal are close to 0. Therefore, this means that the data signals have consistency. For such a data signal consistency check, several binary transitions in the data signal may therefore be sufficient to determine the consistency of the data signal. Unlike the coincidence data signal, the noise variance is never zero, but is above a predetermined coincidence threshold. Therefore, the temperature of the molten metal is controlled,this allows the correct data in the received radio frequency signal to be distinguished from incorrect data or simply noise.

It will be appreciated that the output signal H of the first counter 21_OUTAnd the digital input signal NCO of the numerically controlled oscillator 25_INIs an n-bit binary word, e.g. at least 5 bits (not shown). Thus, the D flip-flop element in the loop filter may comprise D flip-flops for respective bits of the binary word, e.g. 5 flip-flops, each of which is formed by a quadrature pulse signal Q_PA clock is provided. However, the output signal of the second counter 24 is a 1-bit signal. Binary word NCO_INAnd can therefore be in-2ⁿAnd 2ⁿTo change between.

For the digital phase locked loop of the clock and data recovery circuit 16 to be actuated, in principle, the transition must be at the data signal D_OUTAnd (4) detecting. To achieve this, the second counter 24 also supplies the data signal B_OUTTo a transition detector 26 which also receives the in-phase pulse signal I from the numerically controlled oscillator 25_P. Such a transition detector may be constituted by a shift register. Inphase pulse signal I_PIt defines the recovered clock signal R_HIs also supplied to the reset input I of the second counter 24_R. This transition detector 26 supplies the recovered data stream signal R on one output_D. If there is no change in the value in successive data signal bits, the other output of the transition detector 26 holds the previous value in the loop filter 23, as indicated previously.

The actuation time and stability of the clock and data recovery circuit is dependent on the digital phase locked loop gain and on the oversampling factor. This oversampling factor is related to the frequency of the local clock signal CLK. If 45 oversampling is performed, a gain of 0.25 corresponds to a minimum actuation time with acceptable stability. Such a gain of 0.25 can easily be achieved by a two bit shift.

Since circuit 16 is purely digital, the frequency of the local clock signal CLK is an independent variable, and the circuit operates in exactly the same manner for all pairs of constants f (data stream)/f (CLK). The frequency of the local clock signal CLK can therefore be fixed at 45 · f (data stream). The choice of the oversampling factor, for example equal to 45, is directly related to the typical size of the transition pulse (transition pulse), which can be observed at the demodulator output and practically defines the recovered clock jitter. This value is also directly linked to the parameterizable data stream frequency and to the quartz oscillator frequency, which may have a value of, for example, 13 or 26 MHz.

Digital input signal NCO_INThe (moving) mean and (moving) variance calculations of (f) correspond to calculations equivalent to the Root Mean Square (RMS) of the magnitudes of these values. If the data signal D_OUTIs correctly aligned on the local clock and the RMS value of the input of the numerically controlled oscillator 25 is close to zero. The more suspect the received data is-for example in the case of a noise source-the more the associated RMS value at the input of the numerically controlled oscillator 25 increases, the more the latter needs correction.

Fig. 3 shows in a simplified manner various signals over time of the clock and data recovery circuit of the data processing unit according to the invention. In particular, fig. 3 shows two inphase and quadrature pulse signals I of a numerically controlled oscillator_PAnd Q_PA first clock counter H_OUTOutput signal of (2), second bit counter B_OUTAnd the data signal D_OUT。

In the case shown, after a binary transition from "1" to "0" in the data signal, a pulse Q is supplied from a digitally controlled oscillator for resetting the counter_PThen, the signal H is output_OUTVery close to 0. This means that the recovered clock signal is correctly adjusted to the data clock and the recovered data signal of the correct signal picked up by the receiver has been correctly supplied. The data signals can thus be regarded as having coherence. If a positive or negative error E occurs, i.e. at reset, the output of the first counter is not 0, the correction is made via the numerically controlled oscillator. Therefore, for the pulse signal I_PAnd Q_PIs adapted to the frequency and phase of the signal. When there is a "1" bit, the second counter counts up by one unit on each stroke (stroke) of the local clock signal CLK. However, when there is a "0" bit, the second counter counts down by one unit per stroke of the internal clock signal CLK. The same holds for the first counter, but the quadrature pulse signal Q_PIs operated on the same phase pulse signal I_POccurs between two pulses. For increasing or decreasing operation on each clock stroke CLK, an output signal H is shown in the form of a triangle (triangle)_OUTAnd B_OUTIn practice in the form of a step (step).

From the description that has just been given, several variants can be made by a person skilled in the art to the data processing unit of the receiver for the data-carrying signals without departing from the scope of the invention as defined by the claims. The data signal for the data processing unit may be supplied directly from the transmitter on the transmission channel or in a wired manner without using a demodulator. In the case of a radio frequency signal receiver, the dual frequency conversion must be performed before the data signal is supplied to the data processing unit. The receiver can thus demodulate the RF signal by ASK or OOK in order to supply the data signal to be checked by the data processing unit.

Claims (15)

1. A data processing unit (15) for a receiver (1) of a signal carrying data, the unit comprising:

-a clock and data recovery circuit (16) clocked by a local clock signal (CLK) and comprising a digital phase locked loop in which a digitally controlled oscillator (25) is arranged, the digitally controlled oscillator (25) generating at least one pulse signal (I) on an output_P，Q_P) The phase and frequency of the pulse signal can be based on a data signal (D) received at the input of the clock and data recovery circuit_OUT) Is adapted toAnd

a processor circuit (17) connected to the clock and data recovery circuit,

the data processing unit is characterized in that the processor circuit is arranged to be able to calculate a digital input signal (NCO) of a numerically controlled oscillator (25)_IN) To determine the coherence of the data signal if the calculated mean and variance are below a predetermined coherence threshold, and to enable the digital input signal (NCO) of the numerically controlled oscillator to be calculated_IN) Is above a predetermined consistency threshold,

characterised in that the numerically controlled oscillator supplies an in-phase pulse signal (I) at the output_P) And quadrature pulse signal (Q)_P)，

Characterized in that the digital phase locked loop comprises a first clock counter (21), the first clock counter (21) receiving the data signal (D) on an input_OUT) And clocked by a local clock signal (CLK) for oversampling the data signal, wherein the first clock counter is arranged to be clocked by a quadrature pulse signal (Q) supplied by a digitally controlled oscillator (25)_P) On each pulse of (2) at the reset input (Q)_R) Reset-up, output signal value (H) of first clock counter at reset after binary transition of data signal_OUT) So that the numerically controlled oscillator can be adapted.

2. A data processing unit (15) as claimed in claim 1, characterized in that the numerically controlled oscillator (25) supplies an in-phase pulse signal (I)_P) Defining a recovered data clock signal (R)_H)。

3. A data processing unit (15) as claimed in claim 1, characterized in that the digital phase locked loop comprises a digital loop filter (23) for the output signal (H) of the first clock counter (21)_OUT) Filtering is carried out in order to obtain a data signal (D)_OUT) Quadrature pulse signal (Q) after binary transition of (2)_P) Supply a digital control oscillator (25) with a digital signal during the pulseInput signal (NCO)_IN)。

4. A data processing unit (15) as claimed in claim 3, characterized in that the digital loop filter (23) attenuates the output signal of the first clock counter (21) by a factor K in order to supply the digital input signal (NCO)_IN)。

5. A data processing unit (15) as claimed in claim 4, characterized in that the factor is equal to 0.25.

6. A data processing unit (15) as claimed in claim 1, characterized in that the clock and data recovery circuit (16) comprises a second data bit counter (24) which receives the data signal (D) on its input_OUT) And is clocked by a local clock signal (CLK) for oversampling the data signal, and is characterized in that the second data bit counter (24) is clocked by an in-phase pulse signal (I) supplied by a digitally controlled oscillator_P) On each pulse of (a) at the reset input (I)_R) And (4) resetting.

7. A data processing unit (15) as claimed in claim 6, characterized in that the clock and data recovery circuit (16) comprises a transition detector (26) which receives the output signal (B) of the second data bit counter (24)_OUT) In order to supply the recovered data signal (R) on the output_H)。

8. A data processing unit (15) as claimed in claim 6, characterized in that the digital phase locked loop comprises a multiplier (22) for multiplying the output signal (HOUT) of the first clock counter (21) with the output signal (B) of the second data bit counter_OUT) The second data bit counter is arranged to take a value of "+ 1" for data signal bits of "1" and a value of "-1" for data signal bits of "0" for supplying the loop filter (23) with the output signal (H) of the first clock counter (21)_OUT) The polarity of the output signal being adapted to the current data signalBit (D)_OUT)。

9. A data processing unit (15) as claimed in claim 7, characterized in that the transition detector (26) is formed by an inphase pulse signal (I) of a digitally controlled oscillator (25)_P) Providing a clock and characterized in that if the transition detector does not detect any binary transition of the data signal from one bit to another, the transition detector supplies a control signal to a loop filter (23) which is forced to hold a preceding digital input signal (NCO) supplied to the numerically controlled oscillator_IN)。

10. A data processing unit (15) as claimed in claim 1, characterized in that the processor circuit (17) comprises memory means in which a moving average algorithm and/or a moving maximum-minimum algorithm are stored for calculating the digital input signal (NCO) of the numerically controlled oscillator_IN) To determine the data signal (D) by means of the variance and mean over time_OUT) The consistency of (c).

11. A receiver (1) of a data-carrying signal, the receiver comprising:

-an antenna (2) for receiving a data carrying signal,

-at least one low noise amplifier (3) for amplifying and filtering the signal picked up by the antenna,

-a local oscillator (6) for supplying a high-frequency oscillating signal (S)_I，S_Q)，

-at least one mixer unit (4, 5) for mixing the received filtered and amplified signal with a high-frequency oscillating signal supplied by a local oscillator, in order to generate an intermediate signal (I)_INT，Q_INT) The frequency of the intermediate signal is equal to the difference between the frequency of the high-frequency oscillation signal and the carrier frequency of the received signal,

-at least one low-pass filter (8, 9) for filtering the intermediate signal,

-a demodulator (12) receiving the filtered intermediate signal for demodulating itThe data processing unit (15) according to claim 1 supplies a data signal (D)_OUT) The data processing unit comprises: a clock and data recovery circuit (16) clocked by a local clock signal (CLK) and including a digital phase locked loop having a digitally controlled oscillator (25); a processor circuit (17) connected to the clock and data recovery circuit and arranged to calculate over time a digital input signal (NCO) of the numerically controlled oscillator (25)_IN) To determine the coherence of the data signal if the calculated mean and variance are below a predetermined coherence threshold.

12. A receiver (1) as claimed in claim 11, characterized in that the data processing unit (15) is arranged to calculate the numerically controlled oscillator digital input signal (NCO) upon calculation_IN) Is above a predetermined consistency threshold, a full reset of the receiver is immediately applied.

13. Receiver (1) according to claim 11, characterized in that it is a frequency shift keying type RF receiver.

14. The receiver (1) of claim 11, characterized in that the local clock signal (CLK) is derived from a reference signal of a local oscillator (6), the frequency of the reference signal being divided by a series of frequency dividers, and in that the local clock signal frequency is arranged to be between 10 and 100 times the data stream frequency of the data signal.

15. The receiver (1) of claim 14, characterized in that the local clock signal frequency is equal to 45 times the data stream frequency.