HK1182221B - Shielded electrical contact and doping through a passivating dielectric layer in a high-efficiency crystalline solar cell, including structure and methods of manufacture - Google Patents

Description

Shielded electrical contact and doping through a passivating dielectric layer in a high efficiency crystalline solar cell including structure and method of manufacture

Information of related applications

This application claims priority from U.S. provisional patent application No.61/318,099 filed on 26/3/2010. The present application also relates to PCT application No. PCT/US2010/031869, filed on 21/4/2010, published as international publication No. wo2010/123974a1 on 28/10/2010, and claiming priority from U.S. provisional application No.61/171,194 entitled "High-efficiency solar cell structures and methods of manufacturing", filed on 21/4/2009. Each of these applications is hereby incorporated by reference herein in its entirety. All aspects of the invention may be used in conjunction with the disclosure of the above-mentioned application.

Technical Field

The present invention relates to a solar cell. More particularly, the present invention relates to improved solar cell structures and fabrication methods for improving cell efficiency.

Background

Solar cells provide a wide range of benefits to society by converting a substantially unlimited amount of solar energy into usable electrical energy. As the use of solar cells increases, certain economic factors such as high-yield production and efficiency become important.

For example, referring to the schematic diagrams of the exemplary solar cell of fig. 1-2 below, it is assumed that solar radiation preferentially illuminates one surface of the solar cell, commonly referred to as the front side. Efficient absorption of photons in silicon wafers is important in order to obtain high energy conversion efficiency for converting incident photons into electrical energy. This can be achieved by low parasitic light absorption of photons in all layers except the wafer itself. Surface texturing (texturing) is a well-known technique for improving the capture of incident optical radiation. Texturing can be achieved in several ways, but is most commonly formed using wet acidic or alkaline etching, where the surface etch of the wafer is not uniform, leaving a dense field of pyramids or conical pins over the entire surface of the solar cell substrate. However, it should be understood that the geometric shapes and/or surfaces may be textured in any shape that is conducive to improving solar cell efficiency.

An important parameter for high solar cell efficiency is surface passivation. Surface passivation is generally believed to have an effect on the suppression of recombination of electrons and holes in the vicinity of or in the vicinity of a particular physical surface of the wafer. Surface recombination can be reduced by applying a dielectric layer on the substrate. These layers reduce the interface state density and thus the number of recombination centers. The most notable examples are thermally grown silicon oxide and PECVD deposited silicon nitride. Examples of other surface passivation layers include intrinsic amorphous silicon, aluminum nitride, aluminum oxide, and the like. This principle is illustrated in fig. 1. The above-described layers can also provide charges that introduce a repulsive force that reduces the probability of carriers of opposite polarity recombining, thereby reducing the recombination rate. The most notable examples of charge carrying passivation layers are silicon nitride and aluminum oxide. Another way to reduce the amount of carriers of one type near the surface is to diffuse doping atoms that are doped the same or opposite the wafer doping type. In this case, a doping level beyond the wafer doping is required to obtain a high-low junction (also commonly referred to as a back surface field or a front surface field) or a p-n junction. This method can be combined with the other surface passivation methods mentioned above.

High efficiency solar cells require good surface passivation in combination with techniques that minimize recombination losses of the electrical contacts to the substrate. The subject of the present invention is an exemplary solar cell structure and practical methods of forming the same that address the above-mentioned problems.

Disclosure of Invention

The present invention overcomes the disadvantages of the prior art and provides additional advantages, including solar cell structures and methods of formation that utilize surface texturing in conjunction with a passivating dielectric layer to provide a practical and controllable technique to form electrical contacts through the passivating dielectric layer and between the conductive layer and the substrate, thus achieving both good surface passivation and electrical contacts with low recombination losses required for high efficiency solar cells. One method of formation and resulting structure is shown, for example, in fig. 2-3.

Also disclosed is a technique for producing a controlled thin dielectric layer that allows majority carriers to pass through, but blocks minority carriers of the substrate from migrating to the conductive layer, thereby minimizing carrier recombination losses. Such a technique is shown, for example, in fig. 6 and 11.

A practical and controllable technique is also disclosed that produces a high efficiency solar cell by implanting dopants into a semiconductor substrate through small openings in a passivating dielectric layer to create P-N junctions buried beneath the passivating dielectric interface. This results in a junction formed within the substrate (e.g., bulk silicon) under the passivation layer with a low interface state density, thus resulting in low carrier recombination. This technique is illustrated, for example, in fig. 9-11.

Furthermore, by implanting dopants through the controlled contact region, a graded doping concentration can be formed within the contact opening. This doping gradient is effective to repel carriers of one polarity, thus creating a shielded low carrier recombination contact. This is shown, for example, in fig. 10-11.

Using textured substrate surface characteristics in conjunction with a dielectric passivation layer is a practical technique to control the total area of the direct contact or the thickness of the tunnel dielectric barrier contact between the conductive layer and the substrate. Moreover, in either case a graded doping profile is formed throughout the controlled contact region. All of these functions are useful in the fabrication of high efficiency solar cells. The principle of controlling the contact area is illustrated in fig. 4, 7 and 8, for example.

In summary, in one aspect, the invention includes a shield electrical contact through a passivating dielectric layer in a high efficiency crystalline solar cell, wherein the passivating dielectric layer is substantially continuous over the substrate except at controlled contact openings on a geometric texture of the substrate. For example, the invention includes controllably providing controlled contact openings in a dielectric layer by selectively etching the dielectric layer.

In one aspect, a P-N junction is formed in a substrate beneath a passivating dielectric layer, for example, by diffusing or implanting dopants from a dopant-containing conductive layer through controlled contact openings in the passivating dielectric layer.

Further, additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention.

Drawings

The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The above and other objects, features and advantages of the present invention will become apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which:

figure 1 illustrates in schematic form the specific requirements of a high efficiency solar cell;

2a-b are partial cross-sectional views of exemplary solar cells having controlled contact structures according to one or more aspects of the present invention;

FIGS. 3a-e illustrate an exemplary process flow and resulting structure of a shield electrical contact through a passivating dielectric layer in accordance with one or more aspects of the present invention;

4a-b are partial cross-sectional views of controlled contact openings through a dielectric layer achieved by adjusting etch parameters to achieve a desired contact opening area and profile in accordance with one or more aspects of the present invention;

FIG. 5 illustrates preferential etching of a dielectric layer at a spike in accordance with one or more aspects of the present invention;

6a-c illustrate exemplary contact structures formed to include direct contacts or tunnel barrier contacts in accordance with one or more aspects of the present invention;

7a-b illustrate contact area control in accordance with one or more aspects of the present invention;

8a-b illustrate an alternative contact opening method using induced cracking of a dielectric layer at the interface plane and spike to reach a preferential etch path for the contact opening in accordance with one or more aspects of the present invention;

9a-b illustrate forming a P-N junction below a passivating dielectric layer in accordance with one or more aspects of the present invention;

10a-d illustrate shielded direct contact structures implemented in accordance with one or more aspects of the invention;

11a-d illustrate a shielded tunnel barrier contact structure implemented according to one or more aspects of the present invention;

fig. 12 is a partial cross-sectional view of an exemplary solar cell having a multifunctional layer requiring electrical contacts according to one or more aspects of the present invention.

Detailed Description

As schematically shown in fig. 1, a high efficiency solar cell requires both a low recombination current (Jo) and a low contact resistance (Rc) between the substrate and the conductive layer. This requirement is met by a structural interfacial layer having, for example, a dielectric area of 99.5-95% and a contact area of 0.5-5%.

Fig. 2a-b are partial cross-sectional views of exemplary solar cells with controlled contact structures, in accordance with one or more aspects of the present invention, in which high efficiency solar cell 10 provides both a good passivation surface and low contact resistance between conductive layer 11, metallization 14, and substrate 13. A structure that passivates the surface with a dielectric layer 12 while providing a relatively small area of contact between the conductive layer and the substrate is a highly efficient ideal structure.

The shield contact structure described herein is equally suitable for use as a front side structure as well as a back side structure 8, or as a simultaneous structure in a high efficiency solar cell.

Fig. 3a-e illustrate an exemplary process flow and resulting structure of a shield electrical contact through a passivating dielectric layer in accordance with one or more aspects of the present invention.

Process steps are discussed in more detail below, which may include (but are not limited to):

step 21: a substrate is provided. The term "substrate" is used broadly herein to mean any underlying layer or layers requiring an electrically conductive connection. Thus, the battery structure herein can include an additional bottom functional layer.

Step 22: texturing the substrate (e.g., pyramidal peaks) is etching into the substrate to form a bottom structure for forming a controlled contact area between the substrate and a subsequently deposited conductive layer.

Step 23: a dielectric layer is deposited, grown, or otherwise formed on the textured substrate to passivate the substrate and allow for controlled contact between the substrate and a subsequently deposited conductive layer.

Step 24: an open contact extending through a portion of the dielectric layer. For example, contact openings are etched or etched along intersecting planes of the pyramid structures and/or through spikes of the dielectric layer to form controlled contact openings between the substrate and a subsequently deposited conductive layer.

Step 25: a conductive layer is deposited on the upper surface and over the controlled contact openings, forming a controlled contact structure between the substrate and the conductive layer.

Step 26: if desired, dopants are diffused into the substrate (discussed further below).

Fig. 3b-e show perspective views of the textured structure resulting from the above steps 22-25, respectively, in the case of a pyramidal texture shape. Fig. 3d shows exemplary openings at the cusps and/or along the intersecting planes of the pyramids.

Fig. 4a-b are partial cross-sectional views of controlled contact openings through dielectric layer 42 on substrate 43 achieved by adjusting etch parameters to achieve the desired contact opening area and profile in accordance with one or more aspects of the present invention. Erosion of intersecting planes and/or peak regions of the texture planes can be achieved by increasing the directionality of the ion bombardment 46 by several techniques, including:

1. the strength of the attractive electric field at the intersecting planes and peaks of the pyramids is increased by introducing a DC or RF bias 48 at the substrate to introduce charge in the substrate (e.g., fig. 4 b).

2. The use of less reactive gas species in the plasma increases erosion due to direct ion bombardment on the chemical etch.

3. The gas pressure is reduced, thereby increasing the ion mean free path.

Fig. 5 illustrates preferential etching of the dielectric layer 52 at the peaks in accordance with one or more aspects of the present invention. Because the negative-like charge repulsion is in the plane of the surface on the sidewalls of the pyramid (or other geometry), but the net negative force (netnegative) will be stronger and perpendicular to the surface near the sharp intersection of two or more planes or especially at more than three planes where the spikes are formed, the charge density 56 is highest at the intersection of the geometric planes and at the spikes. Thus, the positive ions emitted by the plasma bombardment are preferably at pyramid plane crossings or spikes due to the stronger attraction between positive ions and stronger negative charges at the crossings and spikes.

The erosion of the passivating dielectric layer at the sharp peak is preferred due to several factors including the force of the electric field at the sharp peak, stress cracking at the sharp peak, directionality of ion bombardment, geometric exposure of the larger peak, and the like.

Fig. 6a-c illustrate exemplary contact structures formed to include a direct contact 65 or a tunnel barrier contact 66 in accordance with one or more aspects of the present invention.

In fig. 6b, passivation dielectric layer 62 may be etched in all ways to make direct contact openings. Alternatively, in fig. 6c, the passivation dielectric layer 62 may be thinned preferentially at the sharp peaks to form the tunnel dielectric barrier contact 66.

Fig. 7a-b illustrate contact area control in accordance with one or more aspects of the present invention. The two-dimensional open contact area through the passivation dielectric layer 72 is increased due to the vertical (Y) etch spike. Alternatively, the passivating dielectric layer may be thinned preferentially at the sharp peaks to form the tunnel dielectric barrier contact, with control over the "active" contact area.

Fig. 8a-b illustrate an alternative contact opening method using induced cracking of the dielectric layer 82 at the interface plane and peaks to reach a preferential etch path for the contact opening in accordance with one or more aspects of the present invention.

In a reactive ion etching process, stress cracks 85 can be introduced in the dielectric layer to preferentially etch along the crack interfaces. Stress cracks may be thermally induced or caused by other stresses at the intersections or peaks of the interface planes. The stress at the intersecting planes is inherently higher than the stress on the planar surfaces and can be further increased by parameters of the dielectric deposition process. The contact opening profile and area can be adjusted by varying the concentration of the reactive species and the directionality of the ion bombardment 83.

Fig. 9a-b illustrate the formation of a P-N junction 98 beneath a passivating dielectric layer in accordance with one or more aspects of the present invention. P-N junction 98 is formed beneath the passivated dielectric layer by implanting solid phase dopants 97 into the substrate from the dopant-containing conductive layer 91 through contact openings in the dielectric layer. Under thermal diffusion, the dopant atoms preferably diffuse through the locations of the thinned or etched dielectric.

Fig. 10a-d illustrate a shielded direct contact structure implemented according to one or more aspects of the present invention. A shield contact (shield contact with low carrier recombination losses) can be formed by forming a doping concentration gradient 108 that transitions from a high concentration at the interface of conductive layer 101 to a low concentration at the P-N junction within substrate 103 below contact region 105 formed by the opening in dielectric layer 102. The dopant profile shields the contacts from excessive carrier recombination losses. As mentioned above, the shield contact can be present at the intersection of two or more planes, preferably at the intersection of three or more planes, such as at the peak of the pyramid structure as shown.

Fig. 11a-d illustrate a shielded tunnel barrier contact structure implemented in accordance with one or more aspects of the invention. The shield contact may also be achieved by thinning the dielectric layer to a desired thickness (which may be between 5-50 angstroms) without opening the dielectric layer 112 so that carriers of one polarity can tunnel through to the channel of carriers of the opposite polarity while the potential barrier is present. This structure is referred to as a tunnel barrier contact 116. Alternatively, the doping gradient 118 can be formed by diffusing dopants 117 from the conductive layer 111 through the tunnel dielectric structure to further shield the contact from recombination losses.

Details of exemplary methods for manufacturing the above-described shield contact structures are described in further detail below. The solar cell substrate surface texture typically takes the form of several forms of regularly or randomly distributed micron-scale pyramidal structures. Other texture morphologies including points of conical spikes or other sharply elevated crystalline substrate structures are equally feasible. Surface texturing may be formed using any number of well-known processes including alkaline etching to produce pyramidal surfaces reflecting the crystal structure of the underlying substrate, acidic etching to produce irregular random tapered pin surface structures. In each case, the texture may be applied first with a thin (not necessarily uniform) coating of an insulating dielectric layer. The conformal dielectric layer may be deposited by a number of techniques including thermal oxidation, chemical vapor deposition, physical vapor deposition, and the like. The bottom substrate is electrically or physically exposed through the conformal dielectric layer by preferentially etching or etching the conformal dielectric layer to a desired thickness or completely off of the surface texture peaks or tips, providing a path or opening that forms a contact between the cell substrate and a conductive layer subsequently deposited on top of the dielectric layer. Prior to depositing the conductive layer, etching or etching of the dielectric layer from a plasma enhanced chemical vapor deposition Process (PECVD) for depositing the conductive layer onto the dielectric layer can be performed using several feasible semiconductor processing techniques, including a plasma Reactive Ion Etching (RIE) process or in-situ (in-situ) by ion bombardment. While the foregoing in situ process is preferred, other directed energy sources, such as lasers, may be employed to achieve selective erosion of the peak regions of the surface texture. Several exemplary techniques for preferentially eroding or etching the pyramidal peaks are described below and in, for example, fig. 3-9.

Control of the contact area through the dielectric layer can be achieved by a combination of pyramid geometry, treatment of the dielectric layer, and the intensity and directionality of the ablation energy, as follows:

1. the pyramidal peaks or pyramidal spike texture will preferentially erode or etch relative to the wall or base region due to several effects. The spike is more widely and directly exposed to etching or erosion energy from the plasma or ion beam.

2. The pyramidal texture gradually becomes more shortened as the amount of material etched away from the peaks increases. This is because the cross-sectional area of the base is increased compared to the peaks of the pyramids. In this case, the contact openings through the dielectric layer and into the substrate gradually increase. This gradually increasing contact area makes it possible to control the total amount of contact area that has been opened between the conductive layer and the substrate to a desired amount. Increasing the duration and/or intensity of the etching/ion bombardment can be used to control the contact opening area.

3. Inducing a static charge into the substrate, the charge will migrate away from the charge-like (likecharge) and thus repel the charge to the end of the substrate surface, so the charge density at the intersection of several surface planes, such as the tip of a pyramid-like spike or a tapered pin structure, will tend to be highest. The increased charge density at such a peak produces a stronger electric field at the peak, which attracts a higher ion bombardment flux than the surrounding low charge density region. Thus, a higher ion bombardment flux results in a higher etch rate of the dielectric layer at the peaks of such structures. The charging effect (chargingeffect) can be further enhanced by using a DC or RF bias in the substrate. In particular, this can be achieved in a parallel plate plasma reactor in which a bias voltage of DC or RF is applied to the plate in contact with the substrate.

4. The thermally induced stress causes cracks to enter the dielectric film prior to subjecting the substrate to the plasma, thereby preferentially etching along stress crack interfaces through the dielectric layer. The surface texture has a larger cross-sectional area at the base and becomes a dotted area at the peaks. This unique geometry is used to provide a means of controlling the contact area relative to the overall passivated surface area.

5. Plasma etch conditions are controlled that affect ion bombardment energy, direction, reactivity, and time. These parameters are easily controlled in modern plasma reactors such as PECVD or plasma etch chambers. Fig. 4-6 (by way of example) illustrate concepts described for controlling ion bombardment directionality. Alternatively, other methods using an energy beam source such as an electron beam, an ion beam, a laser, etc. can also be applied. Figures 3a-e illustrate the concept of a technique and texture using contacts that form multiple controlled cross-sectional areas between conductive layers that are successively deposited over a dielectric.

In all of the above structures, the shield electrical contact may be formed on the substrate 1) as a controlled area direct contact between the conductive layer and the substrate, and/or 2) via majority carrier transport through a controlled thin dielectric tunnel barrier. These two basic contact structures are shown in fig. 6, 10 and 11.

In the case of direct contact, the complete cross-sectional structure consists of a stack starting from a textured crystalline solar cell substrate with multiple conductive contacts through a passivating dielectric layer to an upper conductive layer, since the texture on the solar cell substrate consists of millions of pyramids or conical spikes distributed uniformly across the entire solar cell substrate surface, this structure and method provides a technique to form well-distributed contacts in the cell in a controlled cross-sectional area between the substrate and the conductive layer.

The structures described herein minimize carrier recombination in the region under the contact by several techniques. One technique is to minimize the overall contact area between the conductive layer and the substrate, ideally 0.5% to 5% relative to the overall cell area. Another technique is to shield the contacts by leaving a controlled thin dielectric passivation layer in place and relying on tunneling current through the dielectric. A third technique is to implant a high concentration of dopant through a relatively small contact area, resulting in a high concentration of dopant atoms at the contact, which reduces recombination losses by reducing the number of carriers of opposite charge near the contact.

In one embodiment, the solar cell substrate is first etched to form a pyramidal surface texture. The substrate is then coated continuously with a dielectric passivation layer. The dielectric layer is then etched from the peaks of the pyramid-like textured microstructure at the same time as or prior to depositing the conductive layer. Next, the dielectric layer is coated with a conductive layer containing a dopant. Next, the dopant contained in the conductive layer is implanted using thermally activated diffusion through the field of controlled contact openings formed in the dielectric layer at the pyramidal erosion peaks or at the spike-shaped texture surface profile. The dopants implanted through the contact openings diffuse into the continuous P-N junction in the substrate beneath the passivating dielectric layer. Low recombination losses are achieved by virtue of the very low total contact area (less than 5/100) relative to the total passivation area in combination with the dopant concentration gradient within the contact, which creates a charge polarity that repels one polarity of the carriers thereby reducing carrier recombination losses. The above-described embodiments of the present invention are highly advantageous in the manufacture of high efficiency solar cells. One such embodiment is shown in fig. 9-11.

The shielding contact structures described herein are equally suitable for use as front and back side electric fields, or as simultaneous structures in high efficiency solar cells.

According to the above-incorporated application entitled "High-efficiency solar cell structures and methods of manufacturing," a cell comprising an n-type front side, an n-type wafer, a p-type back side, a multifunctional transparent layer, a conductive layer, a highly doped silicon compound layer (or a highly doped silicon compound layer of opposite polarity) can be used in conjunction with any of the contact features of the present invention. One such embodiment is shown in FIG. 12, including the following exemplary layers:

124: front metal contact

121: transparent conductive film:

example (c):

amorphous or polycrystalline silicon carbide:

n-type silicon carbide: phosphorus-doped silicon carbide, nitrogen-doped silicon carbide,

amorphous or polycrystalline silicon:

n-type amorphous silicon: phosphorus-doped amorphous silicon, nitrogen-doped amorphous silicon,

122: electrically passivating the interfacial layer;

example (c): silicon oxide, silicon nitride, amorphous silicon, silicon carbide, aluminum oxide, aluminum nitride;

123: n-type crystalline silicon wafer

Thickness in the range w < 300 μm, basic resistivity of n-type wafer 0.5Ohmcm < rho <10Ohmcm, basic resistivity of p-type wafer 0.1Ohmcm < rho <100Ohmcm

222: electrically passivating the interfacial layer;

example (c): silicon oxide, silicon nitride, amorphous silicon, intrinsic silicon carbide, aluminum oxide, aluminum nitride;

221: transparent conductive film

Example (c):

amorphous or polycrystalline silicon carbide:

p-type silicon carbide: boron-doped silicon carbide, aluminum-doped silicon carbide, gallium-doped silicon carbide.

Amorphous or polycrystalline silicon:

p-type amorphous silicon: a boron-doped amorphous silicon, an aluminum-doped amorphous silicon, a gallium-doped amorphous silicon.

224: back metal

The layers described in the above solar cell structures can be deposited or grown using standard methods like PECVD, APCVD, LPCVD, PVD, plating, etc. For some layers and combinations of layers, innovative methods of making the layers and structures are necessary.

In order to achieve a high efficiency solar cell using a cost efficient manufacturing method, it is advantageous to deposit films of different properties on only one side. While this is very difficult and nearly impossible to do, for standard tube furnace deposition of polysilicon, such as LPCVD deposition, PECVD deposition can be done on one side of the wafer without deposition on the other side. Although PECVD tools are available at industrial level, they operate only at temperature conditions that enable the deposition of amorphous or microcrystalline silicon layers. In the described cell structure, the amorphous silicon layer can be changed into a polycrystalline silicon layer by heat treatment. This also applies to compounds or the like that dope amorphous silicon layers or amorphous silicon carbide. This recrystallization negatively affects the passivation quality of the silicon/amorphous silicon interface layer in the case where it is present in the cell structure. However, the wafer surface is buffered with a crystalline polysilicon layer by an insulator. In this way, the interface is still passivated after the heat treatment and the layer system is stable at high temperatures. During the crystallization process, many properties of the layer change: activating donors or acceptors, increasing light transmission, and hydrogen overflow from the layer.

In addition to the solar cell examples disclosed herein, the invention extends to any type of integrated semiconductor circuit having layers requiring conductive contacts.

In summary, particular aspects of the invention include, but are not limited to:

shielded electrical contacts, structures, and methods of manufacture extend through a passivating dielectric layer in a high efficiency crystalline solar cell.

A shield contact through a passivating dielectric formed by modifying geometric features of a surface texture formed on a solar cell substrate.

A shielding contact structure and a method of forming a front side electric field and/or a back side electric field.

Contact structures and methods for passivating a dielectric layer that is fully continuous over a substrate except only at controlled contact openings on a geometric texture structure.

Contact structures and methods capable of controllably achieving a total contact area of between 0.5-5% by selectively etching a dielectric layer coated on a surface texture of a solar cell substrate.

Contact structures and methods having controlled area coverage across the surface area of a solar cell substrate to a total contact area distributed at a uniform overall density that is between 0.5-5% can be controllably achieved by selectively etching controlled areas of a dielectric layer coated on a geometric surface texture of the solar cell substrate.

Contact structures and methods capable of controllably achieving a total contact area of between 0.5-5% by selectively etching controlled areas of a dielectric layer coated on a geometric surface texture of a solar cell substrate by plasma ion bombardment or reactive ion etching.

Contact structures and methods capable of controllably achieving a total contact area of between 0.5-5% by selectively etching controlled areas of a dielectric layer coated on a geometric surface texture of a solar cell substrate by directional ablation energy, such as a laser.

A shield contact through the passivation dielectric formed by modifying the geometry of the surface texture on the solar cell substrate prior to depositing the conductive layer.

A shield contact through the passivation dielectric formed by modifying the geometry of the surface texture on the solar cell substrate while depositing the conductive layer.

Contacts through the passivation dielectric are formed by controlling contact opening areas in the dielectric layer with the geometry of the texture structures to modify the geometry of the surface texture on the solar cell substrate.

The geometry of the texture structure, which is larger at the bottom and converges to a sharp peak or spiked tip, allows the contact opening area to gradually increase as the peak or spiked peak is gradually eroded away.

The geometry of the texture features are pyramidal, tapered pins, or other contacts through the passivation dielectric that protrude entirely beyond the crystalline solar cell substrate less than an angle comprising 180 degrees.

Is a contact structure of a shielded direct contact or a thin dielectric tunnel barrier contact between a solar cell substrate and a conductive layer.

The contact opening area through the passivation dielectric is not highly dependent on the contact and method of manufacture having a geometric texture of uniform height, including a pyramidal or tapered pin structure.

A contact structure and method in which a P-N junction is formed in a substrate beneath a passivating dielectric layer.

Contact structures and fabrication methods for forming a P-N junction in a substrate beneath a passivating dielectric layer via diffusion or implantation of dopants from a conductive layer containing dopants through controlled openings in the passivating dielectric layer.

Contact structures and methods are shielded direct contacts or thin dielectric tunnel barrier contacts between a solar cell substrate and a conductive layer, which contact structures and methods are further shielded by injecting or diffusing dopants from the conductive layer through a contact opening or through a tunnel barrier into the substrate below the contact.

Contact structures and methods that are further shielded by implanting or diffusing dopants from a conductive layer into the substrate below the contact through the contact opening or through the tunnel barrier and forming a dopant concentration gradient within the contact.

A contact through the passivation dielectric formed by preferentially etching the dielectric layer at the peaks of the geometric features of the surface texture due to greater physical exposure to etching energy, such as ion bombardment.

Contacts through the passivation dielectric formed by modifying the geometry of the texture on the solar cell substrate by utilizing charges or electric fields concentrated due to the geometry of the surface texture to preferentially erode the dielectric layer over specific regions of the texture.

Structures and methods that maximize dopant diffusion depth at the peaks and intersection planes compared to the flat surfaces and valleys, thereby forming P-N junctions furthest from the peaks and intersection planes, thus facilitating devices with minimized surface recombination.

Contacts through the passivation dielectric are formed by etching the dielectric layer with charges or electric fields concentrated due to the geometry and charging capacity of the structure to preferentially follow the intersection of two or more geometric planes of the surface texture on the solar cell substrate.

A contact through a passivating dielectric formed by preferentially eroding the dielectric layer at a peak formed at an intersection of three or more geometric planes of a surface texture on a solar cell substrate by preferentially eroding the dielectric layer over a particular region of the texture with a charge or electric field concentrated due to the geometry of the texture.

Stress cracks in the dielectric layer introduced in a reactive ion etching process to enhance preferential etching along crack interfaces.

Stress cracks that are located at the intersection or peak of two or more interface planes due to the intrinsically higher stress at the intersection of the planes and are further increased by the parameters of the dielectric deposition process used to enhance the preferential etching of the surface texture.

The process flows described herein are examples only. Many changes may be made to these diagrams or the steps (or operations) described therein without departing from the spirit of the invention. For example, the steps may be performed in a differing order, or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention.

Although preferred embodiments have been depicted and described in detail herein, it will be apparent to those skilled in the relevant art that various modifications, additions, substitutions and the like can be made without departing from the spirit of the invention and these are therefore considered to be within the scope of the invention as defined in the following claims.

Claims (9)

1. A method of forming a shielded electrical contact through a passivating dielectric layer in a high efficiency crystalline solar cell, comprising:

providing a substrate comprising a geometric texture protruding from the substrate, the geometric texture having a shape comprising a spike, the spike defined at least in part by an angle comprising less than 180 degrees,

a passivating dielectric layer is provided substantially continuously over the substrate,

forming a controlled contact opening through the passivating dielectric layer to the peak of the geometric texture of the substrate, the forming including introducing an electrical bias into the substrate to preferentially increase an electric field strength of the peak, the increased electric field strength facilitating preferential removal of the passivating dielectric layer from over the peak.

2. The method of claim 1, wherein forming the controlled contact opening through the passivating dielectric layer further comprises selectively etching a controlled region of the dielectric layer by plasma ion bombardment or reactive ion etching.

3. The method of claim 1, wherein forming the controlled contact opening through the dielectric layer further comprises selectively etching a controlled region of the dielectric layer using directional ablation energy.

4. The method of claim 1, wherein the shape of the geometric texture is larger at the bottom and converges to the peak, the shape helping to cause a surface area of the controlled contact opening to gradually increase as the passivating dielectric layer is preferentially removed.

5. The method of any of claims 1-4, further comprising forming a P-N junction in the substrate below the passivating dielectric layer.

6. The method of claim 5, wherein the P-N junction is formed via diffusion or implantation of dopants from a dopant-containing conductive layer through the controlled contact opening in the passivating dielectric layer.

7. The method of claim 6, wherein the dopant diffusion depth is greatest at an intersection plane of the peak and the geometric texture forming the contact opening and smallest at a bottom of the geometric texture, thereby forming the P-N junction furthest from the peak and intersection plane, thereby providing minimized surface recombination.

8. The method of any of claims 1-4, introducing an electrical bias into the substrate further comprising preferentially increasing an electric field strength at an intersection of two or more surfaces of the geometric texture structure, the increased electric field strength facilitating preferential removal of the passivating dielectric layer from over the intersection of the two or more surfaces, the intersection of the two or more surfaces being the spike.

9. The method of claim 8, wherein the geometry and charging capacity of the geometric texture facilitates preferentially increasing the electric field strength at an intersection of two or more surfaces of the geometric texture.