HK1191753A - Compensation for lane imbalance in a multi-lane analog-to-digital converter (adc) - Google Patents

Abstract

The invention relates to a compensation for lane imbalance in a multi-lane Analog-to-Digital Converter (ADC). Various multi-lane ADCs are disclosed that substantially compensate for impairments present within various signals that result from various impairments, such as phase offset, amplitude offset, and/or DC offset to provide some examples, such that their respective digital output samples accurately represent their respective analog inputs. Generally, the various multi-lane ADCs determine various statistical relationships, such as various correlations to provide an example, between these various signals and various known calibration signals to quantify the phase offset, amplitude offset, and/or DC offset that may be present within the various signals. The various multi-lane ADCs adjust the various signals to substantially compensate for the phase offset, amplitude offset, and/or DC offset based upon these various statistical relationships such that their respective digital output samples accurately represent their respective analog inputs.

Description

Compensation for channel imbalance in a multi-channel analog-to-digital converter (ADC)

CROSS-REFERENCE TO RELATED APPLICATIONS

Priority of the present application claims us patent application 61/664,858 filed on day 6, 27, 2012 and us patent application 13/553,017 filed on day 7, 19, 2012, the entire contents of which are incorporated herein by reference.

Technical Field

The present disclosure relates to analog-to-digital conversion, and more particularly, to compensation of various impairments in multiple channels of a multi-channel (multi-lane) analog-to-digital converter (ADC).

Background

Data converters are often used in mixed signal electronic systems. Mixed signal electronic systems include both the analog signal domain and the digital signal domain. The analog signal domain operates primarily on analog signals, while the digital signal domain operates primarily on digital signals. There is a need for a mechanism to transfer signals from one domain, such as the analog signal domain, to another domain, such as the digital signal domain. Typically, an analog-to-digital converter (ADC) is used to convert an analog signal from the analog signal domain to a digital signal for the digital signal domain.

Conventional multi-channel ADCs sample an analog signal at different times using multiple phases of a sampling clock, convert the samples from the analog signal domain to the digital signal domain, and recombine the digital samples to generate a digital signal. Typically, a conventional multi-channel ADC includes a plurality of ADCs, also referred to as multiple channels, to sample and convert an analog signal from an analog signal domain to a digital signal domain. The plurality of ADCs collectively sample the analog signals staggered in time, each at a rate below the Nyquist frequency of the analog signal, but generally at a rate equal to or exceeding the Nyquist frequency.

However, impairments within a conventional multi-channel ADC may cause impairments within the various signals of the conventional multi-channel, such as amplitude offsets, Direct Current (DC) offsets, and/or phase offsets, which may cause the digital signal to no longer accurately represent the analog signal. For example, the impairments may result from unknown offsets between multiple phases of the sampling clock, linear imperfections within various channels in multiple channels of a conventional multi-channel ADC, DC offsets between various channels, and/or amplitude offsets between various channels.

Disclosure of Invention

According to an aspect of the invention, there is provided a multi-channel analog-to-digital converter (ADC) configured to convert an analog input from an analog signal domain to a digital signal domain to provide digital output samples, the ADC comprising: a plurality of ADCs configured to convert an analog input from the analog signal domain to the digital signal domain to provide a plurality of digital output segments, the plurality of ADCs configured to sample the analog input using a corresponding one of a plurality of phases of a sampling clock, the plurality of phases being offset from one another; a switching module configured to interleave (interleave) the plurality of digital output segments to provide the digital output samples; and an impairment detection module configured to determine a statistical relationship between the plurality of digital output segments and a calibration signal to quantify impairments within the plurality of ADCs.

Wherein the statistical relationship is a correlation between the plurality of digital output segments and the calibration signal.

Wherein the damage comprises at least one selected from the group consisting of: a phase offset between at least one of the phases of the plurality of phases and the calibration signal; an amplitude offset between at least a first one of the digital output segments and the calibration signal; and a Direct Current (DC) offset between at least a second one of the digital output segments and the calibration signal.

Wherein the calibration signal is a sinusoidal signal having a known frequency.

Wherein the impairment detection module is further configured to provide a plurality of impairment correction signals based on the statistical relationship, and further comprises: a phase adjustment module configured to adjust a phase of at least one of the plurality of phases based on a corresponding first impairment correction signal of the plurality of impairment correction signals; and a gain/offset adjustment module configured to adjust an amplitude and a direct current offset (DC) of at least one of the plurality of digital output segments based on a corresponding second impairment correction signal of the plurality of impairment correction signals.

Wherein the impairment detection module is further configured to provide a plurality of impairment correction signals based on the statistical relationship, and further comprises: a coefficient generator module configured to provide a plurality of sets of correction coefficients based on the plurality of impairment correction signals; and a plurality of tapped-delay-line modules coupled to the plurality of ADCs and configured to compensate for the impairments within the plurality of digital output segments by weighting their respective taps using the plurality of sets of correction coefficients to provide a plurality of compensated digital output segments, wherein the switching module is further configured to interleave the plurality of compensated digital output segments to provide the digital output samples.

Wherein the coefficient generator module is further configured to update the plurality of sets of correction coefficients using an adaptive algorithm that produces a result that minimizes an error between the plurality of digital output segments and the calibration signal.

Wherein the impairment detection module is further configured to designate one of the plurality of digital output segments as a reference channel and to compare the statistical relationship of other digital output segments to the statistical relationship of the reference channel to quantify the impairment of the other digital output segments relative to the reference channel.

Wherein the statistical relationship is a correlation between the plurality of digital output segments and the calibration signal.

According to another aspect of the invention, there is provided a multi-channel analog-to-digital converter (ADC) configured to convert an analog input from an analog signal domain to a digital signal domain to provide digital output samples, the ADC comprising: a plurality of ADCs configured to convert the analog input from the analog signal domain to the digital signal domain to provide a plurality of digital output segments, the plurality of ADCs configured to sample the analog input using a corresponding phase of a plurality of phases of a sampling clock, the plurality of phases being offset from each other; a coefficient generator module configured to provide a plurality of sets of correction coefficients based on statistical relationships between the plurality of digital output segments and the calibration signal; and a plurality of tapped delay line modules coupled to the plurality of ADCs and configured to weight their respective taps using the plurality of sets of correction coefficients to compensate for impairments within the plurality of digital output segments to provide a plurality of compensated digital output segments, a switching module configured to interleave the plurality of compensated digital output segments to provide the digital output samples.

Wherein the statistical relationship is a correlation between the plurality of digital output segments and the calibration signal.

The multi-channel ADC further includes: a impairment detection module configured to determine a statistical relationship between the plurality of digital output segments and the calibration signal to quantify the impairment within the plurality of digital output segments.

Wherein the impairment detection module is further configured to designate one of the plurality of digital output segments as a reference channel and to compare the statistical relationship of other digital output segments to the statistical relationship of the reference channel to quantify the impairment relative to other digital output segments of the reference channel.

Wherein the statistical relationship is a correlation between the plurality of digital output segments and the calibration signal.

Wherein the damage comprises at least one selected from the group consisting of: a phase offset between at least one of the phases of the plurality of phases and the calibration signal; and an amplitude offset between at least a first one of the digital output segments and the calibration signal.

The multi-channel ADC further includes: an offset detection module configured to determine Direct Current (DC) offsets between the plurality of digital output segments and the calibration signal to provide a plurality of DC offset signals; and a plurality of combining modules configured to combine the plurality of digital output segments and the plurality of DC offset signals to provide a plurality of offset corrected output segments, wherein the plurality of tapped delay line modules are further configured to compensate for impairments in the plurality of offset corrected outputs.

Wherein the plurality of tapped delay line modules are implemented as part of a plurality of adaptive equalizers configured to compensate for impairments within the plurality of digital output segments by adjusting their impulse responses using the plurality of sets of correction coefficients.

According to another aspect of the present invention, there is provided a multi-channel analog-to-digital converter (ADC) configured to convert an analog input from an analog signal domain to a digital signal domain to provide digital output samples, the ADC comprising: a plurality of ADCs configured to convert the analog input from the analog signal domain to the digital signal domain to provide a plurality of digital output segments, the plurality of ADCs configured to use a corresponding phase of a plurality of phases of a sampling clock to sample the analog input, the plurality of phases being offset from each other; a impairment detection module configured to determine a statistical relationship between the plurality of digital output segments and a calibration signal to quantify impairments within the plurality of digital output segments; a plurality of phase adjustment modules configured to adjust phases of the plurality of phases based on the statistical relationship to compensate for the impairments within the plurality of digital output segments; a plurality of gain/offset adjustment modules coupled to the plurality of ADCs configured to adjust amplitudes and direct current offsets (DCs) of the plurality of digital output segments based on the statistical relationship to provide a plurality of compensated digital output segments; and a switching module configured to interleave the plurality of compensated digital output segments to provide the digital output samples.

Wherein the statistical relationship is a correlation between the plurality of digital output segments and the calibration signal.

Wherein the impairment detection module is further configured to designate one of the plurality of digital output segments as a reference channel and to compare the statistical relationship of other digital output segments to the statistical relationship of the reference channel to quantify the impairment relative to other digital output segments of the reference channel.

Drawings

Embodiments of the present disclosure are described with reference to the accompanying drawings. In the drawings, like reference numbers can indicate identical or functionally similar elements. Further, the left-most digit(s) of a reference number identifies the drawing in which the reference number first appears.

FIG. 1 shows a block diagram of a conventional multi-channel analog-to-digital converter (ADC);

FIG. 2A illustrates a conventional plurality of optimal phases of a sampling clock used in a conventional multi-channel ADC;

FIG. 2B illustrates sampling of an analog input by a conventional multi-channel ADC using a conventional plurality of optimal phases of a sampling clock;

FIG. 3A illustrates a conventional plurality of non-optimal phases of a sampling clock that may be used in a conventional multi-channel ADC;

FIG. 3B illustrates sampling of an analog input by a conventional multi-channel ADC using a conventional plurality of non-optimal phases of a sampling clock;

FIG. 4 shows a block diagram of a multi-channel ADC according to an example embodiment of the present disclosure;

FIG. 5 shows a block diagram of an exemplary impairment detection module that may be used in a multi-channel ADC according to an exemplary embodiment of the present disclosure;

FIG. 6 shows a block diagram of an exemplary tone correlator (tone correlator) that may be used in the impairment detection module according to an exemplary embodiment of the present disclosure; and

fig. 7 shows a block diagram of a second multi-channel analog-to-digital converter (ADC) according to an exemplary embodiment of the present disclosure.

The present disclosure will be described with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical or functionally similar elements and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the reference number.

Detailed Description

The following detailed description refers to the accompanying drawings that illustrate exemplary embodiments consistent with this disclosure. References in the detailed description to "one exemplary embodiment," "an exemplary embodiment," etc., indicate that the exemplary embodiment described may include a particular feature, structure, or characteristic, but every exemplary embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same exemplary embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an exemplary embodiment, it is within the knowledge of one skilled in the relevant art to affect such feature, structure, or characteristic in connection with other exemplary embodiments whether or not explicitly described.

The exemplary embodiments described herein are for purposes of illustration and are not intended to be limiting. Other exemplary embodiments are possible, and modifications to the exemplary embodiments are possible within the spirit and scope of this disclosure. Therefore, the detailed description is not meant to limit the disclosure. Rather, the scope of the invention is to be defined only by the following claims and their equivalents.

Embodiments of the present disclosure may be implemented in hardware, firmware, software, or any combination thereof. Embodiments of the disclosure may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by one or more processors. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing device). For example, a machine-readable medium may include Read Only Memory (ROM); random Access Memory (RAM); a magnetic disk storage medium; an optical storage medium; a flash memory device; electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.), and others. Further, firmware, software, programs, instructions may be described herein as performing certain actions. However, it should be understood that such descriptions are merely for convenience and that such actions in fact result from computing devices, processors, controllers, or other devices executing the firmware, software, programs, instructions, etc.

The following detailed description of exemplary embodiments will sufficiently disclose the general nature of the disclosure to enable others, by applying knowledge of one skilled in the art, to readily modify and/or adapt for various applications such as exemplary embodiments without undue experimentation, without departing from the spirit and scope of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning of exemplary embodiments and their numerous equivalents based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings herein.

For purposes of discussion, the term "module" should be understood to include at least one of software, firmware, and hardware (e.g., one or more of a circuit, microchip, or device, or any combination thereof), and any combination thereof. Further, it should be understood that each module may include one or more components within the actual device, and each component forming a portion of the module described above may function cooperatively or independently of any other component forming a portion of the module. Rather, the various modules described herein may represent a single component within an actual device. Further, the components within a module may be in a single device, or distributed among multiple devices in a wired or wireless manner.

Conventional multi-channel analog-to-digital converter (ADC)

Fig. 1 shows a block diagram of a conventional multi-channel analog-to-digital converter (ADC). The conventional multi-channel ADC100 converts the analog input 150 from a first signal domain (e.g., an analog signal domain) to a second signal domain (e.g., a digital signal domain). The conventional multi-channel ADC100 utilizes multiple phases of a sampling clock to sample the analog input 150 at different times, convert the samples from the analog signal domain to the digital signal domain, and recombine the digital samples to produce digital output samples 154. The conventional multi-channel ADC100 includes ADCs 102.1 through 102.i and a switch module 104.

The switching module 104 combines or interleaves the digital output segments 152.1 through 152.i to produce digital output samples 154. After analog signal domain to digital signal domain conversion by ADC102.1, switch module 104 provides digital output segment 152.1 as a first sample of digital output samples 154. The switch module 104 thereafter provides the digital output section 152.2 as a second sample of the digital output samples 154 after conversion from the analog signal domain to the digital signal domain by the ADC 102.2. After conversion of the analog signal domain to the digital signal domain by the adc102.i, the switch module 104 provides the digital output segment 152.i as a sample of the digital output samples 154.

In general, the ADCs 102.1 through 102.i are responsive to multiple phases φ of the sampling clock₁To phi_iThe analog input 150 is converted from the analog signal domain to the digital signal domain to provide digital output segments 152.1 through 152. i. In particular, ADCs 102.1 through 102.i use multiple phases φ of the sampling clock₁To phi_iAnalog input 150 is sampled at each optimal sampling point. E.g., when they correspond to multiple phases of the sampling clock phi₁To phi_iWhen characterized as being in a logic state, ADCs 102.1 through 102.i sample analog input 150. Typically, ADCs 102.1 through 102.i collectively sample the time-staggered analog inputs 150, each at a rate that is below the nyquist frequency of analog input 150, but generally at a rate that equals or exceeds the nyquist frequency. ADCs 102.1 through 102.i convert the sampled representation of analog input 150 from the analog signal domain to the digital signal domain to provide digital output segments 152.1 through 152. i.

Optimum phase of sampling clock

Fig. 2A illustrates a conventional plurality of optimal phases of a sampling clock that may be used in a conventional multi-channel ADC. Ideally, as shown in FIG. 2A, multiple phases φ of the sampling clock₁To phi_iAre characterized as having similar frequencies, but are phase-shifted from each other. E.g. multiple phases phi of the sampling clock₁To phi_iThe frequency of each is given by:

wherein f is_NYQRepresenting the nyquist frequency of the analog input 150 and i representing the number of channels of a conventional multi-channel ADC, i.e. the number of ADCs 102.1 to 102. i. Multiple phases phi of the sampling clock₁To phi_iIs characterized by a phase offset between adjacent phases of:

where i represents the number of channels of a conventional multi-channel ADC.

Fig. 2B shows analog input sampling by a conventional multi-channel ADC using a conventional plurality of optimal phases of the sampling clock. Multiple ADCs, such as ADCs 102.1 through 102.i, of a conventional multi-channel ADC, such as conventional multi-channel ADC100, use multiple phases φ of a sampling clock₁To phi_iThe analog inputs, such as analog input 150, are sampled and converted together, and then combined or interleaved to produce digital output samples, such as digital output samples 154.

As shown in FIG. 2B, a first ADC of the plurality of ADCs uses the phase φ of the sampling clock₁Analog input 150 is sampled at its optimal sampling point X to provide an optimally sampled analog input 250.1. A second ADC of the plurality of ADCs uses the phase phi of the sampling clock₂Analog input 150 is sampled at its optimal sampling point X to provide an optimally sampled analog input 250.2. An ith ADC of the plurality of ADCs using a phase phi of the sampling clock_iThe analog input 150 is sampled at its optimal sampling point X to provide an optimally sampled analog input 250. i. The plurality of ADCs then convert their optimum sampling points X from the analog signal domain to the digital signal domain to provide a digital output section, e.g., digital output section 152.1 through 152.i which are then combined or interleaved to produce digital input samples 154 that most accurately represent the analog input 150.

Non-optimal phase of sampling clock

However, impairments within the conventional multi-channel ADC100 may cause impairments within the various signals of the conventional multi-channel ADC100, such as amplitude offsets, Direct Current (DC) offsets, and/or phase offsets, which may cause the digital output samples 154 to no longer accurately represent the analog input 150. Impairments may result from multiple phases phi of the sampling clock₁To phi_iUnknown offsets therebetween, linearity imperfections within various channels in the multiple channels of the conventional multi-channel ADC100, DC offsets between various channels, amplitude offsets between various channels, and/or any other suitable impairments that may be apparent to one skilled in the relevant art(s) without departing from the spirit and scope of the invention.

Fig. 3A illustrates a conventional plurality of non-optimal phases of a sampling clock that may be used in a conventional multi-channel ADC. As discussed in FIG. 2A, preferably, multiple phases φ of the sampling clock₁To phi_iAre characterized as being offset from each other by similar amounts. In practice, however, impairments within the conventional multi-channel ADC100 may result in multiple phases φ of the sampling clock₁To phi_iAre characterized as being offset in phase from each other by different amounts. Multiple phases phi of the sampling clock₁To phi_iIs characterized by a phase offset between adjacent phases of:

wherein i represents a conventional multiNumber of channels of channel ADC, and δ_iIndicating the presence of a phase phi in the sampling clock_iIs unknown. Typically, the multiple phases of the sampling clock φ₁To phi_iAre characterized as having a corresponding unknown offset delta₁To delta_i. Unknown offset delta₁To delta_iMay result in multiple phases phi of their corresponding sampling clocks₁To phi_iFrom their respective optimum phase phi of the sampling clock₁To phi_i. For example, an unknown offset δ₁To delta_iMay result in multiple phases phi of their corresponding sampling clocks₁To phi_iThe optimum phase phi of the sampling clocks that are slower or faster than their counterparts₁To phi_i. As a result, the ADCs 102.1 through 102.i use these faster and/or slower sampling clocks for multiple phases φ₁To phi_iTo sample the analog input segments 152.1 through 152.i at non-optimal sampling points.

Fig. 3B illustrates analog input sampling by a conventional multi-channel ADC using a conventional plurality of non-optimal phases of the sampling clock. Multiple ADCs, such as ADCs 102.1 through 102.i, of a conventional multi-channel ADC, such as conventional multi-channel ADC100, use multiple phases φ of a sampling clock₁To phi_iThe analog inputs, such as analog input 150, are sampled and converted together, and then combined or interleaved to produce digital output samples, such as digital output samples 154.

As shown in FIG. 3B, various impairments within a conventional multi-channel ADC may result in a phase φ using a sampling clock₁A first ADC of the plurality of ADCs samples the analog input 150 at its non-optimal sampling point O to provide a non-optimally sampled analog input 350.1, and an ith ADC of the plurality of ADCs uses the phase of the sampling clock phi_iAnalog input 150 is processed at its non-optimal sampling point O to provide non-optimally sampled analog input 350. i. Non-optimal sampling points O of the non-optimally sampled analog inputs 350.1 through 350.i lead or lag the unknown offset δ of their respective optimal sampling points X of the optimally sampled analog inputs 250.1 through 250.i₁To delta_i. For example, the non-optimal sampling point O of the non-optimally sampled analog input 350.1 lags (i.e., occurs later in time) its respective optimal sampling point X of the optimally sampled analog input 250.1 by an unknown offset δ₁. As another example, the non-optimal sampling points O of the optimally sampled analog inputs 250.i are advanced (i.e., occur earlier in time) than their respective optimal sampling points X of the optimally sampled analog inputs 250.i by an unknown offset δ_i. The lead and/or lag of the non-optimal sampling point O and the optimal sampling point X may cause the non-optimal sampling point O to no longer accurately represent the analog input 150 when combined or interleaved.

Furthermore, other impairments within a conventional multi-channel ADC may cause the non-optimal sample points O to no longer accurately represent the analog input 150 when combined or interleaved. These other impairments within a multi-channel ADC may result in amplitude offsets and/or DC offsets within the various signals within a conventional multi-channel ADC. For example, as shown in fig. 3B, impairments in the first through ith ADCs may result in a gain Δ G of the analog input 150 with unknown amplitude offset₁To Δ G_i. Furthermore, these impairments within the multi-channel ADC may cause an undesirable DC offset to exist within the analog input 150. Unknown gain Δ G₁To Δ G_iAnd/or an undesirable DC offset may cause the non-optimal sampling points O to no longer accurately represent the analog input 150 when combined or interleaved.

Multi-channel analog-to-digital converter (ADC)

The various multi-channel ADCs of the present disclosure substantially compensate for impairments, such as phase offsets, amplitude offsets, and/or DC offsets, present within the various signals that result from the various impairments such that their respective digital output samples accurately represent their respective analog inputs. In general, various multi-channel ADCs of the present disclosure determine various statistical relationships (e.g., various correlations) between these various signals and various known calibration signals to better quantify phase offsets, amplitude offsets, and/or DC offsets that may be present within the various signals. The various multi-channel ADCs adjust the various signals to adequately compensate for these offsets based on these statistical relationships so that their respective digital output samples accurately represent their respective analog inputs.

Analog compensation of impairments within a multi-channel ADC

Fig. 4 shows a block diagram of a multi-channel ADC according to an exemplary embodiment of the present disclosure. The multi-channel ADC400 converts the analog input 150 from the analog signal domain to the digital signal domain in the normal operating mode. In a normal operating mode, the multi-channel ADC400 samples the analog input 150 at different times using multiple phases of a sampling clock, converts the samples from the analog signal domain to the digital signal domain, and recombines the digital samples to produce digital output samples 154.

Optionally, in the calibration mode of operation, the multi-channel ADC400 determines various statistical relationships, e.g., various correlations, between these digital signals and various known calibration signals, thereby well quantifying the impairments that may be present within the various digital samples. The multi-channel ADC400 determines the phase offset, amplitude offset, and/or DC offset signals based on these various statistical relationships. These various phase offset, amplitude offset, and/or DC offset signals are used by the multi-channel ADC400 to compensate for the amplitude offset, DC offset, and/or phase offset present within the various signals of the multi-channel ADC400 in the analog domain. The multi-channel ADC400 includes ADCs 102.1 through 102.i, a switching module 104, a second switching module 402, a damage detection module 404, phase adjustment modules 406.1 through 406.i, and gain/offset adjustment modules 408.1 through 408. i.

The second switching module 402 selects between the analog input 150 in the normal mode of operation and the calibration signal 450 in the calibration mode of operation to provide the analog input 452. The calibration signal 450 represents a reference signal, such as a sinusoidal signal, that may be used to detect various amplitude offsets, DC offsets, and/or phase offsets present within the various signals of the multi-channel ADC400 resulting from various impairments within the multi-channel ADC 400. In general, calibration signal 450 is characterized as having a known amplitude, a known DC offset, and/or a known phase that can be compared to various signals to quantify the amplitude offset, DC offset, and/or phase offset present within these various signals. In some cases, the calibration signal 450 may be characterized as having a single frequency or a single frequency range, thereby quantifying amplitude offsets, DC offsets, and/or phase offsets present at the single frequency or within the single frequency range. In other cases, the calibration signal 450 may be characterized as having multiple frequencies or multiple frequency ranges, thereby quantifying amplitude offsets, DC offsets, and/or phase offsets present within the multiple frequencies or multiple frequency ranges.

ADCs 102.1-102. i respond to multiple time-sequenced phases of sampling clockToThe analog input 452 is converted from the analog signal domain to the digital signal domain to provide digital output segments 454.1 through 454. i. Specifically, ADCs 102.1 through 102.i use multiple time-aligned phases of a sampling clockToThe analog input 452 is sampled at each optimal sampling point. The ADCs 102.1 to 102.i convert the sampled representation of the analog input 452 from the analog signal domain to the digital signal domain, providing digital output segments 454.1 to 454. i.

The impairment detection module 404 quantifies amplitude offsets, DC offsets, and/or phase offsets present within various signals of the multi-channel ADC400 that result from various impairments within the multi-channel ADC 400. In general, the impairment detection module 404 determines statistical relationships, e.g., correlations, between the calibration signal 450 and various signals within the multi-channel ADC 400. For example, the impairment detection module 404 determines a correlation between the calibration signal 450 and the digital output segments 454.1 through 454.i to quantify the presence of correlation in the digital output segments 454.1 through 454.iInner unknown offset δ as described in FIG. 3B₁To delta_iUnknown gain Δ G₁To Δ G_iAnd/or an unknown DC offset. Further, in this example, the impairment detection module 404 may designate one of the digital output segments 454.1 through 454.i as a reference channel and compare the correlation of the other digital output segments 454.1 through 454.i to the correlation of the reference channel to quantify the unknown offset δ as depicted in fig. 3B that is present within the digital output segments 454.1 through 454.i₁To delta_iUnknown gain Δ G₁To Δ G_iAnd/or unknown DC offset. The impairment detection module 404 provides impairment correction signals 456.1 through 456.i to the various modules within the multi-channel ADC400 to compensate for amplitude offsets, DC offsets and/or phase offsets present within these various signals.

Exemplary phase offset estimation

A single tone signal at carrier frequency fc with analog distortion, e.g. calibration signal 450, can be written as:

r(t)=(1+β)Acos(2πf_c(t+τ))+d, （4）

where τ represents a phase or time offset, β represents an amplitude offset, and d represents a DC offset. When r (t) is correlated with a single tone signal with random initial phase, the average of the resulting signal is proportional to the time offset τ, as follows:

it is directly calculated further:

in practice, a single tone signal is applied to the multi-channel ADC400 in the calibration mode of operation. The various outputs, i.e., digital output segments 454.1 through 454.i, of the various channels of the multi-channel ADC400 are continuously measured by the impairment detection module 404. As a result, the random initial phase of the single tone signal is generally the same for each channel and can be eliminated by identifying one of the channels as a reference channel and referencing the random initial phase present on the other channels against the reference channel. Furthermore, a single tone may sweep a set of frequencies fc (k) to derive at least a least squares time offset by measurement:

sin(2πf_c(k)τ(j)-θ(k)),cos(2πf_c(k)τ(j)-θ(k)) （9）

by mixing r_j(f_c(k) T) is defined as having a frequency f_c(k) J, of the various channels of the multi-channel ADC400, of the tone, E_S(f_c(k) τ (j)) and E_C(f_c(k) τ (j)) is defined as the output of the impairment detection module 404 corresponding to the j-th channel to define the sum θ (k) as the input sequence, i.e., e.g., the random initial phase offset between the analog input 452, and the single tone signal, then:

s(f_c(k),j,t)=r_j(f_c(k),t)*sin(2πf_c(k)t+θ_k) （10）

c(f_c(k),j,t)=r_j(f_c(k),t)*cos(2πf_c(k)t+θ_k) （11）

measurement ofCan be evaluated by evaluating sin^-1(Q(f_c(k) τ (j))). However, this operation is achieved byConvolving (wrap) with the quantityIs limited toAnd it can cause phase discontinuities in different channel observations. Therefore, the phase should be spread out in all channels so that the linear relationship isIs suitable. For example, angles in the second quadrant π - θ will convolve into θ, while angles in the third quadrant π + θ will convolve into- θ. Real part I (f)_c(k) τ (j)) and imaginary component Q (f)_c(k) τ (j)) are changed to spread the phases.

By definitionThe phase unwrapping procedure may be described as:

after phase unwrapping, the common phase θ (k) can be removed by subtracting the reference channel and estimating the timing offset τ by a least squares estimation given as:

wherein N is_fcIndicating the number of pitch measurements. In a practical design, the averaging process may be implemented by linear filtering as defined below:

in some cases, the frequency response of the filter is not approximateUnity gain at DC. Thus, the filter output may passScaling to normalize (normalization) to unity gain. Further, when ξ =2 α, the filter approximates a standard leaky wave averaging filter (steady leaky average filter).

Exemplary gain offset estimation

The gain offset estimate may be obtained by measuring the average energy of one of the channels and comparing it to a reference channel, as follows:

G(f_c(k),j)=E{s²(fc(k),j,t)+c²(fc(k),j,t)} （21）

alternatively, the gain offset estimate may be estimated by measuring the amplitude of the output of one of the pitch correlators 506.1 to 506.i and comparing it to a reference channel, where:

exemplary DC offset estimation

The DC offset of the various channels can be measured using the digital sequence 550.1 to 550. i. Assuming that the DC offset is constant for each of the various channels, the DC offset may be averaged over multiple tone measurements, as follows:

in addition, the impairment detection module 404 may provide a calibration signal 450 that is used to quantify amplitude offsets, phase offsets, and/or DC offsets present within the various signals of the multi-channel ADC 400. Alternatively, those skilled in the art will recognize that the calibration signal 450 may be provided to the second switching module 402 and the damage detection module 404 by other electrical, mechanical, and/or electromechanical means without departing from the spirit and scope of the present disclosure.

The phase adjustment modules 406.1 to 406.i adjust a plurality of phases φ of the sampling clock in response to the impairment correction signals 456.1 to 456.i₁To phi_iTo provide multiple time-sequenced phases of the sampling clockTo. In general, the phase adjustment modules 406.1 to 406.i adjust a plurality of phases φ of the sampling clock₁To phi_iThereby substantially compensating for a plurality of phases phi that may exist in the sampling clock₁To phi_iInner unknown offset delta₁To delta_i. The phase adjustment modules 406.1 to 406.i may advance and/or retard multiple phases φ of the sampling clock₁To phi_iThereby sufficiently compensating for the unknown offset δ₁To delta_i。

The gain/offset adjustment modules 408.1 to 408.i adjust a plurality of phases φ of the sampling clock in response to the impairment correction signals 456.1 to 456.i₁To phi_iProviding compensated digital output segments 458.1 through 458. i. In general, the gain/offset adjustment modules 408.1 to 408.i adjust the digital output segments 454.1 to 454.i to substantially compensate for the unknown gain Δ G that may exist within the digital output segments 454.1 to 454.i₁To Δ G_iAnd/or unknown offsets. The gain/offset adjustment modules 408.1 to 408.i can adjust the increase and/or decrease of the amplitude and/or offset of the digital output segments 454.1 to 454.i to substantially compensate for the unknown gain Δ G₁To Δ G_iAnd/or unknown offsets.

The switching module 104 combines or interleaves the compensated digital output segments 458.1 through 458.i to produce the digital output segment 154.

Exemplary Damage detection Module

Fig. 5 shows a block diagram of an exemplary impairment detection module that may be used in a multi-channel ADC according to an exemplary embodiment of the present disclosure. The impairment detection module 500 determines correlations between known calibration signals (e.g., calibration signal 450) and various signals within a multi-channel ADC (e.g., multi-channel ADC 400) to quantify an unknown offset δ present within the various signals₁To delta_iUnknown gain Δ G₁To Δ G_i(as shown in fig. 3B) and/or DC unknown offset. The impairment detection module 500 provides phase, amplitude and/or offset signals to various modules within the multi-channel ADC to compensate for amplitude offsets, phase offsets and/or DC offsets present within these various signals. The impairment detection module 500 comprises a reference module 502, a Quadrature Direct Digital Frequency Synthesizer (QDDFS) 504, tone correlators 506.1 to 506.i, and a compensation module 508. The impairment detection module 500 may represent an exemplary implementation of the impairment detection module 404.

The reference module 502 generates a calibration signal 552 having a known amplitude, phase, and/or DC offset. Generally, the reference module 502 includes an electrical, mechanical, and/or electromechanical oscillator. For example, the oscillator may comprise a harmonic or linear oscillator, thereby producing a sinusoidal output; and/or relaxation oscillators to produce a non-sinusoidal output such as a square, saw tooth, or triangular output. The oscillator may provide the calibration signal 552 and/or may use a Phase Locked Loop (PLL) reference, which may provide the calibration signal 552. In some implementations, the calibration signal 552 can be used by the multi-channel ADC400 as the calibration signal 450 in the calibration mode of operation.

The QDDFS504 provides a digital reference sequence 554 comprising an in-phase reference sequence 554.1 and a quadrature-phase reference sequence 554.2 based on a calibration signal 552. The quadrature-phase reference sequence 554.2 is approximately 90 degrees out of phase with the in-phase reference sequence 554.1. The QDDFS504 frequency converts and/or digitizes the calibration signal 552 to provide an in-phase reference sequence 554.1 and a quadrature-phase reference sequence 554.2. Generally, the number of channels that the QDDFS504 passes through the multi-channel ADC multiplies the frequency of the calibration signal 552.

The tone correlators 506.1 through 506.i determine the correlation between the digital reference sequence 554 and the digital sequences 550.1 through 550.i (e.g., digital output segments 454.1 through 454. i). In particular, the tone correlators 506.1 through 506.i can determine a first plurality of phase offsets φ between the in-phase reference sequence 554.1 and the digital sequences 550.1 through 550.i_i1To phi_ii. In addition, the tone correlators 506.1 through 506.i may determine a second plurality of phase offsets φ between the quadrature phase reference sequence 554.2 and the digital sequences 550.1 through 550.i_q1To phi_qi. In addition, the tone correlators 506.1 to 506.i can determine a plurality of amplitudes of the digital sequences 550.1 to 550.iTo. In addition, the tone correlators 506.1 to 506.i can determine a plurality of DC offsets Δ of the digital sequences 550.1 to 550.i₁To delta_i. The tone correlators 506.1 to 506.i provide a first plurality of phase offsets phi_i1To phi_iiA second plurality of phase shifts phi_q1To phi_qiMultiple amplitudesToAnd/or a plurality of DC offsets Δ₁To delta_i556.1 to 556.i are related as amplitude, phase and/or DC offset.

The compensation module 508 provides phase, amplitude and/or DC offset signals 558.1 to 558.i, which may represent exemplary embodiments of the impairment correction signals 456.1 to 456.i, for example, in response to the amplitude, phase and/or DC offset correlations 556.1 to 556. i. For example, the compensation module 508 designates one of the channels corresponding to one of the amplitude, phase and/or DC offset correlations 556.1 to 556.i as a reference channel. The compensation module 508 compares the other amplitude, phase and/or DC offset correlations 556.1 through 556.i corresponding to the other channels to the reference channel to determine the amplitude, phase and/or DC offset between the other channels and the reference channel. For example, the compensation module 508 may determine the unknown phase offset between one of these other channels and the reference channel by evaluating:

wherein phi is_iRepresents the in-phase component of one of these other channels, and_qrepresents the quadrature phase shift of one of these other channels and compares it with the phase of the reference channel. As another example, the compensation module 508 may determine the unknown amplitude offset between one of the other channels and the reference channel by taking the average energy of the one of the other channels and the average energy of the reference channel. The compensation module 508 provides phase, amplitude and/or DC offset signals 558.1 to 558.i to compensate for amplitude offsets, phase offsets and/or DC offsets in these other channels relative to the reference channel.

The compensation module 508 may compare the amplitude, phase, and/or DC offset correlations 556.1 to 556.i corresponding to the reference channel with the amplitude, phase, and/or DC offset correlations 556.1 to 556.i corresponding to the other channels to provide a plurality of impairment errors indicative of the amplitude offset, phase offset, and/or DC offset estimates within these other channels of the multi-channel ADC. The compensation module 508 may generate phase, amplitude, and/or DC offset signals 558.1 to 558.i that minimize these impairment errors. It will be apparent to those skilled in the relevant art that compensation module 508 uses a Least Mean Square (LMS), Recursive Least Squares (RLS), Minimum Mean Square Error (MMSE) algorithm, or any suitable algorithm that produces a result that minimizes error (quantified by some metric, e.g., minimum mean square error) to produce phase, amplitude, and/or DC offset signals 558.1 through 558.i without departing from the spirit and scope of the invention.

Exemplary Pitch correlator

Fig. 6 shows a block diagram of an exemplary tone correlator that may be used in an impairment detection module according to an exemplary embodiment of the present disclosure. The tone correlator 600 determines correlations between a known calibration signal (e.g., calibration signal 450 or calibration signal 552) and various signals within a multi-channel ADC (e.g., multi-channel ADC 400) to quantify an unknown offset δ existing within these various signals₁To delta_iUnknown gain Δ G₁To Δ G_i(as shown in fig. 3B) and/or DC unknown offset. The tone correlator 600 determines an average amplitude 652 of a digital sequence 650 (e.g., one of the digital output segments 454.1 through 454.i and/or one of the digital sequences 550.1 through 550. i). In addition, the tone correlator 600 determines an in-phase offset 654 between the in-phase component 658 of the reference sequence (e.g., the in-phase reference sequence 554.1) and the digital sequence 650. In addition, the tone correlator 600 determines a quadrature phase offset 656 between the quadrature phase component 660 of the reference sequence and the digital sequence 650. The tone correlator 600 includes an amplitude detection block 602, a first phase detection block 604, and a second phase detection block 606. Tone correlator 600 may represent an exemplary implementation of one of the tone correlators 506.1 through 506. i.

Amplitude detection module 602 determines the average energy of digital sequence 650, providing an average amplitude 652. The amplitude detection module 602 includes a mathematical expect module 608 and an accumulator 610. The mathematical expectation module 608 determines a weighted average of the digital sequence 650, which digital sequence 650 is then accumulated by the accumulator 610 to provide an average amplitude 652.

The first phase detection module 604 determines the in-phase offset 654 between the in-phase component 658 and the digital sequence 650. The first phase detection module 604 includes a multiplication module 612 and an accumulator 614. The multiplication module 612 multiplies the digital sequence 650 and the in-phase component 658, and the digital sequence 650 is then accumulated by the accumulator 614 to provide the in-phase offset 654.

The second phase detection module 606 determines a quadrature phase offset 656 between the quadrature phase component 660 and the digital sequence 650. The second phase detection module 606 includes a multiplication module 616 and an accumulator 618. Multiplication module 616 multiplies the digital sequence 650 and the quadrature phase component 660, which digital sequence 650 is then accumulated by accumulator 618, providing quadrature phase offset 656.

Digital compensation of impairments in multi-channel ADC

Fig. 7 shows a block diagram of a second multi-channel analog-to-digital converter (ADC) according to an exemplary embodiment of the present disclosure. The multi-channel ADC700 converts the analog input 150 from the analog signal domain to the digital domain in the normal operating mode. In the normal operating mode, the multi-channel ADC700 samples the analog input 150 at different times using multiple phases of a sampling clock, converts the samples from the analog signal domain to the digital signal domain, and recombines the digital samples to produce the digital output samples 154.

Optionally, in the calibration mode of operation, the multi-channel ADC700 determines various statistical relationships (e.g., various correlations) between these digital samples and various known calibration signals, thereby quantifying well the impairments present within the digital samples. The multi-channel ADC700 determines various phase offset, amplitude offset, and/or DC offset signals based on these various statistical relationships. These various phase offset, amplitude offset and/or DC offset signals are used by the multi-channel ADC700 to compensate for the amplitude offset, DC offset and/or phase offset present in the digital domain within the various signals of the multi-channel ADC 700. The multi-channel ADC700 includes ADCs 102.1 to 102.i, a switching module 104, a second switching module 402, a damage detection module 404, a coefficient generator module 702, combining modules 704.1 to 704.i, tapped delay line modules 706.1 to 706.i, and an offset detection module 708.

The second switching module 402 selects between the analog input 150 in the normal mode of operation and the calibration signal 450 in the calibration mode of operation to provide the analog input 452.

ADCs 102.1-102. i are responsive to multiple phases φ of a sampling clock₁To phi_iThe analog input 452 is converted from the analog signal domain to the digital signal domain to provide digital output segments 454.1 through 454. i. In particular, ADCs 102.1 through 102.i use multiple phases φ of the sampling clock₁To phi_iAnalog input 452 is sampled at various optimal sampling points. The ADCs 102.1 to 102.i convert the sampled representation of the analog input 452 from the analog signal domain to the digital signal domain, providing digital output segments 454.1 to 454. i.

The impairment detection module 404 quantizes amplitude offsets, DC offsets and/or phase offsets present in various signals of the multi-channel ADC700 resulting from various impairments in the multi-channel ADC700 to provide impairment correction signals 456.1-456. i.

The offset detection module 708 provides DC offset signals 754.1 through 754.i in response to the damage correction signals 456.1 through 456. i. The offset detection module 708 provides DC offset signals 754.1 through 754.i that minimize DC offset between the digital output segments 454.1 through 454. i. Optionally, offset detection module 708 provides DC offset signals 754.1 through 754.i such that any DC offset is substantially equivalent between digital output segments 454.1 through 454. i.

The combining modules 704.1 to 704.i combine the digital output segments 454.1 to 454.i and the DC offset signals 754.1 to 754.i to provide offset corrected output segments 756.1 to 756. i.

Coefficient generator module 702 provides sets of correction coefficients 750.1 through 750.i to tapped delay line modules 706.1 through 706.i in response to damage correction signals 456.1 through 456. i. The coefficient generator module 702 may generate correction coefficient sets 750.1 through 750.i that minimize the amplitude offset and/or phase offset between the calibration signal 450 and the offset corrected output segments 756.1 through 756. i. The coefficient generator module 702 may generate the sets of correction coefficients 750.1 through 750.i using Least Mean Square (LMS), Recursive Least Squares (RLS), Minimum Mean Square Error (MMSE) algorithm, or any suitable adaptive algorithm that produces a result of minimizing error (quantified by a metric, such as minimum mean square error), as will be apparent to those skilled in the relevant art, without departing from the spirit and scope of the invention.

The tapped delay line modules 706.1 to 706.i compensate for amplitude offsets and/or phase offsets within the offset corrected output segments 756.1 to 756.i, thereby providing compensated digital output segments 752.1 to 752. i. The tapped delay line modules 706.1 to 706.i weight each of their respective taps according to the correction coefficient sets 750.1 to 750.i to compensate for amplitude offsets and/or phase offsets within the offset corrected output segments 756.1 to 756. i. In an exemplary embodiment, tapped delay line modules 706.1 through 706.i may be implemented as part of one or more adaptive equalizers. The one or more adaptive equalizers adaptively adjust their impulse responses according to the sets of correction coefficients 750.1 through 750.i to compensate for amplitude and/or phase offsets within the offset correction output segments 756.1 through 756. i. These adaptive equalizers may be implemented using any suitable adaptive filter, such as, but not limited to, one or more Decision Feedback Equalizers (DFEs), one or more Feed Forward Equalizers (FFEs), and/or any combination thereof.

The switching module 104 combines or interleaves the compensated digital output segments 752.1 through 752.i, producing digital output samples 154.

Conclusion

It is to be understood that the detailed description section, and not the abstract section, is intended to be used to interpret the claims. The abstract section may set forth one or more, but not all exemplary embodiments of the disclosure, and is therefore not intended to limit the disclosure and claims in any way.

The disclosure has been described above with the aid of functional building blocks illustrating the execution of specific functions and relationships. The boundaries of these functional building blocks may be arbitrarily defined herein for convenience of illustration. Alternative boundaries may be defined so long as the specific functions and relationships thereof are appropriately performed.

It will be apparent to persons skilled in the relevant art that various modifications in form and detail can be made therein without departing from the spirit and scope of the disclosure. Thus, the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims (10)

1. A multi-channel analog-to-digital converter (ADC) configured to convert an analog input from an analog signal domain to a digital signal domain to provide digital output samples, the ADC comprising:

a plurality of ADCs configured to convert an analog input from the analog signal domain to the digital signal domain to provide a plurality of digital output segments, the plurality of ADCs configured to sample the analog input using a corresponding one of a plurality of phases of a sampling clock, the plurality of phases being offset from one another;

a switching module configured to interleave the plurality of digital output segments to provide the digital output samples; and

a impairment detection module configured to determine a statistical relationship between the plurality of digital output segments and a calibration signal to quantify impairments within the plurality of ADCs.

2. A multi-channel analog-to-digital converter according to claim 1, wherein said statistical relationship is a correlation between said plurality of digital output segments and said calibration signal.

3. The multi-channel analog-to-digital converter of claim 1, wherein the impairment comprises at least one selected from the group consisting of:

a phase offset between at least one of the phases of the plurality of phases and the calibration signal;

an amplitude offset between at least a first one of the digital output segments and the calibration signal; and

a Direct Current (DC) offset between at least a second one of the digital output segments and the calibration signal.

4. A multi-channel analog-to-digital converter according to claim 1, wherein the calibration signal is a sinusoidal signal having a known frequency.

5. The multi-channel analog-to-digital converter of claim 1, wherein the impairment detection module is further configured to provide a plurality of impairment correction signals based on the statistical relationship, and further comprising:

a phase adjustment module configured to adjust a phase of at least one of the plurality of phases based on a corresponding first impairment correction signal of the plurality of impairment correction signals; and

a gain/offset adjustment module configured to adjust an amplitude and a direct current offset (DC) of at least one of the plurality of digital output segments based on a corresponding second impairment correction signal of the plurality of impairment correction signals.

6. The multi-channel analog-to-digital converter of claim 1, wherein the impairment detection module is further configured to provide a plurality of impairment correction signals based on the statistical relationship, and further comprising:

a coefficient generator module configured to provide a plurality of sets of correction coefficients based on the plurality of impairment correction signals; and

a plurality of tapped delay line modules coupled to the plurality of ADCs configured to compensate for the impairments within the plurality of digital output segments by weighting their respective taps using the plurality of sets of correction coefficients to provide a plurality of compensated digital output segments,

wherein the switching module is further configured to interleave the plurality of compensated digital output segments to provide the digital output samples.

7. The multi-channel analog-to-digital converter of claim 1, wherein the coefficient generator module is further configured to update the plurality of sets of correction coefficients using an adaptive algorithm that produces a result that minimizes an error between the plurality of digital output segments and the calibration signal.

8. The multi-channel analog-to-digital converter of claim 1, wherein the impairment detection module is further configured to designate one of the plurality of digital output segments as a reference channel and to compare the statistical relationship of other digital output segments to the statistical relationship of the reference channel to quantify the impairment of the other digital output segments relative to the reference channel.

9. A multi-channel analog-to-digital converter (ADC) configured to convert an analog input from an analog signal domain to a digital signal domain to provide digital output samples, the ADC comprising:

a plurality of ADCs configured to convert the analog input from the analog signal domain to the digital signal domain to provide a plurality of digital output segments, the plurality of ADCs configured to sample the analog input using a corresponding phase of a plurality of phases of a sampling clock, the plurality of phases being offset from each other;

a coefficient generator module configured to provide a plurality of sets of correction coefficients based on statistical relationships between the plurality of digital output segments and the calibration signal; and

a plurality of tapped delay line modules coupled to the plurality of ADCs configured to weight their respective taps using the plurality of sets of correction coefficients to compensate for impairments within the plurality of digital output segments to provide a plurality of compensated digital output segments,

a switching module configured to interleave the plurality of compensated digital output segments to provide the digital output samples.

10. A multi-channel analog-to-digital converter (ADC) configured to convert an analog input from an analog signal domain to a digital signal domain to provide digital output samples, the ADC comprising:

a plurality of ADCs configured to convert the analog input from the analog signal domain to the digital signal domain to provide a plurality of digital output segments, the plurality of ADCs configured to use a corresponding phase of a plurality of phases of a sampling clock to sample the analog input, the plurality of phases being offset from each other;

a impairment detection module configured to determine a statistical relationship between the plurality of digital output segments and a calibration signal to quantify impairments within the plurality of digital output segments;

a plurality of phase adjustment modules configured to adjust phases of the plurality of phases based on the statistical relationship to compensate for the impairments within the plurality of digital output segments;

a plurality of gain/offset adjustment modules coupled to the plurality of ADCs configured to adjust amplitudes and direct current offsets (DCs) of the plurality of digital output segments based on the statistical relationship to provide a plurality of compensated digital output segments; and

a switching module configured to interleave the plurality of compensated digital output segments to provide the digital output samples.