HK1192058A - Semiconductor devices and fabrication methods - Google Patents

Description

Semiconductor device and method of manufacturing the same

Technical Field

The invention relates to a semiconductor device and a method of manufacturing the same. In particular, the present invention relates to the production of semiconductor devices in high quality crystal structures. For example, the device may be used to form light emitting diodes and solid state lasers.

Background

Currently, there are three main approaches to making white Light Emitting Diodes (LEDs) required for solid state lighting devices: (1) a package of three LED chips, each emitting a different wavelength (red, green and blue, respectively); (2) a combination of a blue (460 nm) LED and a yellow phosphor pumped by blue light from the LED; (3) a single chip emitting UV light, which is absorbed by three phosphors (red, green and blue) in the LED package and re-emitted as broad-spectrum white light. For the first and second approach, the main component is a blue/green LED, both of which are based on InGaN material systems. For the third method, an Ultraviolet (UV) emitter having high performance is required.

Advanced growth techniques for InGaN-based and AlGaN-based devices have been established, but are typically based on c-plane sapphire substrates. This polar orientation results in a strong built-in electric field due to the piezoelectric effect, and the device suffers from a reduction in overlap between electron and hole wave functions and a long radiative recombination time, and thus quantum efficiency is low. This is the so-called Quantum Confined Stark Effect (QCSE). In particular, as the emitter moves toward the green spectral region, a higher InN composition is required and the internal electric field typically becomes extremely high. This presents a major obstacle to achieving InGaN-based emitters (particularly green emitters) with high performance. The same problem exists for AlGaN based UV emitters, but is even worse for AlGaN than for InGaN.

Homoepitaxial growth is ideal for group III nitride-based optoelectronic devices. However, growth on foreign substrates such as sapphire, SiC, silicon, etc., still remains the dominant method for group III nitride growth for reasons of providing capability. Such "large lattice mismatch heteroepitaxy" results in a high density of faults. This will cause a significant reduction in the optical performance of group III nitride photoelectrons, such as InGaN-based near UV/blue/green emitters and AlGaN/GaN-based UV emitters. The problem of faults in AlGaN/GaN based UV emitters becomes more pronounced than in InGaN based emitters because the optical performance of AlGaN/GaN based UV emitters is more sensitive to faults than InGaN based emitters.

The two problems described above (QCSE and faults) are two fundamental obstacles to further improving the optical performance of group III nitride based optoelectronics.

One of the most promising ways to counteract the negative effects of QCSE is growth in an electrodeless or semipolar orientation, which has been proven both theoretically and practically. Another major advantage of electrodeless or semipolar III-nitride emitters is that they can emit polarized light. Liquid Crystal Displays (LCDs) require polarized illumination, and current LCDs require a super-polarizing element to achieve polarized illumination. The low transmission efficiency of the polarizing device results in reduced efficiency, and a device that emits polarized light is advantageous.

Recent growth of group III nitrides on electrodeless or semipolar planes has produced a significant breakthrough for green emitters. However, major challenges have also been exposed in that these high performance electrodeless or semipolar III-nitride emitters can only be grown on extremely expensive GaN substrates, i.e., using homoepitaxial growth methods. Unfortunately, electrodeless or semipolar GaN substrates are very small and extremely expensive. In addition, the high degree of non-uniformity makes them unsuitable for mass production.

Therefore, it is desirable to obtain electrodeless or semipolar GaN with high crystal templates (templates) on sapphire substrates of any size (e.g., to 12 inches) for further growth of InGaN-based or AlGaN-based device structures. To date, conventional Epitaxial Lateral Overgrowth (ELOG) has been employed to improve the crystalline quality of electrodeless or semipolar GaN on sapphire. ELOG techniques are based on selective area growth. Typically, a standard GaN layer is first grown on sapphire by Metal Organic Vapor Phase Epitaxy (MOVPE) or Molecular Beam Epitaxy (MBE) or Hydride Vapor Phase Epitaxy (HVPE), and then the surface is coated ex situ with a dielectric mask,for example SiO₂Or Si₃N₄. The mask is then patterned into micron-scale bars (not nano-scale) using standard photolithography. The masked sample is then used as a template for further growth by MOVPE or MBE or HVPE. Regrowth starts on the exposed GaN in the mask window area because GaN does not grow on top of the dielectric mask. When the growth surface reaches above the height of the mask, the GaN regrowth extends laterally over the stripe mask and can eventually coalesce to form a smooth surface. Faults in the crystal structure starting from under the mask stripes caused by large lattice mismatch between sapphire and GaN are effectively prevented. The mask stripe width and the flap width cannot be further reduced to the nanometer scale due to the limitations of standard lithography. Therefore, generally, a flat surface cannot be obtained until the overgrowth layer reaches a thickness of more than 10-20 μm. In addition, it is difficult to apply such a method to the overgrowth of AlGaN, because the AlGaN lateral growth rate is generally much smaller than the GaN lateral growth rate, resulting in very slow bonding.

Therefore, the conventional ELOG method is very complicated, and thus causes very high additional costs.

Disclosure of Invention

The invention provides a method of manufacturing a semiconductor device. The method can include providing a semiconductor wafer having a semiconductor layer. The method can include forming a first mask layer over the semiconductor layer. The method can include forming a second mask layer over the first mask layer. The method may include annealing or otherwise applying or altering the second mask layer to form islands. The method may include etching through the first mask layer and the semiconductor layer using the islands as a mask to form an array of pillars. The method also includes growing a semiconductor material between the pillars and then over the tops of the pillars.

The method may include removing the islands prior to growing the semiconductor material.

A cap formed from one of the mask layers may be left on top of each pillar during the growth of the semiconductor material. This may be the first mask layer.

The semiconductor layer may be supported on a substrate. The substrate may include at least one of sapphire, silicon, and silicon carbide.

The semiconductor material grown on the pillars may be the same as the material from which the semiconductor layer (and hence the pillars) is made, or it may be a different material.

The semiconductor layer may be formed of a group III nitride. For example, it may be formed of gallium nitride, indium gallium nitride, or aluminum gallium nitride. The semiconductor material may also be a group III nitride material, such as gallium nitride, indium gallium nitride, or aluminum gallium nitride.

The first mask layer may be formed of at least one of silicon dioxide and silicon nitride.

The second mask layer may be formed of a metal, for example, nickel.

The method may further include removing the support substrate. This may include removing a portion, e.g., the lowermost portion, of the column.

The invention also provides a semiconductor device comprising an array of pillars, each comprising a main pillar formed of a semiconductor material, and each comprising a lid formed of a mask material formed on top thereof, the semiconductor material extending between the pillars and over the tops of the pillars and over the lids to form a continuous layer. The two semiconductor materials may be the same, or they may be different. The array of pillars may comprise pillars all less than 1000nm in diameter, and preferably less than 500nm, more preferably less than 300 nm. In some cases there may be irregularities in diameter, so that some of the pillars are large, but preferably at least 90% of the pillars have a diameter of the size given above. The height of the pillars is preferably at least 500nm, more preferably at least 750 nm. The posts may all be substantially the same height. The mask material may be a metal.

At least some of the nano-pillars may have a cavity around their bottom.

The invention is based on the combination of a so-called self-organizing nano-mask method and subsequent overgrowth. The fabrication of the self-organizing nanomask is very simple and does not require additional lithography. The overgrown layer is relatively thin compared to the known ELOG method, but the obtained crystal quality is equal to or better than that of the conventional ELOG. Therefore, the cost can be significantly reduced. In addition, the method can be used to grow any group III nitride including polar, non-polar, or semi-polar.

Drawings

The method or device may also comprise any one or more of the steps or features of the preferred embodiments of the invention, in any combination, which is now described, by way of example only, with reference to the accompanying drawings, in which:

FIGS. 1a to 1h illustrate steps of forming a device according to an embodiment of the present invention;

FIG. 2 is an image of the nanorod array shown in FIG. 1 d; and

fig. 3 is a full width half maximum plot showing the x-ray rocking curve as a function of the azimuthal angle of the incident x-ray beam for samples formed according to the method of fig. 1a to 1h and standard samples of electrodeless GaN.

Detailed Description

Referring to fig. 1a, the first step in the fabrication of the device is to provide a suitable semiconductor wafer 201. Wafer 201 is a conventional wafer and is made of a substrate 205, which in this case comprises a sapphire layer, on which is a semiconductor layer 210 formed of gallium nitride (GaN). Other materials may be used. For example, the substrate may be silicon or silicon carbide. The semiconductor may be other suitable materials, for example, other group III nitrides, such as indium gallium nitride (InGaN) or aluminum gallium nitride (AlGaN).

A first mask layer 220 is provided over the semiconductor layer 210, for example using Plasma Enhanced Chemical Vapor Deposition (PECVD). The first mask layer 220 is formed of silicon dioxide and is deposited with a uniform thickness of approximately 200 nanometers, despite a suitable selective material for this layer, for example, silicon nitride.

A second mask layer 230, comprising a metal, in this case nickel, is provided over the first mask layer 220. This can be done by thermal evaporation or sputtering or electron beam evaporation. In this step, a nickel layer of substantially uniform thickness in the range of 5 to 50 nanometers is formed, followed by flowing nitrogen (N) at a temperature in the range of 600 to 900 degrees Celsius₂) And annealing under the environment. The duration of the annealing process is 1 to 10 minutes, resulting in the formation of a second mask layer 230 from the nickel layer over the first mask layer 220, which includes irregularly distributed self-assembled nickel islands 231. Each of the nickel islands covers a respective approximately circular region of the upper surface of the first mask layer 220, typically no less than 100 nanometers in diameter and no greater than 1000 nanometers in diameter. Thus, the second mask layer 230 can be used to etch the underlying SiO₂Masking of layers in which nickel islands 231 mask the underlying SiO₂Multiple regions of the layer, and the spacing between the nickel islands leaving SiO₂Multiple exposed regions of the layer to define the lower SiO₂The area of the layer to be etched.

Referring to fig. lc, the first mask layer 220 employs CHF in a Reactive Ion Etching (RIE) process using the metal islands 231 of the second mask layer 230 as a mask₃Or SF₆And (5) through etching. This step provides nano-pillars (also referred to as nano-rods) 240 of silicon dioxide irregularly distributed over the GaN layer 210, each of which includes portions 221 of the first mask layer 220 and respective nickel islands 231. Each nanorod 240 corresponds to a respective nickel island having a diameter that is approximately the same as the diameter of the surface area covered by the respective nickel island. The nano-pillars 240 produced by the foregoing steps serve to mask certain regions of the GaN layer 210 and define regions where the GaN layer 210 is to be etched (i.e., exposed regions in the spaces between the nano-pillars 240).

Referring to fig. 1d, in the next step, the GaN layer 210 is etched using the nano-pillars 240 formed in the previous step as a mask, for example, by inductively coupled plasma etching. This step involves etching through the GaN layer 210 such as shown in fig. 1d or partially etching through the GaN layer 210. This step results in a nanopillar structure as shown in fig. 1d, wherein nanopillars 250 extend upward from the sapphire substrate 205, each nanopillar 250 comprising portions 211 of the GaN layer 210, portions 221 of the first mask layer 220, and metal islands 231 from the second mask layer 230. Thus, the etching of this step produces an exposed surface 250a of GaN that includes the sides of the nano-pillars 250. The diameter of each nano-pillar 250 is approximately constant from top to bottom, approximately the same surface area covered by its respective nickel island 231, although in practice some tapered nano-pillars are typically produced.

Referring to fig. le, the nickel islands 231 forming the second mask layer 230 are then removed, resulting in nanopillars 260 comprising portions 211 of the GaN layer 210, portions 221 of the first mask layer 220. This can be done by using hydrochloric acid (HCl) or nitric acid (HNO)₃) And (4) wet etching. This leaves each nano-pillar, which mainly comprises the GaN pillar 211 and the SiO on top of it₂A cover 221.

Referring to fig. 1f, the GaN nanorod array is used as a template for overgrowth (overgrowth) of GaN270 deposited on the side 250a of the GaN pillar 211 by Metal Organic Chemical Vapor Deposition (MOCVD) or MBE or HVPE. Regrowth begins on the sidewalls of the GaN nanorods (lateral then vertical) where the GaN is exposed. This forms a layer 271 on the walls of the nanopillars. These growths are outward from the pillars and toward each other until they touch where the layer is thickest. This then further prevents further growth in the space 273 below the contact point 272 and continues to grow in the space 274 above the contact point. In some cases, this leaves a space 273 as a hollow gap or cavity around the bottom of each nanopillar. These gaps may be interconnected to form a cavity, which is in the form of a labyrinth and extends between all or substantially all of the nanopillars. SiO on top of the nanopillars₂The mask 221 will prevent GaN from growing on top of them. Referring to FIG. 1g, when the growth surface of GaN reaches SiO₂Above the height of the nanomask 221, the regrowth of GaN is on SiO₂Laterally over the top of the nanomask, and finally joined to form a nanomaskA continuous layer extending over the top of the mould, having a smooth surface 271 as shown in figure 1 h. In theory, all faults generated by the template (i.e., in the nano-pillars 260) are effectively blocked. Even if no cavity is left around the bottom of the nanopillars, the growth from the bottom of the gap between the nanopillars is usually partially or completely cut off by the growth from the sides of the nanopillars, and the number of faults extending to the top of the nanopillars is therefore very low.

Once growth has been completed, the substrate 205 may be removed. Removing the substrate typically includes removing the bottom ends of the nano-pillars 260. This can be easily done due to the presence of the hollow space 273 around the bottom of the nanopillars. The bottom of the nanopillar 260 may be removed to a position below the contact point 272, i.e., below the top of the hollow space 273. This may result in a very uniform structure with low stress levels.

Fig. 2 shows a high density array of GaN nanorods formed, each about 200nm in diameter. It is important to note that the sidewalls of the GaN nanorods show the desired vertical alignment.

Fig. 3 shows the X-ray diffraction results of the samples produced as described above. It can be seen that the full width at half maximum of the x-ray rocking curve is greatly reduced for all azimuthal angles of the incident x-ray beam (the zero angle of azimuthal angle is defined as the emission of the incident beam parallel to the c-direction of the growing GaN layer) compared to the standard electrodeless GaN sample on r-plane sapphire. This indicates that the fault density has been greatly reduced in this embodiment of the invention.

Furthermore, the above method is very effectively used to overgrow AlGaN on GaN nanorod structures without suffering from junction problems, since the gap between GaN nanorods is of the order of nanometers, which is far more than SiO commonly used in the above conventional ELOG₂The gaps in the mask are narrow. In addition, the cracking problem of AlGaN on GaN, which typically occurs in conventional III-nitride growth, can be eliminated due to the residual voiding left in the gaps between nanorods during overgrowth.

It is to be understood that other embodiments of the present invention may vary from those described above. The method is applicable to different combinations of substrates, nano-pillar structured materials and grown semiconductor materials, but is primarily applicable where the substrates and grown semiconductors have sufficiently different lattice structures that fault formation in the semiconductor lattice structure is problematic. Obviously, the exact proportions of the structures can vary, although a unique advantage of this approach is that the structures can be produced on a small scale.

Claims (17)

1. A method of manufacturing a semiconductor device, comprising:

(i) providing a semiconductor wafer having a semiconductor layer;

(ii) forming a first mask layer over the semiconductor layer;

(iii) forming a second mask layer over the first mask layer;

(iv) annealing the second mask layer to form islands;

(v) etching through the first mask layer and the semiconductor layer using the islands as a mask to form an array of pillars;

(vi) semiconductor material is grown between the pillars and then on top of the pillars.

2. The method of claim 1, further comprising removing the islands prior to growing the semiconductor material.

3. A method according to claim 1 or claim 2, wherein a cap formed from one of the mask layers is left on top of each of the pillars during the growth of the semiconductor material.

4. A method according to any preceding claim, wherein the semiconductor layer is supported on a substrate.

5. The method of claim 4, wherein the substrate comprises at least one of sapphire, silicon, and silicon carbide.

6. A method according to any preceding claim, wherein the semiconductor layer is formed from a group III nitride.

7. The method of any preceding claim, wherein the first masking layer is formed from at least one of silicon dioxide and silicon nitride.

8. The method according to any of the preceding claims, wherein the second mask layer is formed of a metal.

9. The method of claim 8, wherein the second mask layer is formed of nickel.

10. The method of any preceding claim, wherein the growing step leaves a gap around the bottom of the pillar.

11. The method of claim 10, wherein the semiconductor material grown on adjacent pillars contacts at a location spaced from the substrate such that the gap remains below the location.

12. A semiconductor device comprising an array of pillars formed of semiconductor material, each of which includes a cap formed of a mask material formed on top thereof and semiconductor material extending between the pillars and over the tops of the pillars to form a continuous layer.

13. A semiconductor device according to claim 12, formed according to any one of the methods of claims 1 to 11.

14. A semiconductor device according to claim 12 or claim 13, wherein at least 90% of the pillars are less than 1000nm in diameter.

15. A semiconductor device according to any one of claims 12 to 14, wherein the height of the pillars is at least 500 nm.

16. A method of manufacturing a semiconductor device substantially as described herein with reference to the accompanying drawings.

17. A semiconductor device substantially as described herein with reference to the accompanying drawings.