HK1194858B - Partial buried channel transfer device in image sensors - Google Patents

Abstract

The subject application relates to a partial buried channel transfer device in image sensors. An image sensor pixel includes a photosensitive element, a floating diffusion ("FD") region, and a transfer device. The photosensitive element is disposed in a substrate layer for accumulating an image charge in response to light. The FD region is disposed in the substrate layer to receive the image charge from the photosensitive element. The transfer device is disposed between the photosensitive element and the FD region to selectively transfer the image charge from the photosensitive element to the FD region. The transfer device includes a gate, a buried channel dopant region and a surface channel region. The gate is disposed between the photosensitive element and the FD region. The buried channel dopant region is disposed adjacent to the FD region and underneath the gate. The surface channel region is disposed between the buried channel dopant region and the photosensitive element and disposed underneath the gate.

Description

Partially buried channel transfer in image sensors

Technical Field

The present invention relates generally to optics and in particular, but not exclusively, to image sensors.

Background

Image sensors are widely used in digital still cameras, cellular phones, security cameras, and in medical, automotive, and other applications. Complementary metal oxide semiconductor ("CMOS") technology is used to fabricate lower cost image sensors on silicon substrates. Among the large number of image sensors, an image sensor typically includes hundreds, thousands, or even millions of light sensor cells or pixels. A typical individual pixel includes a microlens, a filter, a photosensitive element, a floating diffusion region, and one or more transistors for reading out signals from the photosensitive element. One of the transistors included in a typical pixel is commonly referred to as a transfer transistor, which includes a transfer gate disposed between the photosensitive element and the floating diffusion. The transfer gate is disposed on a gate oxide. The photosensitive element, floating diffusion region, and gate oxide are disposed on a substrate.

During operation of a typical pixel, a conductive channel region can be formed under the transfer gate when a bias voltage is applied to the transfer gate to cause image charge to be transferred from the photosensitive element to the floating diffusion region. However, conventional pixels typically suffer from image lag, blur, and manufacturing challenges.

Image lag may be caused by the inability of conventional transfer transistors to remove all of the signal from the photosensitive element so that the residual signal remains during successive reads of the pixel. This residual information remaining in the photosensitive elements is commonly referred to as image lag, residual image, ghosting, or inter-frame retention.

Blurring may be caused by high intensity portions of the image that cause photogenerated excess charge carriers to overflow into neighboring photosensitive elements. In one design of a transfer transistor, such as in a standard NMOS transistor, an N-doped polysilicon gate electrode controls a surface channel transistor. In this design, the threshold voltage of the transistor is low, and a negative gate bias typically needs to be applied during the integration period, and a large gate voltage swing is needed to minimize image lag. In this case, blurring may be generated and may limit the dynamic range of the imaging sensor and may limit the type of commercial application of the imaging sensor.

Manufacturing challenges in conventional pixels can stem from the position-sensitive placement of the photosensitive element relative to the transfer gate. The sensitive nature of the placement can lead to increased defects in the various parts and increased manufacturing costs.

Disclosure of Invention

An aspect of the application provides an image sensor pixel, comprising: a photosensitive element disposed in a substrate layer for accumulating image charge in response to light; a floating diffusion ("FD") region disposed in the substrate layer to receive the image charge from the photosensitive element; and a transfer device disposed between the photosensitive element and the FD region to selectively transfer the image charge from the photosensitive element to the FD region, the transfer device comprising: a gate disposed between the photosensitive element and the floating diffusion region; a buried channel dopant region disposed adjacent to the FD region and below the gate; and a surface channel region disposed between the buried channel dopant region and the photosensitive element and disposed below the gate.

Another aspect of the present application provides an imaging system, comprising: an imaging pixel array; and readout circuitry coupled to the array of imaging pixels to readout image data from each of the image sensor pixels, wherein each imaging pixel in the array of imaging pixels includes: a photosensitive element disposed in a substrate layer for accumulating image charge in response to light; a floating diffusion ("FD") region disposed in the substrate layer to receive the image charge from the photosensitive element; and a transfer device disposed between the photosensitive element and the FD region to selectively transfer the image charge from the photosensitive element to the FD region, the transfer device comprising: a gate disposed between the photosensitive element and the floating diffusion region; a buried channel dopant region disposed adjacent to the FD region and below the gate; and a surface channel region disposed between the buried channel dopant region and the photosensitive element and disposed below the gate.

Yet another aspect of the present application provides a method of fabricating an image sensor pixel, the method comprising: forming a buried channel device mask on the semiconductor structure, thereby isolating where the buried channel device is to be located; implanting a first dopant into a buried channel dopant region using high energy ion implantation, wherein an ion beam including the first dopant travels through a polysilicon gate prior to implantation into the buried channel dopant region, the buried channel dopant region disposed between a photosensitive element of the image sensor pixel and a floating diffusion ("FD") region of the image sensor pixel; removing the buried channel device mask; forming a surface trench device mask on the semiconductor structure, thereby isolating where a surface trench device is to be located; and implanting second dopants into a surface channel dopant region disposed between the buried channel dopant region and the photosensitive element.

Drawings

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

FIG. 1 is a cross-sectional view of a conventional image sensor pixel including a conventional transfer gate structure and a conventional photosensor structure.

FIG. 2 is a functional block diagram illustrating an image sensor according to an embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating sample pixel circuitry for two image sensor pixels within an image sensor according to an embodiment of the invention.

FIG. 4A is a cross-sectional view along line A-A' of FIG. 4B illustrating a portion of an image sensor pixel including a transfer device according to an embodiment of the invention.

Figure 4B is a top view of the structure of a photosensitive element, transfer gate and floating diffusion region according to an embodiment of the invention.

Fig. 5 is a graph illustrating a relationship between electrons and relative energy levels of a structure according to an embodiment of the present invention.

FIG. 6 is a flow chart illustrating a process for manufacturing a transfer device according to an embodiment of the invention.

Detailed Description

Embodiments of an apparatus, system, and method of manufacturing an image sensor with a partially buried channel transfer gate are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein may be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

FIG. 1 is a cross-sectional view of a conventional image sensor pixel including a conventional transfer gate structure and a conventional photosensor structure. Image pixel 100 includes a photosensitive element 115 that receives light 105 incident on image pixel 100. To implement a color pixel, image pixel 100 further includes a color filter 145 disposed below microlens 140. The microlens 140 helps focus the light 105 onto the photosensitive element 115. In general, an image sensor includes a number of image pixels 100 arranged in a two-dimensional row and column array in a larger substrate (i.e., extending beyond the substrate 135 as shown). Image pixel 100 further includes a floating diffusion ("FD") region 130 and a photosensitive element 115, such as a photodiode, disposed on a substrate 135. The substrate 135 may comprise an epitaxial layer grown on a substrate. Transfer gate 120 is disposed between photosensitive element 115 and FD region 130 and is used to transfer signals output from photosensitive element 115 to FD region 130. The FD region 130 is surrounded by a P-type well 132 formed in a substrate 135. When a threshold gate voltage (i.e., a bias voltage) is applied to the transfer gate 120, a conductive channel (not illustrated) may be formed in the substrate 135 under the transfer gate 120 and under the gate insulation layer 125. The P-type pinning layer 110 may be disposed over the photosensitive element 115. The neck region 150 is the region that includes the intersection of the P-type pinning layer 110, the photosensitive element 115, the transfer gate 120, and the substrate 135.

The pixel 100 operates as follows. During an integration period (also referred to as an exposure or accumulation period), light 105 is incident on the photosensitive element 115. The photosensitive element 115 generates an electrical signal (photo-generated charge) in response to incident light. The electrical signal is held in the light sensitive element 115. At this stage, the transfer gate 120 may be turned off. When the bias voltage on the transfer gate 120 does not reach its threshold voltage, the transfer gate 120 is turned off and the substrate between the photosensitive element 115 and the FD region 130 is resistant to electron flow.

After the integration period, the transfer gate 120 is turned on to read out the signal from the photosensor 115. For example, a positive bias voltage is applied to the transfer gate 120, and as the bias voltage on the transfer gate 120 increases, the substrate under the transfer gate 120 near the floating diffusion region 130 first becomes conductive. The substrate below the transfer gate 120 that becomes conductive when a bias voltage is applied to the transfer gate 120 is referred to as a channel region (not illustrated). The channel region continues to gradually become conductive toward the photosensitive element 115 as the threshold voltage is approached. When the threshold voltage is met, the channel region conducts allowing charge carriers to flow between the photosensitive element 115 and the FD region 130, thus transferring the electrical signal held by the photosensitive element 115 to the FD region 130. After the electrical signal in the photosensitive element 115 has been transferred to the floating diffusion region 130, the transfer gate 120 is turned off for the next integration period.

FIG. 2 is a block diagram illustrating an imaging system 200 according to an embodiment of the invention. The illustrated embodiment of imaging system 200 includes a pixel array 205, readout circuitry 210, functional logic 215, and control circuitry 220.

The pixel array 205 is a two-dimensional ("2D") imaging sensor or pixel (e.g., pixel P1, P2, …, Pn) array. In one embodiment, each pixel is a complementary metal oxide semiconductor ("CMOS") imaging pixel. As illustrated, each pixel is arranged in rows (e.g., rows R1-Ry) and columns (e.g., columns C1-Cx) to acquire image data of a person, place, or object, which can then be used to render a 2D image of the person, place, or object.

After each pixel has acquired its image data or image charge, the image data is read out by readout circuitry 210 and transferred to functional logic 215. The readout circuit 210 may include an amplification circuit, an analog-to-digital ("ADC") conversion circuit, or others. Function logic 215 may simply store the image data or even manipulate the image data by applying post-image effects (e.g., crop, rotate, remove red-eye, adjust brightness, adjust contrast, or otherwise). In one embodiment, readout circuitry 210 may readout a row of image data at a time along readout column lines (illustrated) or may readout the image data simultaneously using a variety of other techniques (not illustrated), such as a serial readout or a parallel readout of all pixels. Control circuitry 220 is coupled to pixel array 205 to control the operating characteristics of pixel array 205. For example, the control circuit 220 may generate a shutter signal for controlling image acquisition.

FIG. 3 is a circuit diagram illustrating a pixel circuit 300 of two four-transistor ("4T") pixels within an imaging array, according to an embodiment of the invention. Pixel circuit 300 is one possible pixel circuit architecture for implementing each pixel within pixel array 205 of fig. 2. However, it should be understood that embodiments of the invention are not limited to 4T pixel architectures; rather, those skilled in the art, with the benefit of this disclosure, will appreciate that the present teachings also apply to 3T designs, 5T designs, and various other pixel architectures.

In fig. 3, pixels Pa and Pb are arranged in two rows and one column. The illustrated embodiment of each pixel circuit 300 includes a photodiode PD, a transfer transistor T1, a reset transistor T2, a source follower ("SF") transistor T3, a select transistor T4, and a storage capacitor C1. During operation, the transfer transistor T1 receives a transfer signal TX that transfers charges accumulated in the photodiode PD to the floating diffusion node FD. In one embodiment, the floating diffusion node FD may be coupled to a storage capacitor for temporarily storing image charge.

A reset transistor T2 is coupled between a power rail VDD and the floating diffusion node FD to reset the pixel (e.g., discharge or charge the FD and PD to a preset voltage) under control of a reset signal RST. Floating diffusion node FD is coupled to control the gate of SF transistor T3. SF transistor T3 is coupled between power rail VDD and select transistor T4. The SF transistor T3 operates as a source follower providing a high impedance connection to the floating diffusion FD. Finally, select transistor T4 selectively couples the output of pixel circuit 300 to the readout column line under control of a select signal SEL. In one embodiment, the TX signal, the RST signal, and the SEL signal are generated by control circuitry 220.

Fig. 4A and 4B illustrate a portion of an image pixel 400 including a transfer device 425, according to an embodiment of the invention. Fig. 4B is a top view of image pixel 400 and fig. 4A is a cross-sectional view along line a-a' of fig. 4B. Image pixel 400 of FIG. 4A is one possible implementation of pixels P1 through Pn within pixel array 205. The illustrated embodiment of image pixel 400 includes a P-pinned layer 405, a photosensitive element 410, a floating diffusion region 415, a doped well 435, a substrate layer 420, and a transfer device 425. The photosensitive element 410, the doped well 435, and the floating diffusion region 415 are disposed within a substrate layer 420. The P pinning layer 405 is disposed above the photosensitive element 410. A transfer device 425 is disposed between the photosensitive element 410 and the floating diffusion region 415.

The illustrated embodiment of the transfer device 425 includes a common gate electrode 440, a buried channel dopant region 450, a surface channel dopant region 455, and a gate insulation layer 470. Can make V_TX430 are applied to the common gate electrode 440 to activate the transfer device 425. In the illustrated embodiment, the gate electrode 440 is disposed over the buried channel dopant region 450 (forming a buried channel device) in addition to being disposed over the surface channel dopant region 455 (forming a surface channel device). The buried channel devices and the surface channel devices are coupled in series between the photosensitive element 410 and the floating diffusion region 415. The buried channel dopant region 450 may be aligned under the common gate electrode 440, and a right edge of the buried channel dopant region 450 may be flush with a right edge of the common gate electrode 440. The surface channel dopant region 455 may be below the common gate electrode 440 and the left edge of the surface channel region 455 may abut the right edge of the photosensitive element 410.

V_TX430 may reach the threshold voltage of the transfer device 425, turning on the transfer device 425. When the transfer device 425 is turned on, the buried channel 460 and the surface channel 465 form a series connection, allowing charge carriers to flow between the photosensitive element 410 and the floating diffusion region 415. The buried channel 460 and the surface channel 465 together form a channel of the transfer device 425. In one embodiment, the transfer device 425 may be configured to receive V of-1.2 volts_TX430 to keep the conveyor 425 off.

In the illustrated embodiment, the photosensitive element 410 and the floating diffusion region 415 are N-type doped, while the well 435 is oppositely (P-type) doped from the N-type dopant of the photosensitive element 410 and the floating diffusion region 415. The buried channel dopant region 450 is doped N-type. In the illustrated embodiment, the surface channel dopant region 455 is P-type doped. In alternative embodiments, the surface channel region 455 may be doped N-type or not doped at all. Those skilled in the art will understand that in alternative embodiments, the doping polarities in the illustrated embodiments may be reversed.

In the illustrated embodiment, both the buried channel dopant region 450 and the photosensitive element 410 are N-type doped, while the surface channel dopant region 455 is P-type doped, facilitating more controlled transfer of electrons from the photodiode because of the slight energy barrier for transferring electrons. The buried channel dopant region 450 may mean that the transfer device 425 is referred to as a partial buried channel transfer gate. The length of the surface channel dopant region 455 is limited by the presence of the buried channel dopant region 450 and results in a reduction in barrier effectiveness. During the exposure period (transfer device 425 is off), the charge accumulated by the N-doped photosensitive element 410 can remain within the photosensitive element 410 unless it is nearly full capacity or near full capacity. In one example, electrons entering the surface channel dopant region 455 may "punch through" to the buried channel dopant region 450 and the floating diffusion region 415. This feature of the illustrated embodiment causes charge carriers to spill over from the photosensitive element 410 into the floating diffusion region 415 rather than flowing to the photosensitive element of a neighboring pixel causing blooming. By adjusting the ratio between the lengths of the buried channel dopant region 450 and the surface channel region 455, the blur threshold can be tuned. For example, as the surface channel region 455 shortens, the potential barrier to overflow of excess charge into the floating diffusion region 415 is reduced, thereby further suppressing blooming.

In the illustrated embodiment, the buried channel dopant region 450 is doped opposite the substrate. Thus, when the transfer device 425 is turned on, charge carriers are driven under the surface (meaning under the intersection of the gate insulation layer 470 and the buried channel dopant region 450). The buried channel 460 illustrates the charge carriers flowing under the surface. Charge carriers flowing beneath the surface may introduce less noise into the electrical signal because they do not encounter non-uniformity between the gate insulating layer (e.g., silicon oxide) and the buried channel dopant region (e.g., N-type doped silicon).

Fig. 5 is a graph illustrating a relationship between electrons and relative energy levels of a structure according to an embodiment of the present invention. Fig. 5 illustrates the relative energy levels that electrons can experience in an image pixel 400. On the graph, the surface channel dopant region 455 has the highest energy level; the buried channel dopant region 450 has a second high energy level; the photosensitive element 410 has a third high energy level; the floating diffusion region 415 has the lowest relative energy level. When electrons are in the surface channel dopant region 455, the energy levels of the structure illustrated in fig. 4A cause the electrons to flow toward the floating diffusion region 415 regardless of whether the transfer gate 425 is on or off. When the transfer gate is off, the N-type gate 440 in combination with the P-type surface channel dopant region 455 and the N-type buried channel region 450 causes electrons overflowing the sensing element 410 to flow toward the floating diffusion region 415. The relative energy levels in fig. 5 are maintained mostly when the transfer gate is turned on, although the surface channel device has a lower threshold voltage than the buried channel device. The result is that any dark current generated under the transfer device 425 may drift toward the floating diffusion region 415. This feature prevents the white pixel from forming and reduces image lag by preventing electrons from being sent back to the photosensitive element 410 after the transfer event.

FIG. 6 is a flow chart illustrating a process for manufacturing a transfer device according to an embodiment of the invention. Process 600 is one example of how to make a transfer device 425 of image pixels 400. The order in which some or all of the process blocks appear in each process should not be construed as limiting. Rather, those skilled in the art, having the benefit of this disclosure, will appreciate that some of the process blocks may be performed in a variety of orders, or even in parallel, not illustrated.

In process block 605, a buried channel device mask is formed over the existing structure. The buried channel device mask is patterned on an existing structure to isolate regions where the buried channel device will reside. An example of an existing structure may be a combination of the P-pinned layer 405, the photosensitive element 410, the floating diffusion region 415, the substrate layer 420, the gate 440, the buried channel dopant region 450, and the surface channel region 455. However, at process block 605, the gate 440, the buried channel dopant region 450, and the surface channel region 455 may not yet contain the doping illustrated in figure 4A. For example, at process block 605, the buried channel dopant region 450 and the surface channel dopant region 455 will be lightly doped to P in the "epi" layer.

At process block 610, an N-type dopant (e.g., arsenic or phosphorous) may be implanted in the buried channel dopant region 450 using a high energy ion implant, the dopant implant dose to implant phosphorous may be 150 kilo electron volts (keV)¹²cm^-2. In one embodiment, the depth of the N-type dopant in the buried channel region 450 is 10nm to 30 nm. The high energy ion beam passes through the gate 440 on its way to the implanted buried channel dopant region 450. In process block 615, the buried channel device mask is removed. In process block 620, a surface trench device mask is formed. In process block 625, surface channel dopants (P-type dopants in the illustrated embodiment in fig. 4A) are formed in the surface channel region 455.

The above description of illustrated embodiments of the invention, including what is described in the Abstract of the disclosure, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims (18)

1. An image sensor pixel, comprising:

a photosensitive element disposed in a substrate layer for accumulating image charge in response to light;

a floating diffusion "FD" region disposed in the substrate layer to receive the image charge from the photosensitive element; and

a transfer device disposed between the photosensitive element and the FD region to selectively transfer the image charge from the photosensitive element to the FD region, the transfer device comprising:

a gate disposed between the photosensitive element and the floating diffusion region;

a buried channel dopant region disposed adjacent to the FD region and below the gate; and

a surface channel region disposed between the buried channel dopant region and the photosensitive element and disposed below the gate, wherein a ratio of a length of the buried channel dopant region to a length of the surface channel region is tuned to allow electrons to punch through from the photosensitive element to the buried channel dopant region when the photosensitive element is near full capacity and the transfer device is off.

2. The image sensor pixel of claim 1, further comprising a doped well formed in the substrate layer, wherein the FD region is disposed in the doped well, the doped well extending below the FD region and between the FD region and the surface channel dopant region.

3. The image sensor pixel of claim 1, wherein the buried channel dopant region abuts the FD region.

4. The image sensor pixel of claim 1, wherein the gate and the buried channel dopant region form a buried channel device, and wherein the gate and the surface channel region form a surface channel device, wherein the surface channel device has a lower threshold voltage than the buried channel device.

5. The image sensor pixel of claim 1, wherein the photosensitive element, the FD region, the buried channel dopant region, and the gate are N-type doped.

6. The image sensor pixel of claim 5, wherein the surface channel region is P-type doped.

7. The image sensor pixel of claim 1, wherein the transfer means is configured to turn off with a negative voltage.

8. The image sensor pixel of claim 1, wherein the surface channel region and the buried channel region are coupled in series between the photosensitive element and the FD region.

9. An imaging system, comprising:

an imaging pixel array; and

readout circuitry coupled to the array of imaging pixels to readout image data from each of the image sensor pixels, wherein each imaging pixel in the array of imaging pixels includes:

a photosensitive element disposed in a substrate layer for accumulating image charge in response to light;

a floating diffusion "FD" region disposed in the substrate layer to receive the image charge from the photosensitive element; and

a transfer device disposed between the photosensitive element and the FD region to selectively transfer the image charge from the photosensitive element to the FD region, the transfer device comprising:

a gate disposed between the photosensitive element and the floating diffusion region;

a buried channel dopant region disposed adjacent to the FD region and under the gate; and

a surface channel region disposed between the buried channel dopant region and the photosensitive element and disposed below the gate, wherein a ratio of a length of the buried channel dopant region to a length of the surface channel region is tuned to allow electrons to punch through from the photosensitive element to the buried channel dopant region when the photosensitive element is near full capacity and the transfer device is off.

10. The imaging system of claim 9, further comprising a doped well formed in the substrate layer, wherein the FD region is disposed in the doped well, the doped well extending below the FD region and between the FD region and the surface channel dopant region.

11. The imaging system of claim 9, wherein the buried channel dopant region abuts the FD region.

12. The imaging system of claim 9, wherein the gate and the buried channel dopant region form a buried channel device, and wherein the gate and the surface channel region form a surface channel device, wherein the buried channel device has a higher threshold voltage than the surface channel device.

13. The imaging system of claim 9, wherein the photosensitive element, the FD region, the buried channel dopant region, and the gate are N-type doped.

14. The imaging system of claim 13, wherein the surface channel region is P-type doped.

15. The imaging system of claim 9, wherein the transfer device is configured to turn off with a negative voltage.

16. The imaging system of claim 9, wherein the surface channel region and the buried channel region are coupled in series between the photosensitive element and the FD region.

17. A method of fabricating an image sensor pixel, the method comprising:

forming a buried channel device mask on the semiconductor structure, thereby isolating where the buried channel device is to be located;

implanting a first dopant into a buried channel dopant region using high energy ion implantation, wherein an ion beam comprising the first dopant travels through a polysilicon gate prior to implantation into the buried channel dopant region, the buried channel dopant region disposed between a photosensitive element of the image sensor pixel and a floating diffusion "FD" region of the image sensor pixel;

removing the buried channel device mask;

forming a surface trench device mask on the semiconductor structure, thereby isolating where a surface trench device is to be located; and

implanting second dopants into a surface channel dopant region disposed between the buried channel dopant region and the photosensitive element, wherein a ratio of a length of the buried channel dopant region to a length of the surface channel dopant region is tuned to allow electrons to punch through from the photosensitive element to the buried channel dopant region when the photosensitive element is near full capacity and a transfer device is off.

18. The method of claim 17 wherein the buried channel dopant region abuts the floating diffusion region.