HK1195393A - Metal oxide semiconductor devices and fabrication methods - Google Patents

Abstract

The invention relates to metal oxide semiconductor devices and fabrication methods. A semiconductor device includes a first well and a second well implanted in a semiconductor substrate. The semiconductor device further includes a raised drain structure above and in contact with the second well and separate from the gate structure. The raised drain structure includes a drain connection point above the surface of the second well.

Description

Metal oxide semiconductor device and manufacturing method

Technical Field

The present disclosure generally relates to a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). And more particularly to fabrication methods and device constructions that increase the breakdown voltage of Laterally Diffused Metal Oxide Semiconductors (LDMOS).

Background

Silicon semiconductor processes have developed complex operations for manufacturing integrated circuits. As manufacturing process technology continues to advance, the core and input/output (I/O) operating voltages of integrated circuits are gradually decreasing. However, the operating voltage of the auxiliary device is hardly changed. The accessory includes means for interfacing to an integrated circuit. For example, the auxiliary device may be a printer, a scanner, an optical drive, a tape drive, a microphone, a speaker, a video camera, or the like.

An integrated circuit may include an interconnected array of active and passive components, such as transistors, resistors, capacitors, and inductors, integrated or stacked on a substrate using a series of compatible processes. The auxiliary device may operate at a voltage higher than a breakdown voltage of a transistor included within the integrated circuit. As the operating voltage applied to a transistor increases, the transistor eventually breaks down resulting in an uncontrolled increase in current. Examples of adverse effects of electrical breakdown may include breakdown phenomena (used to provide some examples), avalanche breakdown, and gate oxide breakdown. Furthermore, operating above the breakdown voltage for a long time can significantly reduce the lifetime of the transistor.

Disclosure of Invention

The present disclosure provides a semiconductor device including: a first well embedded in the semiconductor substrate; a second well embedded in the semiconductor substrate; a gate structure over the first well and the second well; and a raised drain structure over and in contact with the second well and spaced apart from the gate structure, the raised drain structure including a drain connection point over a surface of the second well.

The above semiconductor device further comprises a raised source structure over and in contact with the first well, the raised source structure comprising a source connection point over a surface of the first well.

In the above semiconductor device, the first well includes a lightly doped region disposed at least partially under the raised source structure and the gate structure.

In the above semiconductor device, the first well is implanted with a material having a first conductivity type; and wherein the second well is implanted with a material having a second conductivity type.

In the above semiconductor device, the first conductivity type is p-type, and the second conductivity type is n-type.

In the above semiconductor device, the raised source structure includes a first highly doped region opposite and on top of the lightly doped region.

In the above semiconductor device, the raised drain structure includes a second highly doped region on top of the second well, and the second highly doped region is more highly doped than the lightly doped region.

In the above semiconductor device, the first highly doped region, the second highly doped region, or both have a thickness between 60nm and 100 nm.

The present disclosure also provides a semiconductor device including: a first well having a first well upper surface; a second well having a second well upper surface; a gate structure disposed on the first well upper surface and the second well upper surface; and a raised source structure disposed over and in contact with the first well, the raised source structure having a source upper surface that is higher in at least one location than the first well upper surface.

The semiconductor device further includes a protrusion-type drain structure disposed above and in contact with the second well and having a drain upper surface that is higher than the second well upper surface in at least one position.

In the above semiconductor device, the gate structure has a gate upper surface higher than the source upper surface and the drain upper surface.

In the above semiconductor device, the second well includes a first Shallow Trench Isolation (STI) region and a second STI region separated from each other.

In the above semiconductor device, the convex drain is located between the first and second STI regions.

In the above semiconductor device, the first well includes a lightly doped region partially below the gate structure and having a doped upper surface lower than the source upper surface.

In the above semiconductor device, the raised source structure and the raised drain structure each include an epitaxial layer having a thickness between 60nm and 100 nm.

In the above semiconductor device, the raised source structure and the raised drain structure each include a silicide layer disposed on the epitaxial layer.

The present disclosure provides a method for fabricating a semiconductor device, comprising: embedding the first well into the semiconductor substrate; embedding the second well into the semiconductor substrate; manufacturing a gate structure partially on the first well and partially on the second well; and making at least one of: a raised source structure over and in contact with the first well, the raised source structure comprising a source connection point over a surface of the first well; and a raised drain structure over and in contact with the second well and spaced apart from the gate structure, the raised drain structure including a drain connection point over a surface of the second well.

In the above method, fabricating the raised source structure, the raised drain structure, or both comprises fabricating an epitaxial layer.

The method further comprises the following steps: and manufacturing a silicide layer on the epitaxial layer.

The method further comprises the following steps: fabricating a Shallow Trench Isolation (STI) region in the second well; and fabricating spacers on top of the STI regions separating the gate structure from the raised drain structure.

Drawings

The methods and apparatus of the present disclosure will be better understood with reference to the following drawings and description. In the drawings, like reference numerals designate corresponding parts throughout the different views.

Fig. 1 shows a cross-sectional view of a semiconductor device according to a first exemplary embodiment.

Fig. 2 shows a cross-sectional view of a semiconductor device according to a second exemplary embodiment.

Fig. 3 shows a cross-sectional view of a semiconductor device according to a third exemplary embodiment.

Fig. 4 shows a cross-sectional view of a semiconductor structure according to a fourth exemplary embodiment.

Fig. 5 shows a cross-sectional view of a semiconductor structure according to a fifth exemplary embodiment.

Fig. 6 shows a cross-sectional view of a semiconductor structure according to a sixth exemplary embodiment.

Fig. 7 illustrates an exemplary method of manufacturing a semiconductor device.

Detailed Description

Fig. 1 shows an example of a cross-sectional view of a semiconductor device 100. The semiconductor device 100 may be an n-type metal oxide semiconductor (NMOS) structure or a p-type metal oxide semiconductor (PMOS). The semiconductor device 100 includes a first well 110 and a second well 120 adjacent to each other. The first well 110 is embedded in the semiconductor substrate 102. Likewise, the second well 120 is also embedded in the semiconductor substrate 102. The first well 110 has a first well upper surface 118. The second well 120 has a second well upper surface 128.

The semiconductor substrate 102 may be a p-type substrate made of a p-type material. The p-type material may be obtained by a doping process to add atoms of a specific type to the semiconductor to increase the number of positive charge carriers (holes). Alternatively, the semiconductor substrate 102 may be an n-type substrate. The first well 110 may be formed by implanting a first material having a first conductivity type into the substrate 102. The second well 120 may be formed by implanting a second material having a second conductivity type into the substrate 102. The first material may be a p-type material, such as boron or other suitable material. The second material may be an n-type material such as phosphorus, arsenic, or other suitable material.

The semiconductor device 100 includes a raised source structure 140 over and in contact with a Lightly Doped Drain (LDD) region 115 located in the first well 110. The raised source structure 140 supports a source silicide layer 142 above the surface 118 of the first well 110. Source silicide layer 142 may include source connection points configured to connect to other electronic components. The thickness of the source silicide layer 142 may be between 10nm and 20 nm. The raised source structure 140 of the NMOS structure may include an N + region 141 and an N-LDD region 115. The thickness of the N-LDD region 115 may range between 10nm and 100 nm. The raised source structure 140 may have a uniform thickness between 20nm and 100 nm. Alternatively, the raised source structure 140 may not have a uniform thickness, and thus the height of the source upper surface 148 may vary. In both cases, the source upper surface 148 is higher than the first well upper surface 118 in at least one location.

LDD refers to a drain (H) having a high degree of dopingDD) Lightly Doped Drain (LDD) of smaller carrier concentration. The symbol "+" may denote an HDD. LDD regions may be represented by the symbol "-" followed by the letters "N" or "P," which indicate either N-type material or P-type material. Thus, the N-LDD region 115 has a lower concentration of N-type material than the N + region 141. The N + region 141 may include an epitaxial silicon layer or an extension grown on the first well 110. The N-type material concentration range of the N-LDD region can be 1 x 10¹⁷cm^-3To 5X 10¹⁸cm^-3In the meantime. The concentration range of the p-type material of the first well 110 may be 5 × 10¹⁶cm^-3To 1X 10¹⁸cm^-3In the meantime.

The first well 110 includes a Shallow Trench Isolation (STI) region 114 adjacent to the N-LDD region 115. The STI region 114 may comprise, for example, SiO₂Or dielectric material of other suitable material. The STI regions provide isolation and protection for the NMOS structure.

The semiconductor device 100 includes a raised drain structure 150 over and in contact with the second well 120 and separated from the gate structure 160. The raised drain structure 150 includes an N + region 151. The N + region 151 may include an epitaxial silicon layer or extension grown on the second well 120. The N + region 151 may have a uniform thickness between 60nm and 100 nm.

The raised drain structure 150 includes a drain silicide layer 152 over the surface 128 of the second well 120. The drain silicide layer 152 may include a drain connection point configured to connect to other electronic components. The raised drain structure 150 includes a drain upper surface 158. The thickness of the drain silicide layer 152 may be between 10nm and 20 nm. The raised drain structure 150 may have a uniform thickness between 20nm and 100 nm. In another embodiment, the raised drain structure 150 may not have a uniform thickness, and thus the drain upper surfaces 158 may not have the same height. In both cases, the drain upper surface 158 is higher than the second well upper surface 128 at least in one location.

The semiconductor device 100 further includes a gate structure 160 disposed between the raised source structure 140 and the raised drain structure 150. The gate structure 160 has a gate upper surface 168. The gate structure 160 is disposed on the first well upper surface 118 and the second well upper surface 128. The upper gate surface 168 is higher than the upper source and drain surfaces 148 and 158.

The gate structure 160 includes a gate silicide layer 163, a gate layer 165, and a gate oxide layer 166. 163 are between 10nm and 20nm thick. 165 is between 50nm and 150nm thick. 166 is between 2nm and 4nm thick. The gate structure 160 may be located between two spacers 162 and 164. The spacers are typically dielectric materials, such as SiO, although any suitable material can be used₂. A gate layer 165 is on the gate oxide layer 166. Gate suicide layer 163 is on layer 165. Any of the silicide layers 142, 152, and 163 described above may comprise a metal and silicon alloy. Silicide layers 142, 152, and 163 are used to form low resistance interconnects between other devices and semiconductor device 100.

The second well 120 includes STI regions 122 and 124. STI regions 122 and 124 may be separated from each other. A raised drain structure may be located between the two STI regions 122 and 124. Spacers 162 contact raised source structure 140 and N-LDD region 115 to provide reduced short channel effects. The spacers 164 may contact the STI regions 122 and may be separated from the raised drain structure 150, thereby keeping the raised drain away from the gate.

In an NMOS device, raised source structure 140 and raised drain structure 150 may comprise at least one of the following materials: germanium (Ge), carbon, any type of n-type material, or a compound such as Si-C.

In PMOS, the raised source structure 140 and the raised drain structure 150 may comprise at least one of the following materials: germanium (Ge), carbon, any type of p-type material, or a compound such as SiGe.

Fig. 2 shows a cross-sectional view of a semiconductor device 200 of a second example. One of the differences between device 100 and device 200 is that the raised drain structure 150 in device 200 is partially in the second well 120. The drain region may be recessed prior to forming the epitaxial layer to create a raised drain, which may reduce drain resistance. The drain upper surface is higher in at least one location than the second well upper surface 128. The raised drain structure 150 may have a different or the same thickness as the raised source structure 140. The second well upper surface 128 may have a different or same height as the first well upper surface 118.

Fig. 3 shows a cross-sectional view of a semiconductor device 300 according to a third exemplary embodiment. One of the differences between the devices 100 and 300 is that the raised source structure 140 is partially in the first well 110. The source upper surface is higher in at least one location than the first well upper surface 118. This will introduce more strain to enhance charge mobility and reduce resistance. It should be noted that although the layout is drawn as a square, the actual shape may be slightly different from the drawn layout shape. According to the shape, mobility can be further enhanced. It is noted that both the raised source structure 140 and the raised drain structure 150 may have other shapes, such as trapezoidal, triangular, or circular shapes in cross-sectional view.

In fig. 1-3, the structure includes a p-n junction with a potential barrier created by adjacent n-type and p-type materials. In the absence of a bias on the gate structure 160, two p-n junctions exist in series between the raised source structure 140 and the raised drain structure 150. One such junction is between the raised drain structure 150 and the substrate 102 and the other junction is between the substrate 102 and the raised source structure 140. These p-n junctions prevent current from flowing from source structure 140 to drain structure 150 upon application of a source-to-drain voltage.

Furthermore, a heterojunction may be formed between the raised source structure 140 and the first well 110 due to the different semiconductor materials located in the source structure 140 and the first well 110. The heterojunction can form a higher barrier and increase the breakdown voltage of the semiconductor device.

When fabricating a semiconductor device, it may be more preferable to fabricate multiple semiconductor devices simultaneously in a single process. Fig. 4-6 show examples of cross-sectional views of how two semiconductor structures having the advantage of higher breakdown voltages can be fabricated side-by-side.

Fig. 4 shows a cross-sectional view of a semiconductor structure 400 according to a fourth exemplary embodiment. The semiconductor structure 400 includes two side-by-side NMOS structures 206 and 207. The NMOS structure 206 has substantially the same structure as the semiconductor device 100 in fig. 1. NMOS structure 207 is substantially symmetrical to NMOS structure 206 along line 205 in the middle of semiconductor structure 400.

In fig. 4, a semiconductor structure 400 includes a first well 210, a second well 220, and a third well 230 embedded (implanted) on a substrate 202. The substrate may be a p-type substrate implanted with a p-type material. The first and second wells 210 and 220 may be implanted with materials having different conductivity types. The first and third wells 210 and 230 may be implanted with materials having the same conductivity type. For example, the first and third wells 210 and 230 may be implanted with p-type material while the second well 220 may be implanted with n-type material.

The semiconductor structure 206 includes a raised source structure 240 over and in contact with the lightly doped region 215 in the first well 210. The raised source structure 240 includes a source silicide layer 242 over the surface 218 of the first well 210. Source silicide layer 242 may include source connection points configured to connect to other electronic components. The raised source structure 240 may include an N + region 241 and an N-LDD region 215. The thickness of the N-LDD region 215 may range between 20nm and 100 nm. The raised source structure 240 may have a uniform thickness between 60nm and 100 nm. The source upper surface 248 is higher than the first well upper surface 218 at least at one location.

The raised drain structure 250 includes a drain silicide layer 252 over the surface 228 of the second well 220. The drain silicide layer 252 may include drain connection points configured to connect to other electronic components. The raised drain structure 250 includes an N + region 251. The raised drain structure 250 includes a drain upper surface 258. The raised drain structure 250 may have a uniform thickness between 60nm and 100 nm. The drain upper surface 258 is higher than the second well upper surface 228 at least in one location.

The semiconductor structure 207 includes a raised source structure 280 over and in contact with the lightly doped region 235 in the third well 230. The raised source structure 280 includes a source silicide layer 282 over the surface 238 of the third well 230. Source silicide layer 282 may include source connection points configured to connect to other electronic components. Raised source structure 280 may include N + regions 281 and N-LDD regions 235. The thickness of the N-LDD region 235 may range between 20nm and 100 nm. The raised source structure 280 may have a uniform thickness between 60nm and 100 nm. The source upper surface 288 is higher than the third well upper surface 238 at least at one location.

Fig. 5 shows a cross-sectional view of a semiconductor structure 500 according to a fifth exemplary embodiment. One of the differences between the fifth exemplary embodiment 500 and the fourth exemplary embodiment 400 is that the raised drain structure 250 is partially in the second well 220. The drain upper surface is higher in at least one location than the second well upper surface 228. The raised drain structure 250 may have a different or the same thickness as the raised source structure 240 or 280. The second well upper surface 228 may have a different or same height as the well upper surfaces 218 and 238.

Fig. 6 shows a cross-sectional view of a semiconductor structure 600 according to a sixth exemplary embodiment. In this embodiment, the raised source structure 240 is partially in the first well 210, and the raised source structure 280 is partially in the third well 230. The source upper surface 242 is higher than the well upper surface 218 at least in one location. The source upper surface 282 is higher than the well upper surface 238 at least in one location. Similar to the semiconductor structure 300 of fig. 3, the raised source structure 240 or 280 may have a trapezoidal shape or other shapes such as a triangle or a circle in a cross-sectional view.

Generally, the disclosed semiconductor structures can be fabricated using either gate-first or gate-last fabrication methods. In the gate-first approach, the gate is formed earlier and then serves as a mask for the source and drain structures. After embedding the source and drain, the wafer may need to be annealed to repair the damage caused during the implantation. Primarily, the gate-last approach uses a sacrificial gate to shield the implant, which is subsequently removed, and a new gate stack is built after the anneal step. In other words, the actual gate is built after the source and drain structures are formed.

Fig. 7 illustrates an exemplary fabrication process 700 for fabricating a semiconductor device with increased breakdown voltage. The method 700 is for illustration only and the processes described below need not be performed in the order described. Likewise, other fabrication steps may be introduced.

In fabrication process 700, STI regions are fabricated by etching a semiconductor region in a semiconductor substrate (710). The process may include using a material such as SiO₂(although any suitable material may be used) to deposit the etched semiconductor substrate to form shallow trench isolation regions. For example, fabricating an STI region adjacent to the source in the first well and another STI region adjacent to the drain in the second well provides insulation and protection to the transistor. Forming an additional STI region between the gate and the drain increases the breakdown voltage of the transistor. The steps may include fabricating a first STI region in the first well and a second STI region in the second well.

The first well is fabricated by embedding the first well in a semiconductor substrate (720). This may include implanting the semiconductor substrate with appropriate dopants to form a P-well or an N-well. For example, a P-type material such as boron is implanted into the substrate to form a P-well, and an N-type material such as phosphorus or arsenic is implanted into the substrate to form an N-well.

The second well is fabricated by embedding the semiconductor substrate in the semiconductor substrate (730). This may include implanting the semiconductor substrate with appropriate dopants to form a P-well or an N-well. The first well and the second well have different conductivity types. For example, the second well may be an N-well and the first well a P-well. When the first well is an N-well, the second well may be a P-well.

A gate structure is formed by fabricating at least one semiconductor substrate partially over the first well and partially over the second well 740. This may be included inPolysilicon is deposited over the top of the entire semiconductor structure and etched to define a gate region partially over the first well and partially over the second well. This may include embedding a semiconductor substrate with polysilicon (although any suitable material may be used) on top of the gate oxide to form a gate structure. The gate may be heavily doped to avoid poly depletion that may reduce gate capacitance. The gate may also be lightly doped to increase the breakdown voltage of the gate oxide layer, which may reduce drive strength. Therefore, the gate electrode is doped with a suitable dopant according to the purpose of the application. For example, the gate may be implanted 10¹⁸cm^-3To 10²⁰cm^-3Of the order of magnitude of (d). Implanting polysilicon with a lighter implant of appropriate impurities increases the breakdown voltage of the gate oxide of the transistor. Lightly implanting N-type material into the polysilicon to form N-regions creates the gates of NMOS devices, while lightly implanting P-type material into the polysilicon to form P-regions creates the gates of PMOS devices. In summary, the gate is heavily implanted 10²⁰cm^-3To increase the performance of the transistor. In a gate-first or gate-last high-K metal gate fabrication process, the gate is formed of a high-K dielectric and the gate is formed of a work-function metal and additional layers of suitable materials.

The spacers are formed by depositing a material such as SiO on top of the semiconductor substrate₂Etc. to form spacers 750. This may include making spacers on the sides of the polysilicon or dummy polysilicon of the gate structure after partially embedding the LDD under the gate structure. The spacers are adjacent to the gate structure. For example, one spacer is adjacent to and in contact with the source structure and separates the gate structure and the source structure. Another spacer is adjacent to the drain structure and in contact with the gate structure and the STI region, and separates the gate structure and the raised drain structure.

A raised source structure is formed by embedding a source semiconductor layer at least partially over the first well and in contact with the first well (760). This may include embedding LDD regions in the first well and fabricating HDD regions by growing an epitaxial silicon layer over the LDD regions. Alternatively, this step may include embedding the HDD region after recessing the source region on the LDD region. As shown in fig. 1 to 6, subsequently, the embedded HDD region is partially in the first well, and the source upper surface is formed over the first well surface. This step may also include embedding a silicide layer on the HDD region.

A raised drain structure is fabricated by embedding a drain semiconductor region in the second well (770). This may include fabricating the HDD region on and in contact with the second well and separate from the gate structure. This step may also include embedding a silicide layer on the HDD region. The drain structure is fabricated to include a drain connection point over the second well surface. The drain structure is fabricated to include a drain connection point above the second well surface as shown in fig. 1-6.

The raised source structure and the raised drain structure may be fabricated simultaneously or separately. When fabricated simultaneously, one of the advantages is that the device is symmetrical. When fabricated separately, one of the advantages is that junction leakage can be reduced for non-raised drain structures, since heterojunctions tend to introduce higher leakage.

The method may further comprise forming a connection between the fabricated transistor and the metallization layer by depositing a metal on top of the polysilicon and then forming an alloy to create a silicide on top of the gate, source and drain of the transistor (although any suitable material may be used). The metallization layers form interconnections between the fabricated transistors and other devices. The region of the semiconductor substrate between the gate and the drain may be devoid of silicide. In other words, there is a gap in the silicide layer between the gate and the drain, requiring any silicide removal in this region.

The embodiments in the present disclosure are for illustrative purposes only and are not limiting. Many other embodiments and implementations are possible within the scope of the systems and methods. Accordingly, there is no limitation to the apparatus and methods except insofar as the appended claims and their equivalents are concerned.

Claims (10)

1. A semiconductor device, comprising:

a first well embedded in the semiconductor substrate;

a second well embedded in the semiconductor substrate;

a gate structure over the first well and the second well; and

a raised drain structure over and in contact with the second well and spaced apart from the gate structure, the raised drain structure comprising a drain connection point over a surface of the second well.

2. The semiconductor device of claim 1, further comprising a raised source structure over and in contact with the first well, the raised source structure comprising a source connection point over a surface of the first well.

3. The semiconductor device of claim 2, wherein the first well comprises a lightly doped region disposed at least partially under the raised source structure and the gate structure.

4. The semiconductor device as set forth in claim 3,

wherein the first well is implanted with a material having a first conductivity type; and

wherein the second well is implanted with a material having a second conductivity type.

5. The semiconductor device of claim 4, wherein the raised source structure comprises a first highly doped region opposite and on top of the lightly doped region.

6. The semiconductor device of claim 5, wherein the raised drain structure comprises a second highly doped region on top of the second well, and the second highly doped region is more highly doped than the lightly doped region.

7. A semiconductor device, comprising:

a first well having a first well upper surface;

a second well having a second well upper surface;

a gate structure disposed on the first well upper surface and the second well upper surface; and

a raised source structure disposed over and in contact with the first well, the raised source structure having a source upper surface that is higher in at least one location than the first well upper surface.

8. The semiconductor device of claim 7, further comprising a raised drain structure disposed over and in contact with the second well and having a drain upper surface that is higher in at least one location than the second well upper surface.

9. The semiconductor device of claim 8, wherein the gate structure has a higher gate upper surface than the source and drain upper surfaces.

10. A method for fabricating a semiconductor device, comprising:

embedding the first well into the semiconductor substrate;

embedding a second well into the semiconductor substrate;

manufacturing a gate structure partially on the first well and partially on the second well; and

making at least one of:

a raised source structure over and in contact with the first well, the raised source structure comprising a source connection point over a surface of the first well; and

a raised drain structure over and in contact with the second well and spaced apart from the gate structure, the raised drain structure comprising a drain connection point over a surface of the second well.