HK1103482A - All digital implementation of clock spectrum spreading (dither) for low power/die area - Google Patents

Description

All-digital implementation of clock spectrum spreading (jitter) for low power/die area

Technical Field

The present invention relates generally to integrated circuits, and more particularly to digital spreading of clock spectra in digital circuits.

Background

Spreading the clock spectrum generally includes spreading the power of the clock pulses over a range of frequencies. Fig. 1 is a simplified schematic diagram of a first clock string 100 and a spread spectrum clock string 105. The pulses in the spread spectrum clock train 105 are spread spectrum pulses that may be generated from the clock pulses in the first clock train 100. The clock edges of the spread spectrum pulses move inward and outward as indicated by the arrows in fig. 1. Spread spectrum clock trains are typically generated for applications where jitter sensitivity is typically low and/or where it is desirable to reduce the peak power of the clock pulses.

Conventional circuits configured to spread the spectrum of a clock train typically include both digital and analog circuits, which typically include a digital modulator and an analog phase interpolator. The digital modulator is configured to receive a clock train (e.g., a first clock train) from a clock generator. The clock string may be a digital clock string. The digital modulator may be configured to generate a jitter waveform using a jitter modulation waveform (jitter waveform) to modulate the clock train. The dithered waveform may then be passed to an analog phase interpolator configured to phase interpolate the dithered waveform. Based on the phase interpolation of the dithering waveform, the analog phase interpolator is configured to generate and output a spread spectrum clock train.

These conventional circuits configured for spreading the spectrum of a clock string have a number of inherent disadvantages, particularly for low power circuit applications. For example, a typical digital modulator configured to modulate a clock train generally operates at the clock frequency of the clock train, which is generally the frequency of a relatively high free-running clock (e.g., generated by a crystal oscillator). Because conventional digital modulators are configured to operate at a free-running clock frequency, these digital modulators draw relatively high currents.

Not only do the digital modulators included in these conventional circuits generally draw relatively high currents, but the analog phase interpolators included in these conventional circuits also generally draw relatively high currents. For example, an analog phase interpolator may draw as much current as a digital modulator. Furthermore, since these conventional circuits typically include analog devices (i.e., analog phase interpolators), the shape of the spread spectrum clock pulses and the amount of power reduction of these clock pulses are typically limited by the linear characteristics of the analog phase interpolators. Analog phase interpolators with relatively high linearity are costly to design and manufacture, and are relatively large. In addition, because these conventional circuits typically include both digital and analog circuits, they may occupy a relatively large amount of die space, which may make these circuits expensive to manufacture.

Accordingly, there is a need for new circuits configured for spreading the frequency spectrum of a clock string that draw relatively less current and occupy relatively less die area than conventional circuits configured to provide such functionality.

Cross reference to related applications

This application claims priority from: U.S. provisional patent application No.60/704,510, entitled "ALLDIGITAL IMPLEMENTATION OF CLOCK SPECTRUM SPREADING (DITHER) FOR LOW POWER/DIE AREA" filed on 8/1/2005; U.S. provisional patent application No.60/722,731 entitled "ALL DIGITAL IMPLEMENTATION OF CLOCK SPECTRUM SPREADING (DITHER) FORLOW POWER/DIE AREA", filed on 30.9.2005; and U.S. patent application No.11/246,328 entitled "ALL DIGITAL IMPLEMENTATION OFCLOCK SPECTRUM SPREADING (DITHER) FOR LOW POWER/DIEAREA" filed on 6.10.2005, the disclosures of all of which are incorporated herein by reference in their entirety.

Disclosure of Invention

Accordingly, embodiments of the present invention provide circuits, methods, apparatus, codes and/or apparatus for adjusting a clock string, in particular for spreading the frequency spectrum of the clock string.

Exemplary embodiments of the present invention include an apparatus for spreading a clock spectrum, and more particularly, an apparatus comprising: means for generating a phase value based on the frequency modulation waveform; and means for dividing the frequency of the clock train by a divider value to generate a dithered clock train phase modulated with said phase value, wherein the divider value comprises a fixed value plus said phase value. The exemplary embodiments also include means for accumulating the jittered clock trains to generate frequency modulated waveforms; and means for accumulating the frequency modulation waveforms to generate a phase modulation signal and generating a phase value based on the phase modulation signal. The exemplary embodiments also include means for tracking and locking the modulation of the jittered clock train. The exemplary embodiments also include means for generating a spread spectrum clock train by tracking the modulation of the jittered clock train and filtering the jittered clock train, the spread spectrum clock train being a spectral spread of the clock train. The frequency modulation waveform is periodic or quasi-periodic. The frequency modulation waveform is a triangular wave. The frequency modulated waveform is a digital signal. The clock string is a digital clock string. The jittered clock string is a digital clock string. The phase value is proportional to the deviation of the frequency modulated waveform from the center of the frequency modulated waveform. The exemplary embodiment also includes means for multiplying the frequency of the jittered clock train by a multiplier value. The average frequency of the spread spectrum clock train is equal to the frequency of the clock train multiplied by the multiplier value divided by the fixed value. Exemplary embodiments further include: means for splitting the phase modulated signal into a first phase modulated signal and a second phase modulated signal; means for delaying the second phase modulated signal in time relative to the first phase modulated signal; and means for thereafter calculating a difference between the first phase modulated signal and the second phase modulated signal to generate a phase value. An exemplary embodiment further comprises means for adding the phase value to the fixed value to generate a divider value.

Another exemplary embodiment of the present invention includes an apparatus for spreading a frequency spectrum of a clock train, and more particularly, includes: means for generating a jittered clock train, and means for accumulating the jittered clock train to generate a frequency modulated waveform. Exemplary embodiments further include: means for accumulating the frequency modulated waveforms to generate a phase modulated signal; and means for generating a divider value that varies in time based on the phase modulation signal. The example embodiments also include means for digitally modulating the clock train based on the divider value that varies in time. The exemplary embodiment also includes means for tracking and filtering the modulation of the jittered clock train to generate a second clock train after spreading the first-mentioned clock train. The divider value that varies in time is equal to the fixed divider value plus the phase value. The phase value is determined from the frequency modulation waveform. Exemplary embodiments also include means for generating a phase value based on the phase modulation signal. Exemplary embodiments further include: means for splitting the phase modulated signal into first and second phase modulated signals; and means for delaying the second phase modulated signal relative to the first phase modulated signal and then calculating the difference between the first phase modulated signal and the second phase modulated signal to generate the phase value. An example embodiment also includes means for adding the phase value to the fixed divider value. The phase value is proportional to the deviation of the digital frequency modulation waveform from the center of the digital frequency modulation waveform. The frequency modulation waveform is periodic or quasi-periodic. The frequency modulation waveform is a triangular wave. The exemplary embodiments also include means for generating a clock string.

According to a particular embodiment of the clock spreading means, the first clock string is a digital clock string. The closed loop control circuit arrangement is configured to multiply the frequency of the jittered clock train by a fixed multiplier value. The temporally varying divider value is a fixed divider value plus a phase value, and the average frequency of the second clock train is equal to the frequency of the first clock train multiplied by the fixed multiplier value divided by the fixed divider value. Exemplary embodiments further include means for calculating a difference between a first portion of the phase modulated signal and a second portion of the phase modulated signal, wherein the second portion is delayed in time relative to the first portion; the difference is the phase value. An exemplary embodiment further comprises means for adding the phase value to a fixed divider value to generate a divider value that varies in time. The means for tracking the modulation of the jittered clock train and filtering it to generate the second clock train is a phase locked loop circuit.

The features and advantages of the present invention may be better understood with reference to the following detailed description and accompanying drawings.

Drawings

FIG. 1 is a simplified schematic diagram of a first clock string and a spread spectrum clock string that may be generated from the first clock string in accordance with one embodiment of the present invention;

FIG. 2 is a simplified schematic diagram of a digital circuit configured to generate a spread spectrum clock train in accordance with one embodiment of the present invention;

FIG. 3 is a high level flow chart with steps for generating a spread spectrum clock train in accordance with one embodiment of the present invention; and

fig. 4A through 4H illustrate various implementations of exemplary embodiments of the present invention.

Detailed Description

The present invention generally provides a digital circuit arrangement and a digital circuit method for conditioning a digital signal. More specifically, the present invention provides digital circuit arrangements and digital circuit methods for spreading a clock spectrum.

Spreading the clock spectrum (e.g., the digital clock spectrum) includes spreading the power of the clock pulses of the clock train over a range of frequencies. Fig. 1 is a simplified schematic diagram of a first clock string 100 and a spread spectrum clock string 105 that may be generated from the first clock string according to one embodiment of the present invention. The edges of the spread spectrum clock train are jittered (diter) relative to the first clock train as indicated by the arrows in fig. 1. The clock pulses of the first clock train may be digitally adjusted to generate spread spectrum clock pulses in the spread spectrum clock train.

Fig. 2 is a simplified schematic diagram of a circuit 200 according to one embodiment of the invention. The circuit 200 includes a clock generator 205, a variable divider 210, a first accumulator 215, a second accumulator 220, a delay circuit 225, a first adder 230, a second adder 235, and a Phase Locked Loop (PLL) 240. The delay circuit 225, the first adder 230 and the second adder 235 are sometimes referred to herein as phase value calculators. According to one embodiment, each of the circuits listed above is a digital circuit. According to an alternative embodiment, the PLL may be a mixed signal circuit. The circuit 200 is configured to generate the first clock string 100 and condition the first clock string to generate the spread spectrum clock string 105. The frequency "f 1" of the first clock train may be the oscillation frequency of a free running clock (e.g., a crystal oscillator). The average frequency "f 2" of the spread spectrum clock train may be less than f1, equal to f1, or greater than f 1.

According to one embodiment, the clock pulse generator 205 is configured to generate the first clock train 100, the first clock train 100 may be a digital clock train. The first clock train is transmitted from the output of clock generator 205 to the input of variable divider 210. The variable divider 210 is configured to generate a jittered clock train 245 having a frequency "f 3". More specifically, the variable divider is configured to divide the frequency f1 of the clock train by a "divider" value N + δ, where f3 is equal to f1/(N + δ). N may be a fixed value (e.g., 128) and δ may be a time-varying value (referred to herein as a phase value). The generation of the phase values will be described in detail below. The phase value may be relatively small compared to N. For example, the absolute value of δ may be 10 times less than N or less (e.g., 20 times less than N). The value of N may be user-specified or may be specified by other circuitry (not shown) coupled to the circuit 200. The value of N may be specified according to the particular application for which the circuit 200 is to be used.

A jittered clock train 245 may be transferred from the output of the variable divider to the input of accumulator 215 and the input of PLL 240, and accumulator 215 (sometimes referred to herein as a frequency accumulator) may be configured to accumulate the jittered clock train and generate therefrom a frequency modulation waveform 250, which frequency modulation waveform 250 may be a digital signal. The frequency modulation waveform may be periodic or quasi-periodic and may have a variety of shapes, e.g., triangular, saw tooth, teardrop, variable, etc. The frequency modulation waveform is used by the circuit 200 to modulate the phase of the first clock train 100 to generate a jittered clock train having jittered edges. Specifically, the frequency modulated waveform is transferred from the output of accumulator 215 to the input of accumulator 220 (sometimes referred to herein as a phase accumulator). Accumulator 220 is configured to accumulate the frequency modulation waveform and is also configured to receive the jittered clock train from the variable frequency divider. Accumulator 220 is also configured to generate a phase modulation signal 255 from the accumulated frequency modulation waveform.

According to one embodiment, the phase value is proportional to the deviation of the frequency modulation waveform from the center of the frequency modulation waveform. For example, if the frequency modulation waveform is a triangular wave, the phase value may be proportional to the value of the triangular wave above or below the reference line 260. More specifically, to calculate the phase value, the phase modulation signal is communicated to adder 230 via two circuit paths 265a and 265 b. Circuit path 265a may be an undelayed path. Circuit path 265b may include a delay circuit 225, the delay circuit 225 configured to delay the phase modulated signal in the second circuit path relative to the phase modulated signal in the first circuit path. The delay circuit 225 may delay the phase modulated signal in the circuit path 265b based on the received jittered clock 245. The adder 230 is configured to subtract the delayed phase modulation signal from the undelayed phase modulation signal. In other words, the adder 230 is configured to calculate the difference between the phase modulated signals at different "time points". The calculated difference of the phase modulation signals at different points in time is the phase value δ. The phase value δ is passed from adder 230 to adder 235, adder 235 being configured to add the phase value to a fixed value N to produce a divider value N + δ. Depending on, for example, the amount by which the phase modulated signal is delayed by the delay circuit, δ may be a positive value or may be a negative value.

Since the frequency modulation waveform changes over time, the phase value also changes over time. For example, as the frequency modulation waveform rises, the phase value similarly rises, and as the frequency modulation waveform falls, the phase value similarly falls. As the phase modulation waveform changes, the phase value may change from a positive value to a negative value. Furthermore, since the phase value changes with time, the divider value N + δ also changes with time. Furthermore, since the divider values change in time, the variable divider divides the frequency f1 of the first clock train by these temporally changing divider values. For example, as the divider value increases, the edges of the jittered clock train generated by the variable divider extend (i.e., the frequency of the jittered clock train decreases), and as the divider value decreases, the edges of the jittered clock train shrink (i.e., the frequency of the jittered clock train increases). This phase change of the jittered clock train changes approximately in accordance with the frequency of the frequency modulation waveform.

According to one embodiment, the frequency of the phase change of the jittered clock train is within the operational detection range of the PLL 240. Thus, the PLL can track and lock onto the modulation of the jittered clock train to filter the jittered clock train to generate a spread spectrum clock train. As the edges (i.e., phase) of the jittered clock train are jittered, the edges of the clock pulses of the spread spectrum clock train are similarly jittered.

According to one embodiment, the PLL may be configured to multiply the frequency of the jittered clock train by a multiplier value "M" such that the average frequency f2 of the spread spectrum clock train 105 is equal to (M/N) · f 1. The value of M may be adjusted to tune the frequency f2 to various desired values.

Fig. 3 is a high level flow chart with steps for spreading the spectrum of clock pulses making up clock train 100 to generate spread spectrum clock train 105. It will be understood that the steps of the high level flow chart described are merely exemplary, and that various steps may be replaced with alternative steps, combined, and/or eliminated without departing from the embodiments represented by the high level flow chart. In an initial step 300, a variable divider receives a clock train, and a divider value that varies in time. In step 305, the variable divider divides the frequency of the clock train by a temporally varying divider value to phase modulate the clock train to generate a dithered clock train. The divider value that varies in time comprises a fixed value plus a phase value that varies in time. In step 310, a frequency accumulator receives the jittered clock train from the variable frequency divider and generates a frequency modulated waveform based on the accumulation of the jittered clock train. In step 315, the phase accumulator receives the frequency modulation waveform from the frequency accumulator and generates a phase modulation signal based on the accumulation of the frequency modulation waveform. In step 320, the phase value calculator calculates a difference between different time points of the phase modulation signal; the difference is the phase value. In step 325, the phase value is added to a fixed value to generate a divider value that varies in time. In step 330, a Phase Locked Loop (PLL) receives a jittered clock train from the variable frequency divider. In step 335, the PLL tracks the modulation of the jittered clock train and filters the jittered clock train to generate and output a spread spectrum clock train.

Reference is now made to fig. 4A-4G, which illustrate various exemplary implementations of the present invention. Referring to fig. 4A, the present invention may be implemented in a hard disk drive 400. The present invention may implement one or both of signal processing and/or control circuits, which are generally designated 402 in fig. 4A. In some implementations, signal processing and/or control circuit 402 and/or other circuits (not shown) in HDD400 may process data, perform coding and/or encryption, perform calculations, and/or format data output to magnetic storage media 406 and/or data received from magnetic storage media 406.

HDD400 may communicate with the following devices via one or more wired or wireless communication links 408: a host device (not shown), such as a computer; a mobile computing device, such as a personal digital assistant, cellular telephone, media player, or MP3 player, among others; and/or other devices. HDD400 may be connected to memory 409, such as Random Access Memory (RAM), low latency nonvolatile memory such as flash memory, Read Only Memory (ROM), and/or other suitable electronic data storage.

Referring now to fig. 4B, the present invention may be implemented in a Digital Versatile Disk (DVD) drive 410. The present invention may implement one or both of the signal processing and/or control circuits of the DVD drive 410, which are generally designated 412 in fig. 4B, and/or the mass data storage device 418. Signal processing and/or control circuits 412 and/or other circuits (not shown) in DVD 410 may process data, perform coding and/or encryption, perform calculations, and/or format data read from optical storage media 416 and/or data written to optical storage media 416. In some implementations, the signal processing and/or control circuits 412 and/or other circuits (not shown) in the DVD 410 can also perform other functions, such as encoding and/or decoding associated with a DVD drive, and/or any other signal processing functions.

DVD drive 410 may communicate with output devices (not shown), such as computers, televisions, and other devices, via one or more wired or wireless communication links 417. The DVD 410 may communicate with a mass data storage device 418 that stores data in a nonvolatile manner. The mass data storage device 418 may include a Hard Disk Drive (HDD), such as that shown in fig. 4A. The HDD may be a mini HDD that includes one or more platters that are less than about 1.8 "in diameter. The DVD 410 may be connected to memory 419 such as RAM, ROM, low latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage.

Referring now to fig. 4C, the present invention may be implemented in a High Definition Television (HDTV) 420. The present invention may implement one or both of the signal processing and/or control circuits of the HDTV 420, which are generally indicated at 422 in figure 4C, and/or a WLAN interface and/or mass data storage device. The HDTV 420 receives HDTV input signals in either a wired or wireless format and generates HDTV output signals for a display 426. In some implementations, signal processing circuit and/or control circuit 422 and/or other circuits (not shown) of HDTV 420 may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other type of HDTV processing that may be required.

The HDTV 420 may communicate with mass data storage 427 that stores data in a nonvolatile form such as optical and/or magnetic storage devices. At least one HDD may have the configuration shown in fig. 4A and/or at least one DVD may have the configuration shown in fig. 4B. The HDD may be a mini HDD that includes one or more platters that are less than about 1.8 "in diameter. HDTV 420 may be connected to memory 428 such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. HDTV 420 may also support connections with a WLAN via a WLAN network interface 429.

Referring now to fig. 4D, the present invention may implement a control system for a vehicle 430, as well as a WLAN interface and/or mass storage device for the vehicle control system. In some implementations, the present invention implements a drive train control system 432 that receives input from one or more sensors, such as temperature sensors, pressure sensors, rotation sensors, airflow sensors, and/or any other suitable sensors, and/or generates one or more output control signals, such as engine operating parameters, transmission operating parameters, and/or other control signals.

The present invention may also be implemented in other control systems 440 of the vehicle 430. The control system 440 may similarly receive signals from input sensors 442 and/or output control signals to one or more output devices 444. In some implementations, the control system 440 may be part of an Antilock Braking System (ABS), a navigation system, a telematics system, a vehicle telematics system, a route deviation system, an adaptive cruise control system, a vehicle entertainment system (e.g., stereo, DVD, CD, etc.). Other implementations are also contemplated.

The powertrain control system 432 may communicate with mass data storage 446 that stores data in a nonvolatile form. The mass data storage 446 may include optical and/or magnetic storage devices, such as hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown in fig. 4A and/or at least one DVD may have the configuration shown in fig. 4B. The HDD may be a mini HDD that includes one or more platters that are less than about 1.8 "in diameter. The powertrain control system 432 may be connected to memory 447 such as RAM, ROM, low latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage. The powertrain control system 432 may also support connections with a WLAN via a WLAN network interface 448. The control system 440 may also include a mass data storage device, memory, and/or a WLAN interface (all not shown).

Referring now to fig. 4E, the present invention may be implemented in a cellular telephone 450 that includes a cellular antenna 451. The present invention may implement one or both of the signal processing and/or control circuits of the cellular telephone 450, which are generally designated 452 in fig. 4E, as well as a WLAN interface and/or mass data storage device. In some implementations, the cellular phone 450 includes a microphone 456, an audio output 458 (e.g., a speaker and/or audio output jack), a display 460, and/or an input device 462 (e.g., a keypad, pointing device, voice actuation, and/or other input device). Signal processing circuitry and/or control circuitry 452 and/or other circuitry (not shown) in cellular telephone 450 may process data, perform coding and/or encryption, perform calculations, format data and/or perform other cellular telephone functions.

The cellular phone 450 may communicate with a mass data storage 464 that stores data in a nonvolatile form, such as optical and/or magnetic storage devices (e.g., hard disk drives HDD and/or DVDs). At least one HDD may have the configuration shown in fig. 4A and/or at least one DVD may have the configuration shown in fig. 4B. The HDD may be a mini HDD that includes one or more platters that are less than about 1.8 "in diameter. The cellular phone 450 may be connected to memory 466 such as RAM, ROM, low latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage. The cellular phone 450 may also support connections with a WLAN via a WLAN network interface 468.

Referring now to fig. 4F, the present invention may be implemented in a set top box 480. The present invention may implement one or both of the signal processing and/or control circuits of the set top box 480 (which are generally designated 484 in fig. 4F), as well as a WLAN interface and/or mass data storage device. The set top box 480 receives signals from a source such as a broadband source and outputs standard and/or high definition audio/video signals suitable for a display 488 such as a television and/or monitor and/or other video and/or audio output device. The signal processing and/or control circuits 484 and/or other circuits (not shown) of the set top box 480 may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other set top box function.

The set top box 480 may communicate with mass data storage 490 that stores data in a nonvolatile manner. The mass data storage device 490 may include optical and/or magnetic storage devices, such as hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown in fig. 4A and/or at least one DVD may have the configuration shown in fig. 4B. The HDD may be a mini HDD that includes one or more platters that are less than about 1.8 "in diameter. The set top box 480 may be connected to memory 494 such as RAM, ROM, low latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage. The set top box 480 may also support connections with a WLAN via a WLAN network interface 496.

Referring now to fig. 4G, the present invention may be implemented in a media player 472. The present invention may implement one or both of the signal processing and/or control circuits of the media player 472, which are generally designated 471 in fig. 4G, as well as the WLAN interface and/or mass data storage device. In some implementations, the media player 472 includes a display 476 and/or a user input 477, such as a keypad, touchpad, or the like. In some implementations, the media player 472 may employ a Graphical User Interface (GUI) that typically employs menus, drop down menus, icons, and/or a point-and-click interface with the display 476 and/or the user input 477. The media player 472 also includes an audio output 475, such as a speaker and/or an audio output jack. The signal processing and/or control circuits 471 and/or other circuits (not shown) of the media player 472 may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other media player function.

The media player 472 may communicate with a mass data storage device 470 that stores data, such as compressed audio and/or video content, in a non-volatile manner. In some implementations, the compressed audio files include files compliant with the MP3 format or other suitable compressed audio and/or video formats. The mass data storage device may comprise an optical and/or magnetic storage device, such as a hard disk drive HDD and/or a DVD. At least one HDD may have the configuration shown in fig. 4A and/or at least one DVD may have the configuration shown in fig. 4B. The HDD may be a mini HDD that includes one or more platters that are less than about 1.8 "in diameter. The media player 472 may be connected to memory 473 such as RAM, ROM, low latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage. The media player 472 may also support a connection to a WLAN via a WLAN network interface 474.

Referring now to fig. 4H, the present invention may be implemented in a voice over ip (voip) phone 483 that may include an antenna 439. The present invention may implement one or both of the signal processing and/or control circuits of VoIP phone 483 (which are generally designated 482 in fig. 4H), as well as a wireless interface and/or a mass data storage device. In some implementations, the VoIP phone 483 portion includes a microphone 487, an audio output 489 (e.g., a speaker and/or audio output jack), a display monitor 491, an input device 492 (e.g., a keypad, pointing device, voice execution, and/or other input device), and a wireless fidelity (Wi-Fi) communication module 486. Signal processing and/or control circuits 482 and/or other circuits (not shown) of VoIP phone 483 may process data, perform coding and/or encryption, perform calculations, format data and/or perform other VoIP phone functions.

VoIP phone 483 may communicate with mass data storage device 502 that stores data in a nonvolatile form, such as optical and/or magnetic storage devices (e.g., hard disk drives HDD and/or DVDs). At least one HDD may have the configuration shown in fig. 4A and/or at least one DVD may have the configuration shown in fig. 4B. The HDD may be a mini HDD that includes one or more platters that are less than about 1.8 "in diameter. VoIP phone 483 may be connected to memory 485 and memory 485 may be RAM, ROM, low latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage. VoIP phone 483 is configured to establish a communication link with a VoIP network (not shown) via Wi-Fi communication module 486. Implementations other than these are contemplated.

It should be understood that the above-described exemplary embodiments are for illustrative purposes only and that various modifications and changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims. For example, although the exemplary embodiment 200 is described and illustrated as including a phase-locked loop circuit, it should be understood that other embodiments may use a frequency-locked loop, a delay-locked loop, or other closed-loop control circuit adapted to track and filter the phase and frequency of a jittered clock train. Accordingly, the above description should not be taken as limiting the scope of the invention, which is defined by the claims.

Claims (27)

1. A method for spreading a spectrum of a clock train, comprising:

generating a phase value based on the frequency modulation waveform;

dividing the frequency of the clock train by a divider value to generate a dithered clock train phase modulated with the phase value, wherein the divider value comprises a fixed value plus the phase value;

accumulating the jittered clock trains to generate the frequency modulation waveform;

accumulating the frequency modulation waveforms to generate phase modulation waveforms and generating the phase values based on the phase modulation waveforms;

tracking and locking modulation of the jittered clock train;

generating a spread spectrum clock train based on the tracking and locking steps, the spread spectrum clock train being a spectral spread of the clock train.

2. The method of claim 1, wherein the frequency modulation waveform is periodic or quasi-periodic.

3. The method of claim 2, wherein the frequency modulation waveform is a triangular wave.

4. The method of claim 1, wherein the frequency modulation waveform is a digital signal.

5. The method of claim 1, wherein the clock string is a digital clock string.

6. The method of claim 1, wherein the jittered clock string is a digital clock string.

7. The method of claim 1, wherein the phase value is proportional to a deviation of the frequency modulation waveform from a center of the frequency modulation waveform.

8. The method of claim 1, further comprising multiplying the frequency of the jittered clock train by a multiplier value.

9. The method of claim 8, wherein the average frequency of the spread spectrum clock train is equal to the frequency of the clock train multiplied by the multiplier value divided by the fixed value.

10. The method of claim 1, further comprising:

splitting the phase modulated signal into a first phase modulated signal and a second phase modulated signal;

delaying the second phase modulated signal in time relative to the first phase modulated signal; and thereafter

Calculating a difference between the first phase modulation signal and the second phase modulation signal to generate the phase value.

11. The method of claim 10, further comprising adding the phase value to the fixed value to generate the divider value.

12. A digital circuit configured for spreading a spectrum of a clock string, comprising:

a variable divider configured to digitally modulate widths of clock pulses constituting the clock train to generate a jittered clock train;

a first accumulator configured to accumulate the jittered clock train to generate a frequency modulated waveform;

a second accumulator configured to accumulate the frequency modulation waveform to generate a phase modulation signal;

a phase value calculator configured to generate a divider value that varies in time based on the phase modulation signal, wherein the variable divider is configured to digitally modulate the width based on the divider value that varies in time; and

a closed loop control circuit configured to track and filter the modulation of the jittered clock train to generate a second clock train that is a spectral spread of the first-mentioned clock train.

13. The digital circuit of claim 12, wherein the temporally varying divider value is equal to a fixed divider value plus a phase value.

14. The digital circuit of claim 13, wherein the phase value is determined from the frequency modulation waveform.

15. The digital circuit of claim 13, wherein the phase value calculator is further configured to generate the phase value based on the phase modulation signal.

16. The digital circuit of claim 15, wherein the phase value calculator is further configured to split the phase modulated signal into first and second phase modulated signals, and delay the second phase modulated signal relative to the first phase modulated signal, and then calculate a difference between the first phase modulated signal and the second phase modulated signal to generate the phase value.

17. The digital circuit of claim 16, wherein the phase value calculator is further configured to add the phase value to the fixed divider value.

18. The digital circuit of claim 13, wherein the phase value is proportional to a deviation of the digital frequency modulation waveform from a center of the digital frequency modulation waveform.

19. The digital circuit of claim 18, wherein the frequency modulation waveform is periodic or quasi-periodic.

20. The digital circuit of claim 19, wherein the frequency modulation waveform is a triangular wave.

21. The digital circuit of claim 12, further comprising a clock generator configured to generate the clock string.

22. The digital circuit of claim 12, wherein the first clock string is a digital clock string.

23. The digital circuit of claim 12, wherein the closed-loop control circuit is configured to multiply the frequency of the jittered clock train by a fixed multiplier value.

24. The digital circuit of claim 23, wherein the temporally varying divider value is a fixed divider value plus a phase value, and wherein the average frequency of the second clock train is equal to the frequency of the first clock train multiplied by the fixed multiplier value divided by the fixed divider value.

25. The digital circuit of claim 12, wherein:

the phase value calculator includes first and second circuit paths configured to communicate the phase modulated signal to a first summer,

the second circuit path includes a delay circuit configured to delay in time the phase modulated signal in the second circuit path relative to the phase modulated signal in the first circuit path, and

the first adder is configured to calculate a difference between the phase modulated signals received from the first circuit path and the second circuit path, the difference being the phase value.

26. The digital circuit of claim 25, wherein the phase value calculator further comprises a second adder configured to add the phase value to a fixed divider value to generate the temporally varying divider value and to communicate the temporally varying divider value to the variable divider.

27. The digital circuit of claim 12, wherein the closed-loop control circuit is a phase-locked loop circuit.