HK1107728B

HK1107728B - Protection device for non-common ground buses

Info

Publication number: HK1107728B
Application number: HK07113249.5A
Authority: HK
Inventors: 刘仕强; 肖安全; 栗国星
Original assignee: 凹凸科技国际股份有限公司
Priority date: 2006-02-09
Filing date: 2007-12-04
Publication date: 2011-04-15

Description

Protection device for non-common ground bus

Technical Field

The present invention relates to an electronic system, and more particularly, to a bus protection device in an electronic system.

Background

In today's society, electronic systems are becoming more and more popular as their functions and uses expand. Many electronic systems are powered using battery packs composed of batteries. The battery may be a rechargeable battery such as an alkaline battery widely known as a nickel cadmium battery and a nickel hydrogen battery. Recently, lithium ion batteries have become more popular in some high-end electronic systems due to their high power density and stable storage capability.

In battery pack applications, communication between the battery pack and an external device is accomplished via a bus. The bus is typically a low voltage bus such as I2C, SMBus, or the like. If the battery pack ground is directly connected to the external device ground, the bus is referred to as a common ground bus. In the common ground bus, 2P-channel Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) may be used to control battery charging and discharging.

If the battery pack ground is not directly connected to the external device ground, the bus is referred to as a non-common ground bus. Fig. 1 illustrates a prior art battery pack application 100 using a common ground bus. The battery pack application 100 includes a battery pack 110 and an external device 150. The battery pack 110 is composed of a battery 111, a controller 113, and a plurality of switches. In this embodiment, the switch includes 2N-channel MOSFETs 115 and 117 for controlling the charging and discharging circuit of the battery 111. The external device 150 may be a load or a charger. Battery pack 110 communicates with external device 150 via a low voltage bus. The battery pack 110 and the external device 150 each include an embedded interface unit (not shown) for connecting to a bus. Therefore, this bus may also be referred to as an interface bus.

When either of N-channel MOSFET115 and N-channel MOSFET117 is turned off, the ground of external device 150 will not be the true ground, and battery 111 is true ground. When both N-channel MOSFETs 115 and 117 are off, the ground of external device 150 is also not true. Thus, the ground pole of the external device 150 will be floating. In this case, when the battery voltage V_BATTAnd voltage V of external device 150_LOr V_CHGThere will be an undesirable current flowing through the bus when there is a voltage difference between them. Fig. 2A illustrates an operational mode 200A of the battery pack application 100. In this operating mode, V_BATTHigher than V_LOr V_CHGAn undesirable current will flow from the battery 110 through the external device 150, across the bus to the true ground (i.e., the ground of the battery 111). Fig. 2B illustrates another operating mode 200B of the battery pack application 100. In this operating mode, V_BATTLess than V_LOr V_CHGThere will be an undesirable current flowing from the external device 150 through the battery 111, across the bus, to the ground of the external device 150. The extra current may cause the interface unit to be completely damaged.

To avoid the above problem, we use an isolation technique to separate the connection between the battery pack 110 and the external device 150 through the bus. Fig. 3 is a simplified block diagram of a prior art opto-isolator isolation application 300. In this embodiment, the isolation circuit 310 serves to isolate the bus connected to the battery pack 110 from the bus connected to the external device 150. The isolation circuit 310 may include at least one opto-isolator. Although isolation techniques can be used to protect the non-common ground bus, the addition of opto-isolators causes power loss and increases the cost of the battery pack application.

Therefore, there is a need to provide a device that provides protection for a non-common ground bus embedded in a battery pack while having low power consumption and low cost. The main idea of the invention is to provide such an apparatus and method.

Disclosure of Invention

One embodiment of the invention is a protection device for a non-common ground bus. The non-common ground bus includes a first bus and a second bus. The protection device includes a controller, a level shifter, a first set of switches, and a second set of switches. The controller is connected in parallel with a battery and generates a first control signal and a second control signal. The level shifter is connected to the battery and the controller. The level shifter receives the first control signal and generates a third control signal. The first set of switches is connected to the controller via a first bus and to an external component via a second bus. The first set of switches is controlled by a second control signal from the controller and a third control signal from the level shifter. The second set of switches is connected between the battery ground and the ground of the external component. The second set of switches is controlled by a second control signal from the controller and a third control signal from the level shifter. When an abnormal condition occurs, the first set of switches is partially closed or fully closed to isolate the first bus line from the second bus line.

Another embodiment of the invention is a protection device for a non-common ground bus. The non-common ground bus includes a first bus and a second bus. The protection device includes a controller, a level shifter, a first set of switches, and a second set of switches. The controller is connected in parallel with a battery and generates a charging signal, a discharging signal and a first control signal. The level shifter is connected to the battery and the controller. The level shifter receives the first control signal and generates a second control signal at a node. The first set of switches is connected to the controller via a first bus and to the external component via a second bus. The first set of switches is controlled by a second control signal from the level shifter. The second set of switches is connected between the ground of the battery and the ground of the external component. The second set of switches is controlled by a charge signal and a discharge signal from the controller. When an abnormal condition occurs, the first set of switches is partially closed or fully closed to isolate the first bus line from the second bus line.

Another embodiment of the invention is an apparatus for protecting a non-common ground bus. The non-common ground bus includes a first bus and a second bus. The apparatus includes a controller, a first level shifter, a first switch, a second level shifter, and a second switch. The controller is connected in parallel with one battery. A first level shifter is also connected in parallel with the battery, the first level shifter exchanging information with the controller. A first switch is connected between the positive electrode of the battery and a node. The first switch is controlled by a first level shifter. The second level shifter is connected in parallel with an external component. The second switch is connected between the positive electrode of the battery and the ground of the external component. The second switch is controlled by a second level shifter.

Another embodiment of the invention is an apparatus for protecting a non-common ground bus. The non-common ground bus includes a first bus and a second bus. The apparatus includes a controller, a first level shifter, a first Low Dropout (LDO) circuit, a second level shifter, and a second LDO circuit. The controller is connected in parallel with one battery. A first level shifter is coupled to the battery and the controller. The first LDO circuit is connected in parallel with the battery and generates a first output voltage for powering the first level shifter. The second level shifter is connected in parallel with an external component. The second level shifter communicates with the first level shifter via a first bus and a second bus. The second LDO circuit is connected in parallel with the external component. The second LDO circuit generates a second output voltage for powering the second level shifter.

Another embodiment of the present invention is an electric vehicle. The electric vehicle includes a vehicle body, an electric motor for driving the vehicle body, and a battery device for supplying power to the electric motor. The battery device may protect the non-common ground bus. The non-common ground bus includes a first bus and a second bus. The battery device includes a battery, a controller, a level shifter, a first set of switches, and a second set of switches. The controller is connected in parallel with a battery and generates a first control signal and a second control signal. A level shifter is connected to the battery and the controller. The level shifter receives the first control signal and generates a third control signal. The first set of switches is connected to the controller by a first bus and to the electric motor by a second bus. The first set of switches is controlled by a second control signal from the controller and a third control signal from the level shifter. The second set of switches is connected between the ground of the battery and the ground of the electric motor. The second set of switches is controlled by a second control signal from the controller and a third control signal from the level shifter. When an abnormal condition occurs, the first set of switches is partially closed or fully closed to isolate the first bus line from the second bus line.

Another embodiment of the invention is a method for protecting an interface bus in a battery application. The method includes the steps of detecting states of the battery and the external device, generating a charge control signal and a discharge control signal according to the detection result, translating the charge control signal into a switch control signal, exchanging information between the battery and the external device through an interface bus in charge and discharge modes, controlling to turn off a plurality of charge switches by the switch control signal to isolate the battery from the external device in case of abnormal conditions in the charge mode, and controlling to turn off a plurality of discharge switches by the discharge control signal to isolate the battery from the external device in case of abnormal conditions in the discharge mode.

Drawings

Advantages of the present invention will become apparent from the following detailed description of exemplary embodiments, which is to be read in connection with the accompanying drawings.

FIG. 1 is a simplified block diagram of a prior art battery pack application;

FIG. 2A shows an operation mode (V) of the battery pack of FIG. 1_BATTGreater than V_LOr V_CHG) A simplified schematic of (a);

FIG. 2B shows another operating mode (V) for the battery pack of FIG. 1_BATTLess than V_LOr V_CHG) A simplified schematic of (a);

FIG. 3 is a simplified block diagram of a prior art implementation of isolation using an opto-isolator;

FIG. 4 is a simplified diagram of a battery pack application using 2 control ports to control an analog switch according to the present invention;

FIGS. 5A-D illustrate various modes of operation of the battery pack of FIG. 4;

FIG. 6 is a simplified diagram of a battery pack application using a control port to control an analog switch according to the present invention;

FIG. 7 shows the use of a common V in the present invention_PACKSimplified block diagram of smart battery pack application for + bus;

FIG. 8 shows the use of a common V in the present invention_PACKSimplified block diagram of smart battery pack application for + bus;

fig. 9 is a flowchart illustrating the operation of the battery pack application of fig. 4.

Detailed Description

Fig. 4 is a simplified schematic diagram of a battery pack application 400 using 2 control ports to control analog switches according to the present invention. The battery pack application 400 includes a battery pack 410, a bus protection circuit 440, and an external device 150. The battery pack 410 further includes a battery 111, a controller 113, switches 115 and 117, and a level switching circuit 420. In this embodiment, battery pack 410 includes NMOS transistors 115 and 117, and bus protection circuit 440 includes NMOS transistors 442 and 444. NMOS transistors 442 and 444 are analog switches that control two ports. The above-mentioned NMOS transistors are each provided with an intrinsic diode. The bus 401 is used for communication between the controller 113 and the bus protection circuit 440, and the bus 403 is used for communication between the bus protection circuit 440 and the external device 150. Bus protection circuit 440 may protect buses 401 and 403 when an abnormal condition occurs. In contrast to the battery pack application 100, the battery pack application 400 also includes a level switch circuit 420 that can drive the bus protection circuit 440.

The battery 111 is connected between the PACK + terminal and the GND1 terminal. The GND1 terminal is a true ground pole. The controller 113 is connected in parallel with the battery 111. The controller 113 may receive the voltage at the PACK + terminal, which is a voltage referenced to ground (i.e., a voltage referenced to the ground). The controller 113 may generate a discharge control signal to control the NMOS transistors 115 and 442. The controller 113 may also generate a charge control signal to control the level switch circuit 420 such that the voltage at the PACK + terminal is converted to a control signal on node 421. The control signal on node 421 is used to control NMOS transistors 117 and 444. NMOS transistors 115 and 117 are used to control the charging and discharging of battery 111.

The level switching circuit 420 is connected between the PACK + terminal and the controller 113. Level switch circuit 420 is comprised of resistor 422, PMOS transistor 424, and a voltage divider comprised of resistors 426 and 428. The resistor 422 is connected between the positive electrode of the battery 111 and the controller 113. The PMOS transistor 424 is controlled by the controller 113. Resistor 422 is also coupled between the source terminal and the gain terminal of PMOS transistor 424. Controlled by the charge control signal, level switch circuit 420 may output a control signal at node 421 for controlling NMOS transistors 117 and 444.

The protection circuit 440 is connected to the controller 113 through a bus 401 and to the external device 150 through a bus 403. NMOS transistors 442 and/or 444 may be turned off to isolate buses 401 and 403. NMOS transistor 115 and/or NMOS transistor 117 may also be turned off under isolation conditions. Therefore, buses 401 and 403 are not grounded. In short, the buses 401 and 403 are referred to as non-common ground buses in isolated condition.

Only 2 NMOS transistors 115 and 117 are used in fig. 4 to control the charging and discharging of the battery 111, and those skilled in the art will appreciate that any number of NMOS transistors greater than 2 may be used. Similarly, the protection circuit 440 may be formed of any number of NMOS transistors greater than 2. In addition, when an abnormal condition occurs, at least some of the transistors (switches) in the protection circuit 440 are turned off to block communication between the battery 111 and the external device 150.

Fig. 5 a-D illustrate various modes of operation of the battery pack application 400. The NMOS transistor shown in fig. 4 will be omitted by itself when turned on or off for simplicity. When the transistor is on, only its on-state is shown in fig. 5 a-D. When the NMOS transistor is off, only its intrinsic diode is shown for illustration.

Fig. 5A illustrates a normal operating mode of the battery pack application 400. In normal mode, current flows from PACK + terminal through resistor 422 to controller 113. The charge control signal and the discharge control signal provided by the controller 113 are set to low (logic 0) and high (logic 1), respectively. PMOS transistor 424 is then turned on and the voltage at the PACK + terminal is divided by the voltage divider. The control signal on node 421 is then set to high. Controlled by the control signal, NMOS transistors 117 and 444 turn on. Similarly, NMOS transistors 115 and 442 are also turned on simultaneously. Thus, the ground of the external device 150 is connected to the ground of the battery 111, and the buses 401 and 403 are common ground buses. In the normal mode, when the external device 150 is a load, the battery 111 will supply power to the external device 150, and the controller 113 will monitor the entire discharge process. If the external device 150 is a charger, the battery 111 will be charged and the controller 113 can monitor the entire charging process. In the normal mode, the battery pack 410 may communicate with the external device 150 through the buses 401 and 403.

Fig. 5B illustrates an abnormal operation mode of the battery pack application 400. When the controller 113 detects an abnormal condition, such as excessive current or excessive temperature, in the battery 111 or the external device 150, the controller 113 activates the protection circuit 440. No current will flow through resistor 422 after protection circuit 440 is activated. PMOS transistor 424 will be off and the voltage at node 421 will be set low. NMOS transistors 117 and 444 are turned off. Since the discharge control signal provided by the controller 113 is also set low, the NMOS transistors 115 and 442 are also turned off synchronously. In this abnormal case, the two intrinsic diodes connected to NMOS transistors 115 and 117 are connected back-to-back. Similarly, the two intrinsic diodes connected to NMOS transistors 442 and 444 are also connected back-to-back. Since the NMOS transistors 115 and 117 are turned off, the ground of the external device 150 is not connected to the ground of the battery 111. Thus, buses 401 and 403 are non-common ground buses and isolated from each other. In this abnormal case bus protection is achieved.

Fig. 5C shows the charging mode of the battery pack application 400, and the external device 150 is a charger. In the charging mode, the charging voltage provided by the charger 150 may be too high, thereby causing an overvoltage. The controller 113 may detect this. The charge control signal provided by the controller 113 will be set high and no current will flow through the resistor 422. Thus, the voltage on node 421 is low and NMOS transistors 117 and 444 are turned off. The ground of the charger 150 is then not connected to the ground of the battery 111 and the buses 401 and 403 are isolated from each other, thereby avoiding bus damage due to over-voltage.

Fig. 5D shows the discharge mode of the battery pack application 400, with the external device 150 being a load. In the discharging mode, the load 150 may be short-circuited, or the battery may not output a sufficient voltage to the load 150. The above situation can be detected by the controller 113 in real time. Upon detection of this, the discharge control signal will be set low and NMOS transistors 115 and 442 will be turned off synchronously. Thus, the ground of load 150 is not connected to the ground of battery 111, and buses 401 and 403 are non-common ground buses. Since NMOS transistor 442 is turned off, buses 401 and 403 are isolated from each other, and communication between battery 111 and load 150 is blocked. Bus protection is achieved in the discharging mode.

Fig. 6 is a simplified schematic diagram of a battery pack application 600 that uses one control port to control an analog switch. The reference numerals in fig. 6 are similar to those in fig. 4, and similar functions of the same external device are omitted for simplicity. Only the differences and improvements of fig. 6 and fig. 4 are described below.

In fig. 6, the battery pack application 600 includes a battery pack 610, a bus protection circuit 640, and an external device 150. The battery pack 610 includes a level switching circuit 620. The level switch circuit 620 is formed by a PMOS transistor 622, a resistor 624, a resistor 626 in series with a diode 627, and a resistor 628 in series with a diode 629. The cathode of the diode 629 is connected to the ground of the battery 111 to prevent leakage current. The cathode of diode 627 is connected to the ground of external device 150 to prevent another leakage current. The level switching circuit 620 may control a bus protection circuit 640 composed of NMOS transistors 442 and 444. NMOS transistors 442 and 444 are analog switches using one control port, node 621 shown in the figure.

When the battery pack 610 operates, the controller 113 may detect the states of the battery 111 and the external device 150. The controller 113 may generate a control signal to control the PMOS transistor 622, a charge control signal to control the NMOS transistor 117, and a discharge control signal to control the NMOS transistor 115. When an abnormal condition occurs, the control signal generated by the controller 113 will be set high, and the PMOS transistor 622 will turn off. So no current flows through resistor 624. The voltage at node 621 will be low. NMOS transistors 442 and 444 are turned off synchronously. If the battery pack application 600 is in the charging process, the charge signal will be set low when the above-described abnormal condition occurs. The NMOS transistor 117 will be off and the ground of the external device 150 is not connected to the ground of the battery 111. Similarly, if an abnormal condition occurs during the discharge, the NMOS transistor 115 will be turned off and the ground of the external device 150 is not connected to the ground of the battery 111. Thus, both buses 401 and 403 are non-common ground buses, whether during charging or discharging. Isolation of buses 401 and 403 may block communication between battery 111 and external device 150. Therefore, bus protection may also be achieved using the isolation techniques described above.

When the external device 150 is a charger, the charger charges the battery 111, and a current will flow through the battery 111 to the ground of the battery 111. Diode 629 prevents the current from flowing through resistor 628 back to node 621. In contrast, when the external device 150 is a load, the battery 111 powers the load, and current will flow through the load 150 to the ground of the load 150. Diode 627 prevents this current from flowing through resistor 626 back to node 621.

Similar to the battery pack application 400 of fig. 4, the battery pack application 600 may use any number (2 or more) of NMOS transistors to control the charging and/or discharging process, and may also use any number (2 or more) of NMOS transistors to configure the bus protection circuit 640. Also, the controller 113 in fig. 4 and 6 may be formed of any analog circuit, digital circuit, integrated circuit, or a combination of the above 3 to implement the above functions.

FIG. 7 shows the use of a common V_PACKA simplified block diagram of a + pole battery pack application 700. The battery pack application 700 generally includes a battery pack 710, a resistor 740, and a component 750. Buses 701 and 703 are used for communication between battery pack 710 and component 750. The battery pack 710 includes a battery 111, a controller 113, a level switching circuit 720, and a PMOS transistor 730. The level switching circuit 720 includes buffers 722 and 724. The controller 113 exchanges information with the level switching circuit 720 through a bus. The component 750 includes an external device 150, a PMOS transistor 760 and a level switching circuit 770. The level switching circuit 770 includes buffers 772 and 774. The external device 150 exchanges information with the level switch circuit 770 through a bus.

When the external device 150 is a charger, the controller 113 may detect the amount of power of the battery 111. During charging, the controller 113 may send information reflecting the state of the battery 111 to the level switching circuit 720 through a bus. Buffer 722 receives the information and generates a logic 0 voltage. PMOS transistor 730 turns on and current flows through resistor 740 to the ground of charger 150. A voltage will then be generated on node 702 that drives buffer 772. The buffer 772 may also transmit information contained in the above-described voltage to the charger 150.

In contrast, information reflecting the state of the charger 150 may be sent to the buffer 774, and the buffer 774 may generate a logic 0 voltage to drive the PMOS transistor 760. Current will flow through resistor 740 and a voltage is generated on node 702. The buffer 724 may send information contained in the voltage back to the controller 113. Thus, battery 111 may communicate with charger 150 via buses 701 and 703.

When the external device 150 is a load, the controller 113 may detect the state of the load 150, such as detecting whether it is short-circuited. Since the communication during the discharging process is similar to that during the charging process, the table is omitted.

As shown in FIG. 7, buses 701 and 703 are non-common ground buses and are common V_PACK+ bus. Because the buses 701 and 703 are not much different from the PACK + side, the low power buses 701 and 703 are protected and the buses 701 and 703 are not damaged even if the battery PACK application 700 uses higher power.

FIG. 8 shows the use of a common V_PACKA simplified block diagram of a smart battery pack application 800 for the + bus. The battery pack application 800 generally includes a battery pack 810 and an assembly 850. Buses 801 and 803 are used for communication between battery pack 810 and assembly 850. The battery pack 810 includes a battery 111, a controller 113, an LDO circuit 820, and a level shifter 830. Component 850 includes external device 150, LDO circuit 860, and level shifter 870. The controller 113 may detect the state of the battery 111 and transmit information reflecting the battery state to the level shifter 830 through a bus. The LDO circuit 820 is powered by the voltage at the PACK + terminal, which is the voltage referenced to true ground, and the LDO circuit 820 outputs a constant voltage to the level shifter 830. Thus, the difference between the voltage at the PACK + terminal and the output voltage of LDO circuit 820 is a relatively fixed value. Level shifter 830 may convert the information into a voltage that is sent over buses 801 and 803 to level shifter 870. Level shifter 870 is powered by the voltage at the PACK + terminal, level shiftingThe device 870 may send the voltage to the external device 150 via a bus. In the opposite direction, information reflecting the status of external device 150 may be sent back to battery 111. Communication between the battery 111 and the external device 150 is then established.

In FIG. 8, buses 801 and 803 are non-common ground buses, but are common V_PACK+ bus. Due to V_PACKThe voltage at + is not much different from the voltage on buses 801 and 803, and low power buses 801 and 803 are protected from bus damage even when higher power is used by battery pack application 800, such as 50 volts for charger 150.

Embodiments 700 and 800 are intended to be illustrative and exemplary and that modifications and variations are possible without departing from the spirit of the invention. In addition, some of the peripheral components are not shown in FIGS. 7 and 8 for simplicity. Those skilled in the art will appreciate that the addition of such peripheral components does not depart from the scope of the invention.

The protection techniques described above may be used in high power electrical systems. Such high power electrical systems may include, for example, electric bicycles, electric motorcycles, and other electric vehicles. An electric vehicle typically includes a body equipped with a motion mechanism, including an electric motor and a battery device. The electric motor is used to drive the vehicle body. The battery device powers the electric motor, and the bus in the battery device may be protected using any of the configurations and techniques mentioned above. For the sake of simplicity, the specific operation of the electric vehicle will not be described herein.

Fig. 9 is a flowchart illustrating the operation of the battery pack application 400. In step 910, the controller 113 may detect the states of the battery 111 and the external device 150. In step 920, the controller 113 generates a charging control signal and a discharging control signal according to the detection result in step 910. In step 930, the level shifter 420 translates the charge control signal into a switch control signal. In step 940, the battery and the external device exchange information over buses 401 and 403 in charge and discharge mode. In step 950, when an abnormal condition occurs during the charging mode, the switch control signal controls the charging switches 117 and 444 to be turned off, thereby isolating the external device 150 from the battery 111. In step 960, when an abnormal condition occurs in the discharging mode, the discharging control signal controls the discharging switches 115 and 442 to be turned off, isolating the external device 150 from the battery 111.

In operation, the battery 111 may communicate with a load or charger 150 in a normal mode. In this mode, the controller 113 may set the discharge control signal high and the charge control signal low. When the PMOS transistor 424 is turned on, the level shifter 420 may output a logic 1 at the node 421. All NMOS transistors will be turned on. In this mode, since all NMOS transistors in the protection circuit 440 are off, the battery pack 410 may communicate with the load or charger 150 via buses 401 and 403, the buses 401 and 403 being common ground buses.

The level shifter 420 may activate the protection circuit 440 to protect the buses 401 and 403 if an abnormality occurs in the battery 111 and/or the load 150. In the abnormal mode, the controller 113 may set the charge control signal to high and the discharge control signal to low. In this way, the charge control signal (high) and the discharge control signal (low) may cause all NMOS transistors to turn off. In abnormal mode, the ground of load 150 is not connected to the ground of the battery and buses 401 and 403 are non-common ground buses. In abnormal mode, the NMOS transistors in the protection circuit 440 will both be off, isolating the buses 401 and 403. Thus, buses 401 and 403 are protected in the abnormal case.

If the external device 150 is a charger, the battery 111 will operate in a charging mode. When an abnormal condition occurs during charging, the controller 113 will turn off the associated NMOS transistor and the charging stops. NMOS transistors 117 and 444 are turned off during charging. Buses 401 and 403 are then non-common ground buses, which are protected because controller 113 and charger 150 are isolated.

If the external device 150 is a load, the battery 111 will operate in a discharge mode. If an abnormality occurs during the discharge process, the controller 113 will turn off the associated NMOS transistor and the discharge process stops. NMOS transistors 115 and 442 are turned off during the discharge. Buses 401 and 403 are then non-common ground buses, which are protected due to the isolation of controller 113 from load 150.

The embodiments described herein are merely selected from a few examples of how the invention may be implemented and are intended to be illustrative and not limiting. It will be apparent to those skilled in the art that many other embodiments are possible without departing substantially from the spirit and scope of the invention as defined in the following claims. Furthermore, elements described and claimed herein may be singular, and plural forms thereof are contemplated as being claimed unless limitation to the singular is explicitly stated.

Claims

1. An apparatus for protecting a non-common ground bus, the non-common ground bus including a first bus and a second bus, the apparatus comprising:

a controller connected in parallel with the battery, the controller generating a first control signal and a second control signal;

a level shifter coupled to the battery and the controller, the level shifter receiving the first control signal and generating a third control signal;

a first group of switches connected to the controller through a first bus and connected to the external component through a second bus, the first group of switches being controlled by a second control signal from the controller and a third control signal from the level shifter;

a second group of switches connected between a ground of the battery and a ground of the external component, the second group of switches being controlled by a second control signal from the controller and a third control signal from the level shifter;

when an abnormal condition occurs, the first set of switches is partially or fully closed to isolate the first bus line from the second bus line.

2. The protection device of claim 1, wherein the level shifter further comprises:

a transistor having a gate, a source and a drain, the source being connected to the positive terminal of the battery;

a resistor connected between the gate and the source of the transistor;

a voltage divider is connected between the drain of the transistor and ground of the external component, the divider having a node and generating the control signal at the node.

3. A protection device for a non-common ground bus, the non-common ground bus including a first bus and a second bus, the protection device comprising:

a controller connected in parallel with the battery, the controller generating a charging signal, a discharging signal and a first control signal;

a level shifter coupled to the battery and the controller, the level shifter receiving the first control signal and generating a second control signal at a node;

a first group of switches connected to the controller through a first bus and connected to the external component through a second bus, the first group of switches being controlled by a second control signal generated by the level shifter;

a second set of switches connected between a ground of the battery and a ground of the external component, the second set of switches being controlled by the charging signal and the discharging signal generated by the controller;

4. The protection device of claim 3, wherein the level shifter comprises:

a first diode having an anode and a cathode, the cathode being connected to the ground of the external component;

a first resistor connected between the anode of the first diode and the node;

a second diode having an anode and a cathode, the cathode being connected to the ground of the battery;

a second resistor connected between the anode of the second diode and the node;

a third resistor connected to the node;

a transistor having a gate for receiving a first control signal from the controller, a source connected to the positive terminal of the battery, and a drain connected to the third resistor.

5. An apparatus for protecting a non-common ground bus, the non-common ground bus including a first bus and a second bus, the apparatus comprising:

a controller connected in parallel with the battery;

a first level shifter connected in parallel with the battery, the first level shifter exchanging information with the controller;

a first switch connected to the positive pole of the battery, the switch being controlled by the first level shifter;

a second level shifter connected in parallel with the external component, the second level shifter exchanging information with the external component through an additional bus;

a second switch connected to the positive pole of the battery, the switch being controlled by the second level shifter,

wherein one of the first bus and the second bus is connected to the positive electrode of the battery through a first switch, the other of the first bus and the second bus is connected to the positive electrode of the battery through a second switch, and the first switch is connected to the second switch through the first bus and the second bus.

6. The apparatus of claim 5, wherein the first and second level shifters each comprise a plurality of buffers.

7. The apparatus of claim 5, wherein the first level shifter communicates with the second level shifter via the first bus and the second bus when one of the first switch and the second switch is open.

8. An apparatus for protecting a non-common ground bus, the non-common ground bus including a first bus and a second bus, the apparatus comprising:

a controller connected in parallel with the battery;

a first level shifter connected to the battery and the controller;

a first Low Dropout (LDO) circuit connected in parallel with the battery, the circuit generating a first output voltage to power the first level shifter;

a second level shifter connected in parallel with the external device, the second level shifter exchanging information with the first level shifter through the first bus and the second bus, the second level shifter communicating with the external device through an additional bus;

a second LDO circuit connected in parallel with the external device, the second LDO circuit generating a second output voltage for powering the second level shifter.

9. The apparatus of claim 8, wherein the first and second level shifters each comprise a plurality of buffers.

10. An electric vehicle, comprising:

a vehicle body;

an electric motor for driving the vehicle body;

a battery device for powering an electric motor, the battery device operable to protect a non-common ground bus in an abnormal situation, the non-common ground bus including a first bus and a second bus, the battery device comprising:

a battery;

a first set of switches connected to the controller through a first bus and to the electric motor through a second bus, the first set of switches being controlled by a second control signal from the controller and a third control signal from the level shifter;

a second group of switches connected between a ground of the battery and a ground of the electric motor, the second group of switches being controlled by a second control signal from the controller and a third control signal from the level shifter;

11. The electric vehicle of claim 10, wherein the level shifter comprises:

a resistor connected between the gate and the source of the transistor;

a voltage divider is connected between the drain of the transistor and the ground of the electric motor, the voltage divider having a node and generating a control signal at the node.

12. A method for protecting an interface bus in a battery application system, comprising the steps of:

detecting states of the battery and the external device;

generating a charge control signal and a discharge control signal in the controller according to the result of the detection;

translating the charge control signal into a switch control signal;

exchanging information between the battery and the external device through the interface bus in the charging and discharging modes;

when abnormality occurs in the charging mode, the plurality of charging switches are controlled to be closed by the switch control signal so as to isolate the external equipment from the battery;

and when the abnormality occurs in the discharging mode, the plurality of discharging switches are controlled to be closed by the discharging control signal to isolate the external device from the battery.