HK1109514A - Pipelined analog-to-digital converters - Google Patents

Description

Pipeline analog-to-digital converter

Technical Field

The present invention relates to pipelined analog-to-digital converters (pipelined ADCs).

Background

Reducing power consumption of electronic devices has become increasingly important, especially for battery powered devicesDevices such as laptop computers, personal digital assistants, cellular telephones, MP3 players, and other devices. Analog-to-digital converters (ADCs) are commonly used in these electronic devices to convert analog signals to digital signals. The ADC may comprise a pipelined ADC utilizing a plurality of stages. Each stage uses a sample-and-hold circuit for the analog input voltage V of the pipeline ADC_inOr residual voltage V from a previous stage_resSampling is performed. In addition, each stage receives a reference voltage V_ref。

Referring now to fig. 1, a typical pipelined ADC 10 is shown. The ADC 10 includes a plurality of stages 12-1, 12-2 and 12-3 (collectively referred to as stages 12) cascaded in series. Although three stages 12-1, 12-2, and 12-3 are shown, pipelined ADC 10 may include more or fewer stages. Some of the a/D converter stages 12 include a sample and hold module 14 that couples an analog input signal V_inOr residual signal V from a previous stage_resSampling and holding are performed. The low resolution A/D sub-converter module 16 quantizes the held analog signal to B_iThe resolution of the bits, where i corresponds to the current stage of the pipeline a/D converter 10. Number of bits B per stage_iAnd/or the number of stages may be determined to some extent by the required sampling rate and resolution. The output of the a/D sub-converter module 16 is provided to a low resolution D/a sub-converter module 18, which D/a sub-converter module 18 converts the resulting digital output signal back to analog form.

The D/a sub-converter modules 18 may have the same resolution as the corresponding a/D sub-converter modules 16 in the same stage. The difference module 20 inputs V from a voltage_inSubtracts the analog output from the D/A sub-converter module 18 to produce a residual signal V_res. Residual signal V_resEqual to the held analog signal (V)_inOr V from a preceding stage_res) And the difference between the reconstructed analog signal.

The analog interstage difference module 22 may be used to amplify the residual signal. The amplified residue signal is output to the next stage 12-2 of the pipelined ADC 10. The first ADC stage 12-1 of the pipelined ADC 10 operates on the most current analog input sample, while the second ADC stage 12-2 operates on the amplified residue of the previous input sample. The third ADC stage 12-3 operates on the amplified residue output by the second ADC stage 12-2.

The simultaneity of operation allows the switching speed to be determined by the time used in one stage. Once the current stage has completed operating on the analog input sample received from the previous stage, the current stage is available to operate on the next sample.

Disclosure of Invention

The pipelined analog-to-digital converter includes a first ADC stage that receives a first voltage reference and one of an input voltage and a first residual voltage, and generates a first digital signal and a second residual voltage. The second ADC stage receives the second residual voltage and the second voltage reference from the first ADC stage and generates a second digital signal. The second voltage reference is lower than the first voltage reference.

A system includes a pipeline analog-to-digital converter and further includes a first voltage source that provides a first voltage reference. The second voltage source provides a second voltage reference. The analog circuit receives a first voltage reference. The digital circuit receives a second voltage reference.

An integrated circuit includes a pipelined analog-to-digital converter and further includes a first voltage source that provides a first voltage reference. The second voltage source provides a second voltage reference. The analog circuit receives a first voltage reference. The digital circuit receives a second voltage reference.

In other features, the first ADC stage further comprises a sample-and-hold module that samples and holds one of the input voltage and the first residual voltage. The analog-to-digital converter converts the output of the sample-and-hold module into a digital signal. The digital-to-analog converter converts the digital signal into an analog signal. The first ADC stage further comprises a difference module that generates a difference signal between the output of the sample-and-hold circuit and the analog signal. The amplifier module amplifies the difference signal.

An integrated circuit includes a pipelined analog-to-digital converter and further includes an analog voltage source that generates a first voltage reference. The first voltage reference is an analog voltage reference. The digital voltage source generates a second voltage reference. The second voltage reference is a digital voltage reference.

A system includes a pipeline analog-to-digital converter and further includes an analog voltage source that generates a first voltage reference. The first voltage reference is an analog voltage reference. The digital voltage source generates a second voltage reference. The second voltage reference is a digital voltage reference.

Other suitable aspects of the present disclosure will be apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the disclosure, are intended for purposes of illustration only and are not intended to limit the scope of the disclosure.

Drawings

The present disclosure will become more fully understood from the detailed description and the accompanying drawings, wherein:

FIG. 1 is a functional block diagram of a pipelined analog-to-digital converter (ADC) according to the prior art;

FIG. 2 is a functional block diagram of an exemplary pipelined ADC according to the present invention;

FIG. 3 is a functional block diagram of another exemplary pipelined ADC according to the present invention;

FIG. 4 is a functional block diagram of an integrated circuit including a pipelined ADC according to the present invention;

FIG. 5 is a functional block diagram of an integrated circuit including an analog voltage source, a digital voltage source, and a pipelined ADC according to the present invention;

FIG. 6A is a functional block diagram of a hard disk drive;

FIG. 6B is a functional block diagram of a Digital Versatile Disc (DVD);

FIG. 6C is a functional block diagram of a high definition television;

FIG. 6D is a functional block diagram of a vehicle control system;

FIG. 6E is a functional block diagram of a cellular telephone;

FIG. 6F is a functional block diagram of a set-top box; and

fig. 6G is a functional block diagram of a media player.

Detailed Description

The following description is merely exemplary in nature and is in no way intended to limit the disclosure, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. As used herein, the term module, circuit and/or device refers to an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and memory that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality. As used herein, at least one of the phrases A, B and C should be interpreted to mean logical (a or B or C), using a non-exclusive logical or. It should be understood that the steps of the method may be performed in a different order without altering the principles of the present disclosure.

Referring now to FIG. 2, there is shown a circuit comprising a plurality of voltage references V_{ref_i}Where i corresponds to the current stage of the pipelined ADC 100 according to the invention. ADC 10 includes stages 112-1, 112-2, and 112-3 (collectively referred to as stages 112), a sample-and-hold module 114, an ADC module 116, a digital-to-analog converter (DAC) module 118, a difference module 120, and an amplifier module 122. Although three stages are shown, more or fewer stages may be used. In FIG. 2, V_{ref_1}≥V_{ref_2}And V_{ref_1}＞V_{ref_3}. Pipeline ADC 100 postThe quantization of the bits of the level of the facet does not require the same signal-to-noise ratio (SNR) as the current level, so a lower reference voltage can be used for at least one of the second and third levels.

The power consumed by the stages 112-1, 112-2, and 112-3 of the pipelined ADC 100 is related to the voltage reference of each stage. Thus, pipelined ADC 100 tends to consume less power than a pipelined ADC having multiple stages provided with the same voltage reference as shown in fig. 1.

Referring now to FIG. 3, it shows the inclusion of different voltage references V_{ref_i}Where i corresponds to the current stage of the pipelined ADC 120. Voltage reference V_{ref_i}Is taken from the analog supply voltage V of the analog circuit in the system comprising the ADC 120_{analog_ref}And at least one of the voltage references is taken from the digital supply voltage V of the digital circuit in the system comprising the ADC 120_{digital_ref}。

Referring now to fig. 4, an Integrated Circuit (IC)200 is shown. One or more power supplies 202 provide unregulated voltage to voltage regulators (voltage regulators) 204 and 206. The first voltage regulator 204 provides an analog power supply voltage V_{analog_ref1}、V_{analog_ref2}A_{analog_ref_X}Wherein X is an integer greater than 0. The second voltage regulator 206 provides a digital power supply voltage V_{digital_ref1}、V_{digital_ref2}A_{digital_ref_Y}Wherein Y is an integer greater than 0. IC 200 may also include IC components 210 to perform additional circuit functions. The first voltage regulator 204 also provides power to one or more analog circuits 216 in the IC 200. The second voltage regulator 206 also supplies one or more digital circuits 214.

Referring now to fig. 5, an Integrated Circuit (IC)220 is shown. The analog voltage source 224 generates an analog supply voltage V_{analog_ref1}、V_{analog_ref2}A_{analog_ref_X}Wherein X is an integer greater than 0. The digital voltage source 226 generates a digital supply voltage V_{digital_ref1}、V_{digital_ref2}A_{digital_ref_Y}Which isWherein Y is an integer greater than 0. IC 220 may also include IC components 210 to perform additional circuit functions. The analog voltage source 224 also powers one or more analog circuits 216 in the IC 200. The digital voltage source 226 also powers one or more digital circuits 214.

Referring now to fig. 6A through 6G, various exemplary implementations of the device are shown. Referring now to fig. 6A, the device may be implemented in one of a plurality of ADCs in hard disk drive 400. The device may be implemented and/or embodied in signal processing and/or control circuitry (generally identified as 402 in fig. 6A) and/or a power supply 403. In some implementations, signal processing and/or control circuit 402 and/or other circuits (not shown) in HDD 400 may process data, perform coding and/or encryption, perform calculations, and/or format data that is output to and/or received from magnetic storage media 406.

HDD 400 may communicate with a host device (not shown) such as a computer, a mobile computing device such as a personal digital assistant, cellular telephone, media or MP3 player, and/or other devices via one or more wired or wireless communication links 408. HDD 400 may be connected to memory 409, such as Random Access Memory (RAM), short latency nonvolatile memory such as flash memory, Read Only Memory (ROM), and/or other suitable electronic data storage.

Referring now to fig. 6B, the device may be implemented in one of a plurality of ADCs in a Digital Versatile Disc (DVD) drive 410. The device may be implemented and/or realized in signal processing and/or control circuitry (generally designated 412 in fig. 6B), mass data storage devices, and/or power supply 413 of DVD drive 410. Signal processing and/or control circuits 412 and/or other circuits (not shown) in DVD410 may process data, perform coding and/or encryption, perform calculations, and/or format data read from and/or written to optical storage medium 416. In some implementations, the signal processing and/or control circuits 412 and/or other circuits (not shown) in the DVD410 can also perform other functions such as encoding and/or decoding and/or any other signal processing functions associated with a DVD drive.

DVD drive 410 may communicate with an output device (not shown), such as a computer, television, or other device, via one or more wired or wireless communication links 417. The DVD410 may communicate with a mass data storage 418 that stores data in a nonvolatile manner. The mass data storage 418 may include a Hard Disk Drive (HDD). The HDD may have the configuration shown in fig. 6A. The HDD may be a mini HDD that includes one or more platters that are less than about 1.8 "in diameter. The DVD410 may be connected to memory 419 such as RAM, ROM, a relatively short latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage.

Referring now to fig. 6C, the apparatus may be implemented in one of a plurality of ADCs in a High Definition Television (HDTV) 420. The device may be implemented and/or realized in signal processing and/or control circuitry (generally identified in fig. 6C as 422), a WLAN interface, a mass data storage device, and/or a power supply 423 of the HDTV 420. The HDTV420 receives HDTV input signals in either wired or wireless form and generates HDTV output signals for a display 426. In some implementations, signal processing and/or control circuit 422 and/or other circuits (not shown) in HDTV420 may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other type of HDTV processing that may be required.

The HDTV420 may communicate with mass data storage 427 that stores data in a nonvolatile manner such as optical and/or magnetic storage devices. At least one HDD may have the configuration shown in fig. 6A and/or at least one DVD may have the configuration shown in fig. 6B. The HDD may be a mini HDD that includes one or more platters that are less than about 1.8 "in diameter. HDTV420 may be connected to memory 428 such as RAM, ROM, short latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. HDTV420 may also support connections with a WLAN through a WLAN network interface 429.

Referring now to fig. 6D, the device may be implemented and/or realized in one of a plurality of ADCs in the control system, WLAN interface, mass data storage device of the vehicle control system, and/or power supply 433 of the vehicle 430. In certain implementations, the apparatus implements a transmission control system 432 that receives input from one or more sensors, such as a temperature sensor, a pressure sensor, a rotation sensor, an air flow sensor, and/or any other suitable sensor, and/or generates one or more output control signals, such as engine operating parameters, transmission operating parameters, and/or other control signals.

The apparatus may also be implemented in other control systems 440 of the vehicle 430. The control system 440 may likewise receive signals from input sensors 442 and/or output control signals to one or more output devices 444. In some implementations, the control system 440 may be part of an anti-lock braking system (ABS), a navigation system, a telematics system, a vehicle telematics system, a lane departure system, an adaptive cruise control system, a vehicle entertainment system such as a stereo, DVD, compact disc, etc. Other implementations may also be included.

The transmission control system 432 may communicate with mass data storage 446 that stores data in a nonvolatile manner. The mass data storage 446 may include optical and/or magnetic storage devices, such as hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown in fig. 6A and/or at least one DVD may have the configuration shown in fig. 6B. The HDD may be a mini HDD that includes one or more platters that are less than about 1.8 "in diameter. The transmission control system 432 may be connected to memory 447 such as RAM, ROM, a relatively short latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage. The transmission control system 432 may also support connections with a WLAN through a WLAN network interface 448. The control system 440 may also include a mass data storage device, memory, and/or a WLAN interface (all not shown).

Referring now to fig. 6E, the device may be implemented in one of a plurality of ADCs in a cellular phone 450, which may include a cellular antenna 451. The device may be implemented and/or embodied in signal processing and/or control circuitry (generally identified in fig. 6E as 452), a WLAN interface, a mass data storage device, and/or a power supply 453 of the cellular telephone 450. In some implementations, the cellular phone 450 includes a microphone 456, an audio output 458 such as a speaker and/or audio output jack, a display 460, and/or an input device 462 such as a keyboard, pointing device, voice actuation (voiceaction), and/or other input device. Signal processing and/or control circuits 452 and/or other circuits (not shown) in cellular telephone 450 may process data, perform coding and/or encryption, perform calculations, format data and/or perform other cellular telephone functions.

The cellular phone 450 may communicate with mass data storage 464 that stores data in a nonvolatile manner, such as optical and/or magnetic storage devices, such as hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown in fig. 6A and/or at least one DVD may have the configuration shown in fig. 6B. The HDD may be a mini HDD that includes one or more platters that are less than about 1.8 "in diameter. The cellular phone 450 may be connected to memory 466 such as RAM, ROM, short latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. The cellular phone 450 may also support connections with a WLAN through a WLAN network interface 468.

Referring now to fig. 6F, the device may be implemented in one of a plurality of ADCs in set top box 480. The device may be implemented and/or embodied in the signal processing and/or control circuits (generally labeled 484 in fig. 6F), WLAN interface, mass data storage device, and/or power supply 483 of the set top box 480. The set top box 480 receives signals from a signal source, such as a broadband signal source, and outputs standard and/or high definition audio/video signals suitable for a display 488, such as a television and/or monitor and/or other video and/or audio output device. Signal processing and/or control circuits 484 and/or other circuits (not shown) in the set top box 480 may process data, perform coding and/or encryption, perform calculations, format data and/or perform other set top box functions.

The set top box 480 may communicate with mass data storage 490 that stores data in a nonvolatile manner. The mass data storage device 490 may include optical and/or magnetic storage devices, such as hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown in fig. 6A and/or at least one DVD may have the configuration shown in fig. 6B. The HDD may be a mini HDD that includes one or more platters that are less than about 1.8 "in diameter. The set top box 480 may be connected to memory 494 such as RAM, ROM, short latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. The set top box 480 may also support connections with a WLAN through a WLAN network interface 496.

Referring now to fig. 6G, the device may be implemented in one of a plurality of ADCs in the media player 500. The device may be implemented and/or embodied in signal processing and/or control circuitry (generally identified in fig. 6G as 504), a WLAN interface, a mass data storage device, and/or a power supply 503 of the media player 500. In some implementations, the media player 500 includes a display 507 and/or a user input 508 such as a keyboard, touchpad, and the like. In some implementations, media player 500 may use a Graphical User Interface (GUI) that typically uses menus, drop down menus, buttons, and/or a point-and-click interface via display 507 and/or user input 508. The media player 500 also includes an audio output 509 such as a speaker and/or audio output jack. Signal processing and/or control circuits 504 and/or other circuits (not shown) in media player 500 may process data, perform coding and/or encryption, perform calculations, format data and/or perform other media player functions.

The media player 500 may communicate with mass data storage 510 that stores data, such as compressed audio and/or video content, in a nonvolatile manner. In some implementations, the compressed audio files include files that conform to the MP3 format or other suitable compressed audio and/or video format. The mass data storage device may comprise an optical and/or magnetic storage device, such as a hard disk drive HDD and/or a DVD. At least one HDD may have the configuration shown in fig. 6A and/or at least one DVD may have the configuration shown in fig. 6B. The HDD may be a mini HDD that includes one or more platters that are less than about 1.8 "in diameter. The media player 500 may be connected to memory 514 such as RAM, ROM, short latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage. The media player 500 may also support connections with a WLAN through a WLAN network interface 516. Other implementations are possible in addition to the above.

Those skilled in the art can now appreciate from the foregoing description that the teachings of the present disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification, and the following claims.

Claims (10)

1. A pipelined analog-to-digital converter comprising:

a first analog-to-digital converter stage receiving one of an input voltage and a first residual voltage and a first voltage reference and generating a first digital signal and a second residual voltage; and

a second analog-to-digital converter stage that receives the second residual voltage from the first analog-to-digital converter stage and a second voltage reference, and generates a second digital signal, wherein the second voltage reference is lower than the first voltage reference.

2. A system comprising the pipelined analog-to-digital converter of claim 1, the system further comprising:

a first voltage source providing the first voltage reference; and

a second voltage source that provides the second voltage reference.

3. The system of claim 2, further comprising:

an analog circuit that receives the first voltage reference; and

a digital circuit that receives the second voltage reference.

4. An integrated circuit comprising the pipelined analog-to-digital converter of claim 1, the integrated circuit further comprising:

a first voltage source providing the first voltage reference; and

a second voltage source that provides the second voltage reference.

5. The integrated circuit of claim 4, further comprising:

an analog circuit that receives the first voltage reference; and

a digital circuit that receives the second voltage reference.

6. The pipelined analog-to-digital converter of claim 1, wherein the first analog-to-digital converter stage further comprises:

a sample-and-hold module that samples and holds the one of the input voltage and the first residual voltage;

an analog-to-digital converter that converts the output of the sample-and-hold module to a digital signal; and

a digital-to-analog converter that converts the digital signal to an analog signal.

7. The pipeline analog-to-digital converter of claim 6, wherein the first analog-to-digital converter stage further comprises:

a difference module that generates a difference signal between the output of the sample and hold module and the analog signal; and

an amplifier module that amplifies the difference signal.

8. An integrated circuit comprising the pipelined analog-to-digital converter of claim 1, the integrated circuit further comprising:

an analog voltage source that generates the first voltage reference, wherein the first voltage reference is an analog voltage reference; and

a digital voltage source that generates the second voltage reference, wherein the second voltage reference is a digital voltage reference.

9. A system comprising the pipelined analog-to-digital converter of claim 1, the system further comprising an analog voltage source that generates the first voltage reference, wherein the first voltage reference is an analog voltage reference.

10. A system comprising the pipelined analog-to-digital converter of claim 1, the system further comprising a digital voltage source that generates the second voltage reference, wherein the second voltage reference is a digital voltage reference.