HK1120674B - Method and system for signal processing - Google Patents

Description

Method and system for processing signal

Technical Field

The present invention relates to rake receivers, and more particularly, to a method and system for a delay locked loop of a rake receiver.

Background

Mobile communications have changed the way people communicate, and mobile phones have also changed from a luxury item to an integral part of people's daily lives. Although voice communication can satisfy the basic requirements of people for communication and mobile voice communication has further penetrated people's daily lives, the next stage of mobile communication development is the mobile internet. The mobile internet will become a common source of everyday information and, of course, a universal mobile access to such data should be achieved.

Third generation (3G) cellular networks are specifically designed to meet these future demands of the mobile internet. With the proliferation and use of these services, cost-effective optimization of network capacity and quality of service (QoS), among other factors, becomes more important to cellular network operators than today. Of course, these factors can be achieved through careful network planning and operation, improvements in transmission methods, and improvements in receiver technology. Therefore, operators need new techniques to increase the downlink throughput to provide better QoS capacity and rate than those of cable modem and/or DSL service providers. In this regard, it is a more viable option for today's wireless carriers to employ networks based on wideband cdma (wcdma) technology to deliver data to end users.

However, implementing advanced wireless technologies such as WCDMA and/or high speed packet access (HSDPA), etc., still requires overcoming some architectural difficulties. For example, rake receivers are the most commonly used receivers in CDMA systems, primarily because of their simplicity and better performance. The rake receiver includes a bank of spreading sequence correlators, each of which receives a single multipath signal. The rake receiver operates on a plurality of discrete paths. It will be very critical for the performance of the receiver to correctly indicate the propagation paths and to place fingers (rake fingers) in these propagation paths to track the path positions. The task of tracking propagation paths once fingers are assigned into the path can be challenging given the wide dynamic range of a given WCDMA/HSDPA signal. The received multipath signals may be combined in a number of ways, with Maximum Ratio Combining (MRC) being preferred in the associated receiver. However. Rake receivers are not optimal in many practical systems. For example, the performance of the network is reduced by Multiple Access Interference (MAI), which refers to interference introduced by other users in the network.

In WCDMA downlink, intra-cell interference and inter-cell interference may generate MAI. Signals from neighboring base stations can contribute to inter-cell interference characterized by scrambling codes, channels, and angles of arrival that are different from the desired base station signal. Inter-cell interference may be suppressed using spatial equalization. Spatial equalization may be used to reduce inter-cell interference. In synchronous downlink applications employing orthogonal spreading codes, multi-path propagation can produce intra-cell interference. In some cases, the intra-cell interference includes inter-path interference (IPI). IPI occurs when one or more paths or "fingers" interfere with other paths within a rake receiver. Due to the non-zero cross-correlation between spreading codes with arbitrary time shifts, interference exists between propagation paths (or fingers) after despreading, thereby generating MAI. The level of intra-cell interference is strongly dependent on the channel response. In an approximately flat fading channel, the physical channels are kept almost completely orthogonal to each other, and intra-cell interference does not have any serious impact on the receiver performance. On the other hand, the performance of the rake receiver will be severely degraded by intra-cell interference in the frequency selective channel. Frequency selectivity is common for channels in WCDMA networks.

Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.

Disclosure of Invention

A method and/or system for a delay locked loop in a rake receiver, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.

According to an aspect of the present invention, there is provided a method of processing a signal, the method comprising:

normalizing the signal power of the first control channel according to a threshold value; and

adjusting a sampling time associated with at least one or more of: the first control channel, the second control channel, the third control channel, and the data channel.

Preferably, the second control channel is delayed with respect to the first control channel by a certain period of time.

Preferably, the data channel is a Dedicated Physical Channel (DPCH).

Preferably, the first control channel is a common pilot control channel (CPICH).

Preferably, the second control channel is a common pilot control channel (CPICH).

Preferably, the method further comprises combining the signal power of the first control channel for at least two antennas.

Preferably, the method further comprises normalizing the combined signal power of the first control channel according to the threshold value.

Preferably, the method further comprises combining the signal power of the second control channel for at least two antennas.

Preferably, the method further comprises adjusting a sampling time associated with at least one or more of the following according to a comparison between the normalized combined signal power of the first control channel and the combined signal power of the second control channel: the first control channel, the second control channel, the third control channel, and a data channel.

According to an aspect of the invention, there is provided a machine readable storage having stored thereon a computer program having at least one code section for processing a signal, the machine executable by the at least one code section and performing the steps of:

normalizing the signal power of the first control channel according to a threshold value; and

adjusting a sampling time associated with at least one or more of: the first control channel, the second control channel, the third control channel, and the data channel.

Preferably, the second control channel is delayed with respect to the first control channel by a certain period of time.

Preferably, the data channel is a Dedicated Physical Channel (DPCH).

Preferably, the first control channel is a common pilot control channel (CPICH).

Preferably, the second control channel is a common pilot control channel (CPICH).

Preferably, the at least one code segment comprises code for combining the signal power of the first control channel of at least two antennas.

Preferably, said at least one code segment comprises code for normalizing said combined signal power of said first control channel in accordance with said threshold value.

Preferably, the at least one code segment comprises code for combining the signal power of the second control channels of at least two antennas.

Preferably, said at least one code segment comprises code for adjusting sampling times related to at least one or more of the following according to a comparison between said normalized combined signal power of said first control channel and said combined signal power of said second control channel: the first control channel, the second control channel, the third control channel, and a data channel.

According to an aspect of the present invention, there is provided a signal processing system, the system comprising:

one or more circuits for normalizing a signal power of a first control channel according to a threshold value; and

the one or more circuits are configured to adjust a sampling time associated with at least one or more of: the first control channel, the second control channel, the third control channel, and the data channel.

Preferably, the second control channel is delayed with respect to the first control channel by a certain period of time.

Preferably, the data channel is a Dedicated Physical Channel (DPCH).

Preferably, the first control channel is a common pilot control channel (CPICH).

Preferably, the second control channel is a common pilot control channel (CPICH).

Preferably, the one or more circuits are operable to combine the signal power of the first control channel for at least two antennas.

Preferably, the one or more circuits are configured to normalize the combined signal power of the first control channel according to the threshold value.

Preferably, the one or more circuits are operable to combine the signal power of the second control channel for at least two antennas.

Preferably, the one or more circuits are operable to adjust a sampling time associated with at least one or more of the following according to a comparison between the normalized combined signal power of the first control channel and the combined signal power of the second control channel: the first control channel, the second control channel, the third control channel, and a data channel.

Various advantages, objects, and novel features of the invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings.

Drawings

The invention will be further described with reference to the accompanying drawings and examples, in which:

fig. 1A is a block diagram of a wireless communication user equipment according to an embodiment of the present invention;

fig. 1B is an exemplary block diagram of a rake receiver according to an embodiment of the present invention;

FIG. 2 is an exemplary block diagram of a transmitter with transmit antenna diversity according to an embodiment of the present invention;

FIG. 3A is an exemplary block diagram of a finger architecture for transmit antenna diversity according to an embodiment of the present invention;

FIG. 3B is an exemplary block diagram of a receiver front end in accordance with an embodiment of the invention;

fig. 4 is an exemplary block diagram of received signal inversion and decoding in a rake receiver in accordance with an embodiment of the present invention;

fig. 5A is an exemplary block diagram of a delay locked loop of a differential rake receiver based on channel signal power, in accordance with an embodiment of the present invention;

fig. 5B is an exemplary block diagram of a delay locked loop of a rake receiver with transmit diversity based on the difference in channel signal power, in accordance with an embodiment of the present invention;

fig. 6A is an exemplary block diagram of a delay locked loop of a rake receiver in accordance with an embodiment of the present invention;

fig. 6B is an exemplary block diagram of a delay locked loop of a rake receiver with transmit diversity according to an embodiment of the present invention.

Detailed Description

Some embodiments of the present invention provide a method and/or system for a delay locked loop for a rake receiver. Some aspects of the invention include normalizing the signal power of the first control channel based on a threshold value. The sampling time associated with at least one or more of the following may be adjusted based on a comparison between the normalized signal power of the first control channel and the signal power of the second control channel: a first control channel, a second control channel, an on-time (on-time) control channel, and a data channel. The second control channel is delayed relative to the first control channel by a particular period of time. The first control channel and the second control channel are common pilot control channels (CPICHs). And normalizing the combined signal power of the first control channel according to the threshold value.

Fig. 1A is a block diagram of a wireless communication user equipment according to an embodiment of the present invention. Referring to fig. 1A, a User Equipment (UE)60 is shown.

UE 60 includes a host interface 62, a digital receiver processing module 64, an analog-to-digital converter 66, a filtering/gain module 68, a down conversion module 70, a low noise amplifier 72, a receiver filter module 71, a transmitter/receiver (Tx/Rx) switching module 73, a local oscillation module 74, a memory 75, a digital transmitter processing module 76, a digital-to-analog converter 78, a filtering/gain module 80, an up conversion module 82, a power amplifier 84, a transmitter filter module 85, and an antenna 86, which are operatively coupled as shown. The antenna 86 may be shared by the transmit and receive paths according to the control of the Tx/Rx switching module 73.

The digital receiver processing module 64 and the digital transmitter processing module 76, in combination with executable instructions stored in the memory 75, may be used to implement digital receiver functions and digital transmitter functions, respectively. Digital receiver functions may include, but are not limited to, demodulation, constellation demapping, decoding, and/or descrambling. Digital transmitter functions include, but are not limited to, scrambling, encoding, constellation mapping, and modulation. Digital receiver and transmitter processing modules 64 and 76 may be implemented using shared processing devices, separate processing devices, and/or multiple processing devices, for example, which may be microprocessors, microcontrollers, digital signal processors, microcomputers, central processing units, field programmable gate arrays, programmable logic devices, state machines, logic circuits, analog circuits, digital circuits, and/or any device that may process signals (analog and/or digital) based on operational instructions.

The memory 75 may be a single memory device or a plurality of memory devices. For example, memory 75 may be read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, and/or any device that may store digital information. When digital receiver processing module 64 and/or digital transmitter processing module 76 perform one or more of its functions via a state machine, analog circuitry, digital circuitry, and/or logic circuitry, the memory storing the corresponding operational instructions may be embedded with the circuitry comprising the state machine, analog circuitry, digital circuitry, and/or logic circuitry. Memory 75 may be used for storage and digital receiver processing module 64 and/or digital transmitter processing module 76 may be used to execute operational instructions corresponding to at least a portion of the functions described herein.

In operation, UE 60 may be used to receive outbound data through host interface 62. The host interface 62 may be used to send outbound data to the digital transmitter processing module 76. The digital transmitter processing module 76 may be configured to process outbound data, such as IEEE802.11 a, IEEE802.11b, and bluetooth, in accordance with a particular wireless communication standard or protocol to thereby generate digitally transmitted formatted data. The digital transmit formatted data may be a digital baseband signal or a digital low-IF signal, where the frequency range, e.g., low IF, may be hundreds of kilohertz to several megahertz.

The digital-to-analog converter 78 is used to convert the digital transmit formatted data from the digital domain to the analog domain. The filtering/gain module 80 may be used to filter the analog baseband signal and/or adjust its gain before passing it to the up-conversion module 82. The up-conversion module 82 may be used to directly convert the analog baseband signal or the low IF signal to an RF signal according to a transmitter local oscillation 83 provided by the local oscillation module 74. The power amplifier 84 is used to amplify the RF signal and thereby generate an outbound RF signal, which may be filtered by the transmitter filter module 85. The antenna 86 may be used to transmit the outbound RF signal to a target device, such as a base station, an access point, and/or another wireless communication device.

UE 60 may be operative to receive, via antenna 86, inbound RF signals that may be transmitted by a base station, an access point, or another wireless communication device. The antenna 86 may be used to pass the inbound RF signals through the Tx/Rx switching module 73 to the receiver filter module 71, where the Rx filter module 71 band-pass filters the inbound RF signals. The Rx filter module 71 may be used to pass the filtered RF signal to a low noise amplifier 72, and the low noise amplifier 72 amplifies the inbound RF signal and generates an amplified inbound RF signal. The low noise amplifier 72 may be used to pass the amplified inbound RF signal to a down conversion module 70 which converts the amplified inbound RF signal directly to an inbound low IF signal or baseband signal based on receiver local oscillation 81 provided by a local oscillation module 74. The down conversion module 70 is used to pass the inbound low IF signal or baseband signal to the filtering/gain module 68. The filter/gain module 68 may be used to filter and/or attenuate the inbound low-IF signal or the inbound baseband signal to thereby generate a filtered inbound signal.

The analog-to-digital converter 66 may be used to convert the filtered inbound signal from the analog domain to the digital domain, thereby generating digital receive formatted data. The digital receiver processing module 64 may be used to decode, descramble, demap, and/or demodulate the digitally received formatted data to obtain inbound data. The host interface 62 may be used to communicate the obtained inbound data to the wireless communication host device.

The local oscillation module 74 may be used to adjust the output frequency of the received local oscillation signal. The local oscillator module 74 is operable to receive a frequency correction input to adjust the output local oscillator signal to generate a frequency corrected local oscillator signal output.

Fig. 1B is an exemplary block diagram of a rake receiver according to an embodiment of the present invention. Referring to fig. 1B, a rake receiver 100 is shown. Rake receiver 100 includes a plurality of fingers, finger 1116, finger 2118, finger 3120, and combiner 122. Each finger, for example, finger 1116 may include a down-sampler 104, a delay-locked loop (DLL) module 102, a descrambler 106, a DPCH despreader 108, a CPICH despreader 112, a channel compensation module 110, and a delay equalizer 114.

DLL 102 may comprise suitable logic, circuitry, and/or code that may be adapted to receive an input signal from baseband and to generate an output signal to each finger, such as finger 1116, finger 2118, and finger 3120, based on a determined ratio of accumulated signal power between the earliest offset path (early offset path) CPICH and the latest offset path (late offset path) CPICH.

The downsampler 104 may comprise suitable logic, circuitry, and/or code and may be operable to receive the delayed output signal from the DLL 102 and the input signal from baseband and to downsample the received signals. The downsampler 104 may output the downsampled received signal to the descrambler 106. The sampling instants, i.e. the sampling phases, can be controlled by the output of the DLL 102.

The descrambler 106 may comprise suitable logic, circuitry, and/or code that may enable multiplication of a received signal with a scrambling code and a delayed version of the scrambling code. Each delay may correspond to a separate plurality of paths combined by the rake receiver 100. The DPCH despreader 108 may comprise suitable logic, circuitry, and/or code that may be adapted to despread the descrambled data for each path in the data channel by multiplying the despread data with an Orthogonal Variable Spreading Factor (OVSF) code. The CPICH despreader 112 may comprise suitable logic, circuitry, and/or code and may be adapted to despread the descrambled data for each path in the control channel by multiplying the descrambled data by the OVSF code.

The channel compensation module 110 may comprise suitable logic, circuitry, and/or code that may be adapted to receive a plurality of generated channel estimates for each channel based on a descrambled signal and generate a plurality of derotated output signals to the delay equalizer 114. The delay equalizer 114 may comprise suitable logic, circuitry, and/or code and may be adapted to receive an input signal from the channel compensation module 110 and generate a delay output signal to the combiner 122 to compensate for differential delays in symbol arrival times at the fingers. Combiner 122 may comprise suitable logic, circuitry, and/or code that may be adapted to receive I and Q signals from fingers (e.g., finger 1116, finger 2118, and finger 3120) and combine the received signals according to a combining algorithm (e.g., maximal ratio combining).

The rake receiver 100 may be a wireless receiver that may be designed to utilize multiple sub-receivers to calculate the effects of multipath fading. Each sub-receiver may be delayed in order to tune with the independent multipath component. Each component can be independently decoded and combined to achieve a higher signal-to-noise ratio (SNR) (or Eb/No) in a multipath environment.

In the rake receiver 100, each multipath may be assigned a finger to obtain the maximum received signal energy. Each of these different multipath signals may be combined together to form a composite signal, which may achieve better characteristics than a single path. The received signal may be split into multiple independent paths that may be combined with their corresponding channel estimates.

Fig. 2 is an exemplary block diagram of a transmitter with transmit antenna diversity according to an embodiment of the present invention. Referring to fig. 2, a transmitter 200 includes a Dedicated Physical Channel (DPCH) module 202, a space-time transmit diversity (STTD) mapping module 203, a plurality of mixers 204, 206, and 208, a plurality of combiners 210 and 212, a main transmit antenna (Tx1)214, and an auxiliary transmit antenna (Tx2) 216.

The DPCH module 202 is configured to receive a plurality of input channels, e.g., a Dedicated Physical Control Channel (DPCCH) and a Dedicated Physical Data Channel (DPDCH). The DPCH module 202 may control the power of the DPCCH and DPDCH simultaneously. The STTD mapping module 203 may be turned off in the closed-loop mode, and a User Equipment (UE) may determine a plurality of weight factors W₁And W₂And transmits a signal to an access point or a cell transceiver of a UMTS Terrestrial Radio Access Network (UTRAN) through a feedback indicator (FBI) field of the uplink DPCCH. The STTD mapping module 203 is enabled in the open loop mode and applies a plurality of weighting factors W₁And W₂Is determined to be 1.

Mixer 204 may be used to mix the output of DPCH module 202 with the spread and/or scrambled signal to generate a spread complex-valued signal that may be input to mixers 206 and 208. Mixers 206 and 208 may each use a weight factor W₁And W₂The complex-valued input signals are weighted and generated for output to a plurality of combiners 210 and 212, respectively. Combiners 210 and 212 combine the outputs generated by mixers 206 and 208 with pilot channel 1 (e.g., common pilot channel 1(CPICH 1)) and pilot channel 2 (e.g., common pilot channel 2(CPICH 2)), respectively. The common pilot channels 1 and 2 have a fixed channel code configuration for measuring the phase-amplitude signal strength of the channel. Antennas 214 and 216 may receive the outputs generated from combiners 210 and 212 and may transmit wireless signals.

For example, in closed loop mode 1, the weighting factor W₁May be a constant quantity, and the weight factor W₂May be a complex valued signal. Weight factor W₂And corresponding phase adjustmentMay be determined by a User Equipment (UE) and may transmit a signal to a UMTS Terrestrial Radio Access Network (UTRAN) access point or cell transceiver by using a feedback indicator (FBI) field of the uplink DPCCH. For example, for closed loop mode 1, the signal may be generated byThe two antennas transmit different orthogonal dedicated pilot symbols in the downlink DPCCH. The UE can estimate the channel from each antenna perspective separately using the CPICH. UE calculates phase adjustment w once per slot₁＝e^JφAnd applied to the UTRAN access point to maximize the received power of UE 60.

For example, in the case of non-soft handover, the weight vector that maximizes the following equation is obtainedwThe feedback information can be calculated:

P＝w ^HH^HHw(1)

wherein H ═ 2 [, ]h ₁ h ₂]And isw＝[w₁，w₂]^TWherein the column vectorh ₁Andh ₂representing the estimated channel impulse responses of transmit antennas 1 and 2, with a length equal to the length of the channel impulse response.wThe adjustment value is calculated corresponding to the UE 60.

Fig. 3A is an exemplary block diagram of a finger architecture for transmit antenna diversity according to an embodiment of the present invention. Referring to fig. 3A, a common pilot channel for transmit antenna 1(CPICH1)301, a common pilot channel for transmit antenna 2(CPICH2)303, a Dedicated Physical Channel (DPCH) module 305, and a Received Signal Code Power (RSCP) module 328 are shown.

The CPICH 1301 includes a receiver front end module 302, a descrambler 304, an accumulator (accumulator)306, and an IIR filter 308. The CPICH 2303 includes a receiver front end module 310, a descrambler 312, an accumulator 314, and an IIR filter 316. The DPCH module 305 includes a receiver front end module 318, a descrambler 320, an accumulator 322, and a channel compensation and decoding module 326.

The plurality of receiver front-end modules 302 and 310 may comprise suitable logic, circuitry and/or code that may enable processing of received RF signals from transmit antenna 1 and transmit antenna 2, respectively. The receiver front-end module 318 may comprise suitable logic, circuitry and/or code that may enable processing of received RF signals from the receiver antenna 1. The multiple receiver front-end modules 302, 310, and 318 may perform filtering, amplification, and analog-to-digital (a/D) conversion operations. The plurality of receiver front end modules 302, 310, and 318 are used to amplify and convert the received analog RF signal to baseband. The plurality of receiver front-end modules 302, 310, and 318 include analog-to-digital (a/D) converters for digitizing the received analog baseband signals.

The plurality of descramblers 304, 312, and 320 may comprise suitable logic, circuitry, and/or code that may enable multiplication of a received signal with a scrambling code and a delayed version of the scrambling code. Each delay corresponds to an independent plurality of paths that may be combined by the rake receiver 100. The plurality of descramblers 304, 312 and 320 are for despreading the descrambled data of each path by multiplying the descrambled data by a spreading code. The multiple descramblers 304, 312, and 320 may also be used to multiply the received signal with a scrambling code and/or an Orthogonal Variable Spreading Factor (OVSF) code.

The plurality of accumulators 306, 314, and 322 may comprise suitable logic, circuitry, and/or code that may enable accumulation of descrambled signals from the plurality of descramblers 304, 312, and 320, respectively. The plurality of IIR filters 308 and 318 may comprise suitable logic, circuitry, and/or code that may enable IIR filtering of the received signal paths from the plurality of accumulators 306 and 314, respectively, to generate output signals to the RSCP module 328 and the channel compensation and decoding module 326.

The channel compensation and decoding module 326 may combine the same symbols obtained through different paths using corresponding channel information and a combining method such as Maximum Ratio Combining (MRC), and generate an output signal to the combiner. The RSCP module 328 may comprise suitable logic, circuitry, and/or code and may be adapted to measure received signal code power or SNR for multiple multipath signals from the transmit antennas 1 and 2 and generate output signals to the control unit/firmware.

The generated code of at least one pilot channel, such as CPICH 1301 or CPICH 2303, may be adjusted to measure the signal strength of each of a plurality of received multipath signals, which may be modified. The signal strength of a plurality of received multipath signals may be measured in a pilot channel (e.g., CPICH 1301) by assigning a zero to the generated code or scrambling code in descrambler 304.

Fig. 3B is an exemplary block diagram of a receiver front end in accordance with an embodiment of the present invention. Referring to fig. 3B, a receiver front end module 350, a receiver antenna 351, and a baseband processing module 364 are shown. The receiver front end module 350 includes a Low Noise Amplifier (LNA)352, a mixer (mixer)354, an oscillator 356, a low noise amplifier 358, a band pass filter 360, and an analog to digital converter (a/D) 362.

The receiver front-end module 350 may comprise suitable logic, circuitry, and/or code that may enable converting a received RF signal to baseband. An input of the low noise amplifier 352 may be connected to the antenna 351 so that an RF signal may be received from the antenna 351. The low noise amplifier 352 may comprise suitable logic, circuitry, and/or code that may enable receiving an input RF signal from the antenna 351 and amplifying it in a manner that may result in a low additive noise in an output signal generated by the low noise amplifier 352.

The multiplier 354 in the receiver front-end module 350 may comprise suitable logic, circuitry, and/or code that may enable mixing of the output of the low noise amplifier 352 with an oscillator signal generated by an oscillator 356. The oscillator 356 may comprise suitable logic, circuitry, and/or code that may enable providing an oscillating signal that may be used to mix down to baseband with an output signal generated from an output of the low noise amplifier 352. A Low Noise Amplifier (LNA) or amplifier 358 may comprise suitable logic, circuitry, and/or code that may enable low noise amplification and output of the signal generated by mixer 354. The output of the low noise amplifier or amplifier 358 may be passed to a transmit path bandpass filter 360. The band pass filter 360 may comprise suitable logic, circuitry, and/or code that may enable band pass filtering of an output signal generated by the output of the low noise amplifier 360. The band pass filter module 360 may be used to hold the desired signal and filter out unwanted signal components, such as higher signal components including noise. The output of the band pass filter 360 may be passed to an analog to digital converter 362 for processing.

The analog-to-digital converter (a/D)362 may comprise suitable logic, circuitry, and/or code that may enable conversion of an analog signal generated from the output of the transmit path bandpass filter 360 to a digital signal. The analog-to-digital converter 362 may generate a sampled digital representation of the bandpass filtered signal, which may be passed to the baseband processing module 364 for processing. The baseband processing module 364 may comprise suitable logic, circuitry, and/or code that may enable processing of digital baseband signals received from the output of the a/D362. Although a/D362 is shown as part of receiver front-end module 350, the invention is not so limited. Thus, the A/D362 may be integrated as part of the baseband processing module 364. In operation, the receiver front-end module 350 may be used to receive RF signals via the antenna 351 and convert the received RF signals into a sampled digital representation, which may be passed to the baseband processing module 364 for processing.

Fig. 4 is an exemplary block diagram of the inversion and decoding of a received signal in a rake receiver in accordance with an embodiment of the present invention. Referring to fig. 4, a channel compensation and Space Time Transmit Diversity (STTD) decoding module 402 is shown. The channel compensation and STTD decoding module 402 may include a channel compensation module 404, an STTD decoding module 406, a plurality of multiplexers 416 and 428, a plurality of multipliers 420 and 424, a plurality of conjugation modules 418 and 426, and a summer 422.

The channel compensation module 404 may include a plurality of conjugate modules 408 and 414 and a plurality of multipliers 410 and 412. The channel compensation module 404 is configured to receive the data signal from the accumulator 322. The channel compensation module 404 is used to receive the channel estimate h1n or h3n from the IIR filter 308 in the CPICH 1301. The channel compensation module 404 is configured to receive the channel estimate h2n or h4n from the IIR filter 316 in the CPICH 2303.

A plurality of conjugation modules 408 and 414 may be used to generate conjugates of the channel estimates h1n and h2n received from IIR filters 308 and 316, respectively. Multiplier 410 may be used to multiply the data received from accumulator (accumulator)322 with the conjugate of channel estimate h1n, thereby generating a first inverted output. Multiplier 412 is operative to multiply the data received from accumulator 322 by the conjugate of channel estimate h2n to thereby generate a second inverted output. The first inverted output may be received by the multiplexer 416 and the second inverted output may be received by the STTD decoding module 406.

The STTD decoding module 406 may comprise suitable logic, circuitry, and/or code that may enable receiving the inverted output from the channel compensation module 404 and decoding the received inverted signal according to open-loop or closed-loop transmit diversity to generate a decoded output signal to the multiplexer 416.

The multiplexer 416 may receive the first inverted output from the channel compensation module 404 and the decoded output signal from the STTD decoding module 406 and select a particular signal based on determining whether the rake receiver performs transmit diversity. If transmit diversity is not being performed in the rake receiver, the multiplexer 416 may select the first inverted output from the channel compensation module 404 and output the selected inverted output to the combiner via the multiplexer 428. If transmit diversity is already being performed in the rake receiver, the multiplexer 416 may select the inverted output signal from the STTD decoding module 406 and generate an output to the multiplexer 428.

For closed loop transmit diversity, the plurality of conjugation modules 418 and 426 may receive a plurality of weight factors W, respectively₁And W₂. For example, for finger 0, the plurality of conjugate modules 418 and 426 may generate conjugates of the received weight factors, W1_0 and W2_0, respectively.

The multiplier 420 may multiply the first inverted output received from the channel compensation module 404 with the conjugate of the received weight factor, W1_0, to generate a first output to the summer 422. The multiplier 424 may multiply the second inverted output received from the channel compensation module 404 with the conjugate W2_0 of the received weight factor, thereby generating a second output to the summer 422. Summer 422 may be used to sum the received first and second outputs and generate an output to multiplexer 428.

For open loop transmit diversity, multiplexer 428 is used to select the output received from multiplexer 416 and generate an output to the combiner. For closed loop transmit diversity, a multiplexer 428 may be used to select the output received from the summer 422 and generate an output to the combiner.

Fig. 5A is an exemplary block diagram of a delay locked loop of a differential rake receiver based on channel signal power, in accordance with an embodiment of the present invention. Referring to fig. 5A, an earliest offset path common pilot channel (CPICH)501, a latest offset path CPICH 503, a summing module 518, an accumulator 520, a comparator 522, a threshold 524, and a or gate module 526 are shown. The earliest offset path CPICH501 may include a receiver front end module 502, a descrambler 504, an accumulator 506, and a power module 508. The latest offset path CPICH 503 may include a receiver front end module 510, a descrambler 512, an accumulator 514, and a power module 516. The earliest offset path CPICH501 may be ahead of the on-time CPICH by a certain time period. The latest offset path CPICH 503 may be delayed from the on-time CPICH by a certain time period.

The plurality of receiver front-end modules 502 and 510 may comprise suitable logic, circuitry, and/or code that may enable processing of RF signals received from transmit antennas. The multiple receiver front-end modules 502 and 510 may perform such operations as filtering, amplification, and analog-to-digital (a/D) conversion. The plurality of receiver front end modules 502 and 510 are used to amplify and convert the received analog RF signals to baseband. The plurality of receiver front-end modules 502 and 510 each include an analog-to-digital (a/D) converter for digitizing the received analog baseband signals.

The plurality of descramblers 504 and 512 may comprise suitable logic, circuitry, and/or code that may enable multiplication of a received signal with a scrambling code and a delayed version of the scrambling code. The plurality of descramblers 504 and 512 are for despreading the descrambled data of each path by multiplying the descrambled data by a spreading code. The multiple descramblers 512 and 520 may also be used to multiply the received signal with scrambling codes and/or Orthogonal Variable Spreading Factor (OVSF) codes.

The plurality of accumulators 506 and 514 may comprise suitable logic, circuitry, and/or code that may enable accumulation of descrambled signals from the plurality of descramblers 504 and 512, respectively. The power module 508 may comprise suitable logic, circuitry, and/or code and may be adapted to calculate the signal power of the earliest offset path CPICH 501. For example, the signal power may be based on the square of the amplitude of the earliest offset path CPICH 501. The power module 516 may comprise suitable logic, circuitry, and/or code that may enable calculation of the signal power of the latest offset path CPICH 503. For example, the signal power may be based on the square of the amplitude of the latest offset path CPICH 503.

The summing module 518 may be used to add or subtract the signal power of the earliest offset path CPICH501 calculated by the power module 508 to the signal power of the latest offset path CPICH 503 calculated by the power module 516. The accumulator 520 may comprise suitable logic, circuitry, and/or code and may be adapted to accumulate and store a difference between the signal power of the earliest offset path CPICH501 calculated by the power module 508 and the signal power of the latest offset path CPICH 503 calculated by the power module 516. The comparator 522 may comprise suitable logic, circuitry, and/or code and may be adapted to compare a difference between the accumulated signal power of the earliest offset path CPICH501 calculated by the power module 508 and the signal power of the latest offset path CPICH 503 calculated by the power module 516 to a threshold value 524 and generate a plurality of advance/delay signals to control the sampling times of the fingers of the control and data channels. The advance/retard signal may be provided as an input to an or gate block 526. The OR gate module 526 may comprise suitable logic, circuitry, and/or code that may enable clearing of the accumulator 520. The OR gate module 526 may be used to receive a plurality of advance/retard signals that may clear the accumulator module 520. The output of the comparator module 522 may be used to adjust the sampling time or phase of the fingers of the control channel and the data channel.

Fig. 5B is an exemplary block diagram of a delay locked loop of a rake receiver with transmit diversity based on the difference in channel signal power in accordance with an embodiment of the present invention. Referring to fig. 5B, earliest offset path common pilot channel (CPICH) CPICH 551 for TX antenna 1, earliest offset path common pilot channel (CPICH) CPICH553 for TX antenna 2, latest offset path CPICH555 for TX antenna 1, latest offset path CPICH 557 for TX antenna 2, a plurality of accumulators 584 and 586, summing module 587, comparator 592, threshold 594, and or gate module 596 are shown. The earliest offset path CPICH 551 for TX antenna 1 may be ahead of the on-time CPICH by a certain time period. The latest offset path CPICH555 for TX antenna 1 may be delayed from the on-time CPICH by a certain time period. The earliest offset path CPICH553 for TX antenna 2 may be ahead of the on-time CPICH by a certain time period. The latest offset path CPICH 557 for TX antenna 2 may be delayed from the on-time CPICH by a certain time period.

The CPICH 551 may include a receiver front end module 560, a descrambler 562, an accumulator 564, and a power module 566. The CPICH553 may include a receiver front end module 552, a descrambler 554, an accumulator 556, and a power module 558. The CPICH555 may include a receiver front end module 568, a descrambler 570, an accumulator 572, and a power module 574. The CPICH 557 may include a receiver front end module 576, a descrambler 578, an accumulator 580, and a power module 582.

The plurality of receiver front-end modules 560 and 552 may comprise suitable logic, circuitry, and/or code that may enable processing of the earliest offset path RF signal received from the transmit antenna 1. The multiple receiver front end modules 568 and 576 may comprise suitable logic, circuitry and/or code that may be operable to process the earliest offset path RF signal received from the transmit antenna 2. The multiple receiver front end modules 560, 552, 568, and 576 may perform operations such as filtering, amplification, and analog-to-digital (a/D) conversion. The plurality of receiver front end modules 560, 552, 568, and 576 operate to amplify and convert the received analog RF signals to baseband. The plurality of receiver front-end modules 560, 552, 568, and 576 may each include an analog-to-digital (a/D) converter for digitizing the received analog baseband signals.

The plurality of descramblers 562, 554, 570 and 578 are substantially the same as shown in figure 5A. The plurality of accumulators 564, 556, 572, and 580 are substantially the same as shown in FIG. 5A. The plurality of power modules 566, 558, 574 and 582 may comprise suitable logic, circuitry and/or code that may enable calculation of signal power for the CPICH 551, CPICH553, CPICH555 and CPICH 557, respectively. These signal powers may be based on the square of the amplitude of the corresponding CPICH. The accumulator 584 may comprise suitable logic, circuitry, and/or code and may be adapted to accumulate and store the determined signal power of the CPICHs 551 and 553 and generate an output to the summer 587. The accumulator 586 may comprise suitable logic, circuitry, and/or code and may be operable to accumulate and store the determined signal power of the CPICHs 555 and 557 and generate an output to the summer 587.

A summing module 587 may be used to add or subtract the signal power accumulated by accumulator 584 to the signal power accumulated by accumulator 586. The comparator 592 may comprise suitable logic, circuitry, and/or code and may comprise suitable circuitry that may be adapted to compare the cumulative difference between the signal power of the earliest offset path CPICH and the signal power of the latest offset path CPICH to a threshold 594 and generate a plurality of enable signals (enable signals) to the or gate module 596. The OR gate module 596 may comprise suitable logic, circuitry, and/or code that may enable clearing of the plurality of accumulators 584 and 586. Or gate module 596 may be used to receive a plurality of advance/retard signals that may control the sampling times of the fingers of the control channel and the data channel. The advance/retard signal may be an input to an or gate module 596. The OR gate module 596 may be configured to receive the plurality of advance/retard signals and clear the plurality of accumulator modules 584 and 586. The output of the comparator module 592 can be used to adjust the sampling time or phase of its fingers for the control channel and the data channel.

Fig. 6A is an exemplary block diagram of a delay locked loop of a rake receiver in accordance with an embodiment of the present invention. Referring to fig. 6A, the earliest offset path common pilot channel (CPICH) CPICH 651 for antenna 1, the latest offset path CPICHCPICH 653 for antenna 1, a plurality of accumulators 668 and 670, a multiplier 674, a threshold 672, a comparator 676, and a gate module 678 are shown.

The CPICH 651 may include a receiver front end module 652, a descrambler 654, an accumulator 656, and a power module 658. The CPICH 653 may include a receiver front end module 660, a descrambler 662, an accumulator 664, and a power module 666. The various modules in the CPICH 651 and CPICH 653 are substantially the same as described in fig. 5A. The CPICH 653 may be delayed for a particular period of time than the CPICH 651.

The power modules 658 and 666 may comprise suitable logic, circuitry, and/or code that may enable the calculation of the signal power of the CPICH 651 and the signal power of the CPICH 653, respectively. For example, the signal power may be based on the square of the amplitude of the CPICH 651, or on the square of the amplitude of the CPICH 653.

The accumulator 668 may comprise suitable logic, circuitry, and/or code that may enable accumulation of the signal power of the CPICH 651 as calculated by the power module 658. A multiplier 674 may be used to multiply and normalize the signal power accumulation value of the CPICH 651 by a threshold value 672. The accumulator 670 may comprise suitable logic, circuitry, and/or code and may enable accumulation of the signal power of the CPICH 653 calculated by the power module 666.

The comparator 676 may comprise suitable logic, circuitry, and/or code and may comprise suitable logic, circuitry and/or code that may be operable to compare an integrated value of the signal power of the CPICH 651 that has been normalized to an integrated value of the signal power of the CPICH 653 and generate a plurality of advance/retard signals that may be used to control the sampling times of the fingers of the control channel and the data channel. The advance/retard signal may be provided as an input to an or gate module 678. The or gate module 678 may comprise suitable logic, circuitry, and/or code that may enable clearing of the plurality of accumulators 668 and 670. An or gate module 678 may be used to receive the multiple advance/delay signals and clear the multiple accumulators 668 and 670. The output of the comparator module 676 may be used to adjust the sampling time and phase of the rake fingers for the control channel and the data channel.

Fig. 6B is an exemplary block diagram of a delay locked loop of a rake receiver with transmit diversity according to an embodiment of the present invention. Referring to fig. 6B, the earliest offset path common pilot channel (CPICH) CPICH601 for antenna 1, the earliest offset path common pilot channel (CPICH) CPICH 603 for antenna 2, the latest offset path CPICH 605 for antenna 1, the latest offset path CPICH 607 for antenna 2, a plurality of accumulators 634 and 636, a multiplier 638, a threshold 640, a comparator 642, and a gate module 644 are shown. The earliest offset path CPICH601 for antenna 1 may be ahead of the punctual CPICH by a certain time period. The latest offset path CPICH 605 for TX antenna 1 may be delayed from the on-time CPICH by a certain time period. The earliest offset path CPICH 603 for TX antenna 2 may be ahead of the on-time CPICH by a certain time period. The latest offset path CPICH 607 for TX antenna 2 may be delayed from the on-time CPICH by a certain time period.

The CPICH601 may include a receiver front end module 610, a descrambler 612, an accumulator 614, and a power module 616. The CPICH 603 may include a receiver front end module 602, a descrambler 604, an accumulator 606, and a power module 608. The CPICH 605 may include a receiver front end module 618, a descrambler 620, an accumulator 622, and a power module 624. The CPICH 607 may include a receiver front end module 626, a descrambler 628, an accumulator 630, and a power module 632.

The various blocks in the CPICH601, CPICH 603, CPICH 605, and CPICH 607 are substantially the same as shown in fig. 5A. The process of obtaining diversity gain can be used to combat multipath fading in a wireless cellular communication system, since signal quality can be improved without increasing transmit power or losing bandwidth efficiency. In a single antenna W-CDMA handset, the attenuation of different multipath signals may be independent. The receiver may demodulate the same signal from several different multipath signals and combine them into different multipath signals. The resulting combined signal is stronger than the individual signals. The CPICH 605 may be delayed with respect to the CPICH601 by a particular time period. Similarly, the CPICH 607 may be delayed with respect to the CPICH 603 by a particular time period.

The power modules 616 and 608 may comprise suitable logic, circuitry, and/or code that may enable calculation of the signal power of the CPICH601 and the signal power of the CPICH 603, respectively. For example, the signal power may be based on the square of the amplitude of the CPICH601, or based on the square of the amplitude of the CPICH 603. The power modules 624 and 632 may comprise suitable logic, circuitry, and/or code that may enable calculation of the signal power of the CPICH 605 and the signal power of the CPICH 607, respectively. The signal power may be based on the square of the amplitude of the CPICH 605, or alternatively, on the square of the amplitude of the CPICH 607.

The accumulator 634 may comprise suitable logic, circuitry, and/or code that may enable accumulation and storage of the signal power of the CPICH601 calculated by the power module 616 and the signal power of the CPICH 603 calculated by the power module 608. The multiplier 638 may be used to multiply and normalize the accumulated value of the signal power of the CPICH601 and the accumulated value of the signal power of the CPICH 603 by the threshold value 640. The accumulator 636 may comprise suitable logic, circuitry, and/or code that may enable accumulation and preservation of the signal power of the CPICH 605 calculated by the power module 624 and the signal power of the CPICH 607 calculated by the power module 632.

The comparator 642 may comprise suitable logic, circuitry, and/or code and may comprise suitable logic, circuitry, and/or code that may be enabled to compare the integrated value of the normalized signal power of the CPICH601 and signal power of the CPICH 603 to the integrated value of the signal power of the CPICH 605 and signal power of the CPICH 607 and generate a plurality of advance/retard signals that may be utilized to control the sampling times of the fingers of the control channel and the data channel. The advance/retard signal may be provided as an input to an or gate module 644.

The or gate module 644 may comprise suitable logic, circuitry, and/or code that may enable clearing of the plurality of accumulators 634 and 636. The OR gate module 644 is operable to receive the plurality of advance/retard signals and clear the plurality of accumulators 634 and 636. The output of the comparator module 642 may be used to adjust the sampling time and phase of the fingers of the control channel and the data channel.

In accordance with an embodiment of the present invention, a method and system for a rake receiver delay-locked loop includes one or more circuits for normalizing the signal power of a first control channel (e.g., the earliest offset path common pilot control channel (CPICH) CPICH601 for antenna 1) based on a threshold 640. The one or more circuits adjust sampling times associated with at least one or more of the following based on a comparison between a normalized signal power of an earliest offset path CPICH CPICH601 of a first control channel, e.g., antenna 1, and a signal power of a latest offset path CPICHCPICH 605 of the second control channel, e.g., antenna 1: a first control channel such as the earliest offset path CPICH CPICH601 for antenna 1, a second control channel such as the latest offset path CPICH CPICH 605 for antenna 1, an on-time control channel, and a data channel. The latest offset path CPICH CPICH 605 of the second control channel, e.g., antenna 1, is delayed by a particular period of time relative to the earliest offset path CPICH CPICH601 of the first control channel, e.g., antenna 1.

Or gate module 644 may clear the plurality of accumulators 634 and 636 based on a comparison between the normalized signal power of the earliest offset path CPICHCPICH 601 for a first control channel, e.g., antenna 1, and the signal power of the latest offset path CPICH CPICH 605 for the second control channel, e.g., antenna 1. Accumulator 634 may be used to combine the signal power of the first control channel for one or more antennas. For example, accumulator 634 may be used to combine the signal power of earliest offset path CPICH CPICH601 for antenna 1 and the signal power of earliest offset path CPICH CPICH 603 for antenna 2. The rake receiver 100 may normalize the combined signal power of the first control channel based on a threshold 640. For example, the rake receiver 100 may normalize the combined signal power for the earliest offset path CPICH CPICH601 for antenna 1 and the earliest offset path CPICH CPICH 603 for antenna 2 based on a threshold value 640.

Accumulator 636 may be used to combine the signal power of the second control channel for one or more antennas. For example, accumulator 636 may be used to combine the signal power of latest offset path CPICH CPICH 605 for antenna 1 and the signal power of latest offset path CPICH CPICH 607 for antenna 2. The one or more circuits may be configured to adjust sample times associated with the first control channel (e.g., earliest offset path CPICH CPICH601 for antenna 1 and earliest offset path CPICH CPICH 603 for antenna 2), the on-time control channel, and the data channel based on a comparison of a normalized combined signal power of the first control channel (e.g., earliest offset path CPICH CPICH601 for antenna 1 and earliest offset path CPICH CPICH 603 for antenna 2) and a combined signal power of the second control channel (e.g., signal power of latest offset path CPICH CPICH 605 for antenna 1 and latest offset path CPICH CPICH 607 for antenna 2).

The one or more circuits may be configured to adjust the offset associated with the second control channel (the signal power of the latest offset path CPICHCPICH 605 for antenna 1 and the latest offset path CPICH CPICH 607 for antenna 2) based on a comparison of the normalized combined signal power of the first control channel (e.g., the earliest offset path CPICH CPICH601 for antenna 1 and the earliest offset path CPICH CPICH 603 for antenna 2) and the combined signal power of the second control channel (e.g., the signal power of the latest offset path CPICH CPICH 605 for antenna 1 and the latest offset path CPICH CPICH 607 for antenna 2).

Another embodiment of the present invention provides a machine-readable storage, having stored thereon, a computer program having at least one code section executable by a machine for causing the machine to perform the steps as described above for a delay locked loop of a rake receiver.

Accordingly, the present invention may be realized in hardware, software, or a combination of hardware and software. The present invention may be practiced in a centralized fashion in at least one computer system, or in a distributed fashion where elements are spread across different interconnected computer systems. Any kind of computer system, or other apparatus adapted for carrying out the methods described herein, is suited to use the invention. An example of a combination of hardware and software can be a general-purpose computer system with a computer program that, when being loaded and executed, controls the computer system such that it carries out the methods described herein.

The present invention can also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which when loaded in a computer system is able to carry out these methods. Computer program in the present context means any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following: a) conversion to other languages, code or notation; b) regenerated in other forms.

While the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiments disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims (4)

1. A method of processing a signal, the method comprising:

normalizing the signal power of the first control channel according to a threshold value; and

adjusting a sampling time associated with at least one or more of: the first control channel, the second control channel, the third control channel, and the data channel;

the first control channel is an earliest deviation path general pilot control channel, and the earliest deviation path general pilot control channel is ahead of an on-time general pilot control channel by a specific time period; the second control channel is a latest offset path general pilot control channel, and the latest offset path general pilot control channel is delayed by a specific time period compared with an on-time general pilot control channel;

the method further comprises:

accumulating signal power of the first control channel by a first accumulator;

accumulating signal power of the second control channel by a second accumulator;

multiplying and normalizing the accumulated value of the signal power of the first control channel by the threshold value through a multiplier;

comparing, by a comparator, the integrated value of the signal power of the first control channel and the integrated value of the signal power of the second control channel, which have been normalized, and generating a plurality of advance/delay signals to control sampling times of fingers of control channels and data channels;

receiving the plurality of advance/retard signals through an OR gate module and clearing the first accumulator and the second accumulator.

2. The method of claim 1, wherein the data channel is a dedicated physical channel.

3. A signal processing system, the system comprising:

one or more circuits for normalizing a signal power of a first control channel according to a threshold value; and

the one or more circuits are configured to adjust a sampling time associated with at least one or more of: the first control channel, the second control channel, the third control channel, and the data channel;

the first control channel is an earliest deviation path general pilot control channel, and the earliest deviation path general pilot control channel is ahead of an on-time general pilot control channel by a specific time period; the second control channel is a latest offset path general pilot control channel, and the latest offset path general pilot control channel is delayed by a specific time period compared with an on-time general pilot control channel;

the one or more circuits include:

a first accumulator for accumulating signal power of the first control channel;

a second accumulator for accumulating signal power of the second control channel;

a multiplier for multiplying and normalizing an accumulated value of the signal power of the first control channel by the threshold value;

a comparator for comparing the integrated value of the signal power of the first control channel and the integrated value of the signal power of the second control channel, which have been normalized, and generating a plurality of advance/delay signals to control sampling times of fingers of control channels and data channels;

an OR gate module for receiving the plurality of advance/retard signals and clearing the first accumulator and the second accumulator.

4. The system of claim 3, wherein the data channel is a dedicated physical channel.