HK1122399B - Electromigration-resistant and compliant wire interconnects, nano-sized solder compositions, systems made thereof, and methods of assembling soldered packages - Google Patents

Description

Electromigration resistant and compliant wire interconnect, nano-solder composition, system made therefrom, and method of assembling a soldered package

RELATED APPLICATIONS

This patent application claims priority from U.S. application No. 11/173939 filed on 30.6.2005, which is incorporated herein by reference.

Technical Field

The disclosed embodiments relate to nano-sized solder paste compositions for microelectronic device packaging.

Background

Integrated Circuit (IC) dies are often fabricated into processors for various tasks. IC operational problems cause heat generation and thermal expansion stresses in the die package. High melting point solders, while withstanding the high operating temperatures caused by dense circuitry in the die, require high processing temperatures, which can result in high thermal-mechanical stresses due to Coefficient of Thermal Expansion (CTE) mismatches between the semiconductor die and the organic substrate. However, with low melting point solders, electromigration is more likely to occur. In addition, corrosion may occur between the two dissimilar metals of the solder bump and the bond pad.

Drawings

In order to understand the manner in which embodiments are obtained, a more particular description of various embodiments is provided by reference to the accompanying drawings. Understanding that these drawings depict only typical embodiments that are not necessarily drawn to scale and are not therefore to be considered to be limiting of its scope, some embodiments will be described and explained with additional specificity and detail through the use of the accompanying drawings, in which:

fig. 1A is a cross-section of a microelectronic device during processing according to an embodiment;

FIG. 1B is a cross-section of the microelectronic device shown in FIG. 1A after further processing;

FIG. 1C is a cross-section of the microelectronic device shown in FIG. 1B after further processing;

FIG. 1D is a cross-section of the microelectronic device shown in FIG. 1C after further processing;

FIG. 1E is a cross-section of the microelectronic device shown in FIG. 1D after further processing;

FIG. 1F is a cross-section of the microelectronic device shown in FIG. 1C after further processing according to an embodiment;

FIG. 2 is a computer image cross-sectional detail of the nano-solder paste composite shown in FIG. 1C, according to one embodiment;

FIG. 3A is a cross-section of an interconnect template during processing according to one embodiment;

FIG. 3B is a cross-section of the interconnect template shown in FIG. 3A after further processing according to one embodiment;

FIG. 4 is a cross-section of an interconnect template during processing according to one embodiment;

FIG. 5 is a cross-section of an interconnect template during processing according to one embodiment;

FIG. 6 is a cross-section of a package according to an embodiment;

FIG. 7 is a cross-section of a package according to an embodiment;

FIG. 8 is a process flow diagram according to various embodiments; and

FIG. 9 is an illustration of a computing system, according to an embodiment.

Detailed Description

The following description includes terms, such as upper, lower, first, second, etc., that are used for descriptive purposes only and are not to be construed as limiting. Embodiments of a device or article described herein can be manufactured, used, or shipped (ship) in a number of positions and orientations. The terms "die" and "chip" generally refer to a physical object that is the basic workpiece that is transformed by various process operations into the desired integrated circuit device. The die is typically singulated from a wafer, and the wafer may be made of semiconductor, non-semiconductor, or a combination of semiconductor and non-semiconductor materials. The backplane (board) is typically a resin-impregnated fiberglass structure that serves as the mounting substrate for the die.

One embodiment relates to wire interconnects embedded in nanosolder. The nanosolder is produced from a solder paste containing metal particles having diameters ranging from about 2 nanometers (nm) to about 50 nm. Thereafter, the solder paste is reflowed and results in cured particles ranging in size from about 50 nanometers (nm) to about 20 micrometers (μm). One embodiment includes a wire interconnect and a nanosolder that are substantially the same metal. "substantially the same metal" is intended to mean substantially the same chemical composition of the metal or alloy. Accordingly, one embodiment includes a method of operating a device at a current density allowed by the presence of a nano-solder and a wire interconnect of substantially the same metal. In one embodiment, the current density that can be maintained for the device is up to 10⁶amp/cm²。

Referring now to the drawings, wherein like structures are provided with like reference numerals. In order to best explain the embodiments of the structure and process, the drawings contained herein are diagrammatic representations of embodiments. Thus, the actual appearance of the fabricated structures, for example in a photomicrograph, may appear different while still incorporating the basic structures of the embodiments. Furthermore, the drawings only show the structures necessary for understanding the embodiments. Other structures known in the art have not been included to maintain the clarity of the drawings.

Fig. 1A is a cross-section of a microelectronic device 100 during processing according to an embodiment. The substrate 110, which may be a die of a processor, for example, includes bond pads 112 for electrical communication from the substrate 100 to the outside world. The microelectronic device 100 is shown as being processed with a patterned mask 114 that exposes the bond pads 112.

In one embodiment, the bond pad 112 is a copper metallization upper layer that can contact any of several metallization layers. For example, a metallization layer such as metal one (M1, not shown) in the microelectronic device makes electrical contact with the bond pad 112. In another example, a metallization layer such as metal two (M2, not shown) makes electrical contact with the bond pad 112. M2 makes electrical contact with M1. In another example, a metallization layer, such as metal three (M3, not shown), makes electrical contact with the bond pad 112. M3 makes electrical contact with M2, and M2 makes electrical contact with M1. In another example, a metallization layer such as metal four (M4, not shown) makes electrical contact with the bond pad 112. M4 makes electrical contact with M3. M3 makes electrical contact with M2, and M2 makes electrical contact with M1. In another example, a metallization layer, such as metal five (M5, not shown), makes electrical contact with the bond pad 112. M5 makes electrical contact with M4. M4 makes electrical contact with M3. M3 makes electrical contact with M2, and M2 makes electrical contact with M1. In another example, a metallization layer such as metal six (M6, not shown) makes electrical contact with the bond pad 112. M6 makes electrical contact with M5. M5 makes electrical contact with M4. M4 makes electrical contact with M3. M3 makes electrical contact with M2, and M2 makes electrical contact with M1. In another example, a metallization layer such as metal seven (M7, not shown) makes electrical contact with the bond pad 612. M7 makes electrical contact with M6. M6 makes electrical contact with M5. M5 makes electrical contact with M4. M4 makes electrical contact with M3. M3 makes electrical contact with M2, and M2 makes electrical contact with M1. It will become apparent from this disclosure that various semiconductor substrate structures may be adapted for use in various embodiments.

Fig. 1B is a cross-section of the microelectronic device 101 shown in fig. 1 after further processing. According to various embodiments set forth in the present disclosure, the patterned mask 114, which in one embodiment is a patterned photoresist, has been filled with a nanoparticle solder paste 116, such as a nanoparticle solder paste powder 116.

In one embodiment, the nanoparticle solder paste 116 includes a volatile binder and flux vehicle for the nanoparticle solder paste 116 in the process. In one embodiment, the molding itself is not performed, but rather a nano-particle (hereinafter nano-solder) solder paste of solder is formed evenly (solder for) and during heating to a sufficient temperature, the solder carrier liquefies and preferentially wets the bond pads 112 and preferentially becomes shielded from the substrate 110, i.e., it does not wet the substrate 110 as it does to wet the bond pads 112. The substrate 110 may be a semiconductor, a dielectric, and combinations thereof.

Fig. 1C is a cross-section of the microelectronic device 102 shown in fig. 1B after further processing. In this embodiment, the molding mask 114 has been removed. Removal of the patterned mask 114 can be performed by pulling it away from the substrate 110, thereby leaving the nano-solder paste 116 formed as discrete islands directly over the bond pads 112.

Fig. 2 shows an enlargement of a portion of the microelectronic device shown in fig. 1C. Fig. 2 is taken from the area in dashed line 2 shown in fig. 1C. Fig. 2 shows a metal particle composition precursor (precursor) as the metal particle composition 218 in the solder paste matrix 220. The metal particle composition 218 includes one of the metal particle composition embodiments set forth in this disclosure. Because the solder paste matrix 220 substantially prevents the metal particle composition 218 from being affected by corrosion and/or oxidation, the metal particle composition 218 may prevent significant grain growth during reflow. In one embodiment, the metal particle composition 218 after reflow has a particle size ranging from about 50nm to less than or equal to about 20 μm.

In one embodiment, the metal particle composition 218 includes particles having a size ranging from about 2nm to 50 nm. In one embodiment, the metal particle composition 218 includes particles having a size ranging from about 10nm to about 30 nm. In one embodiment, the metal particle composition 218 includes particles having a size in a range of 98% less than or equal to about 20 nm.

Due to the embodiment of particle size, nucleation of the metal particles of the metal particle composition causing the transition from solid to solidus can begin at about 400 ℃ or below. For example, gold may encounter a solid-to-solidus (solid-to-solid) transition at about 300 ℃.

In one embodiment, the metal particle composition 218 includes a melting temperature equal to or less than about 400 ℃. Depending on the metal type and particle size, the metal particle composition 218 may have a melting temperature variation of several hundred degrees. For example, solid gold has a melting temperature of about 1064 ℃. When gold is formed into the nanoparticles described herein, the melting temperature can be lowered to about 300 ℃.

In one embodiment, the metal particle composition 218 includes a first metal having a particle size in a range of less than or equal to about 20nm, and the first metal is present alone as a pure metal or as a macroscopically monophasic alloy. In one embodiment, the metal particle composition 218 includes silver (Ag). In one embodiment, the metal particle composition 218 includes copper (Cu). In one embodiment, the metal particle composition 218 includes gold (Au). In one embodiment, the metal particle composition 218 includes a gold-tin alloy (Au80Sn 20). In one embodiment, the metal particle composition 218 includes tin (Sn). In one embodiment, the metal particle composition 218 includes a combination of at least two of the above metal particle compositions. In one embodiment, the metal particle composition 218 includes a combination of at least three of the above-described metal particle compositions.

In one embodiment, the metal particle composition 218 includes an Au80Sn20 solder alloy including Au as a core result and Sn as a shell structure. In one embodiment, the first metal comprises silver and the shell structure is selected from copper, gold, lead and tin. In one embodiment, the core structure comprises gold and the shell structure is selected from copper, silver, lead and tin. In one embodiment, the core structure comprises lead and the shell structure is selected from copper, silver, gold and tin. In one embodiment, the core structure comprises tin and the shell structure is selected from copper, silver, gold and lead. In one embodiment, any of the above core structure and shell structure metal particle compositions includes a core structure present in a larger amount than a shell structure.

In one embodiment, the core structure has a first melting temperature and the shell structure has a second melting temperature that is lower than the first melting temperature. In this embodiment, the core structure may be gold and the shell structure may be tin.

In one embodiment, the metal particle composition 218 is a core and multi-shell structure. In one embodiment, the metal particle composition includes a first portion and a second portion, but the structure is more heterogeneous in agglomeration than the core-shell structure.

Fig. 3A is a cross-section of an interconnect template 300 during processing according to one embodiment. The interconnect substrate 322 is prepared with a plurality of vias, one of which is designated with reference numeral 324. In one embodiment, the interconnect substrate 322 is an interlayer dielectric layer (ILD) material, such as a polyimide material. Processing of the interconnect template 300 includes forming interconnects in the vias 324.

In one embodiment, the interconnect substrate 322 is patterned using a mask (not shown), and the plurality of vias (via)324 are formed by a process such as etching using a mask, or a laser is passed through a mask to simultaneously form the vias 324 and pattern the mask. Other processes for forming the vias 324 may be included, such as a punching process.

In one embodiment, the via 324 is prepared by forming a seed layer 326 in the via 324. The mask, when present, prevents deposition of the seed layer anywhere outside of the via 324. In one embodiment, the seed layer 326 is formed by Chemical Vapor Deposition (CVD) of a seed material. For example, where the interconnect is to be copper, the CVD copper process is conducted under plasma conditions to form the seed layer 326 in the electrolytic deposition of copper to prepare the filled vias 324. In one embodiment, tilted Physical Vapor Deposition (PVD) is performed on both sides of the via 324 such that the seed layer 326 is deposited substantially uniformly along the via 324. Where a PVD process is used to form the seed layer 326, the mask may thereafter be removed by rinsing with a mask solvent or other suitable conventional mask removal process.

Fig. 3B is a cross-section of the interconnect template shown in fig. 3A after further processing according to one embodiment. The interconnect substrate 322 includes a seed layer 326 disposed in the via 324 in preparation for further processing. In one embodiment, the via 324 has been filled by electroplating of a wire interconnect 328 over the seed layer 326 in the via 324.

In one embodiment, each wire interconnect 328 has a thickness ranging from about 20 μm to about 106 μm. In one embodiment, wire interconnect 328 has a thickness of about 40 μm. The interconnect thickness may include a seed layer 326.

Compliant interconnects may be implemented by forming interconnects that can be bent (i.e., compliant) without breaking the connection to the solder bumps. Compliant interconnects may be implemented by using substantially the same metal for both structures. Compliant interconnects may also be implemented by employing a high-to-width aspect ratio in combination with substantially the same metal for both structures. In one embodiment, wire interconnect 328 has a height-to-width aspect ratio ranging from about 0.5: 1 to about 5: 1. In one embodiment, wire interconnect 328 has a height-to-width aspect ratio ranging from about 1: 1 to about 4: 1. In one embodiment, wire interconnect 328 has a height to width aspect ratio ranging from about 2: 1 to about 3: 1. In one embodiment, wire interconnect 328 has a height to width aspect ratio of about 3.5: 1.

Fig. 4 is a cross-section of an interconnect template 400 during processing according to one embodiment. In one embodiment, the interconnect template 400 includes an interconnect substrate 422 and a wire interconnect 428. In this embodiment, the wire interconnect 428 is a wire that has been filled into the interconnect template 422 by physically inserting the wire interconnect 428 into the via 424. In one embodiment, electroplating is performed by first electroless plating into the via 424, followed by electroplating to fill the via 424.

Fig. 5 is a cross-section of an interconnect template 500 during processing according to one embodiment. The interconnect substrate 522 is prepared using a plurality of vias, one of which is designated with reference numeral 524. In one embodiment, the interconnect substrate 522 is an interlayer dielectric layer (ILD) material, such as a polyimide material. In this embodiment, the wire interconnect 528 is a wire that has been filled into the interconnect template 522 by physically inserting the wire interconnect 528 into the via 524. In one embodiment, via 524 has been filled by electroplating of wire interconnect 528.

Processing has achieved a wire interconnect 528 in an interconnect substrate 522 having an upper surface 521 and a lower surface 523. The wire interconnect 528 extends at least one of above and below the interconnect substrate 522. In one embodiment, interconnect substrate 522 is etched back to expose interconnect 528.

Fig. 1D is a cross-section of the microelectronic device 103 shown in fig. 1C after further processing. The substrate 110, the bond pads 112, and the nano-solder paste 116 are brought into contact with a wire interconnect 128, such as a wire interconnect 528 disposed in the interconnect template 500 shown in fig. 5. In one embodiment, the wire interconnect 128 includes silver. In one embodiment, the wire interconnect 128 comprises copper. In one embodiment, the wire interconnect 128 comprises gold. In one embodiment, the wire interconnect 128 includes gold-tin alloy Au80Sn 20. In one embodiment, the wire interconnect 128 includes tin. In one embodiment, the wire interconnect 128 includes a combination of the above-described metals and alloys. In one embodiment, any of the wire interconnect embodiments set forth in this disclosure are brought into contact with the nano-solder paste 116.

In one embodiment, the nano-solder paste 116 includes a flux carrier that is mixed with the solder paste during processing. In one embodiment, the flux carrier is activated in the solder paste 116 during heating. In one embodiment, the flux carrier is a sulfonamide that activates at or above about 150 ℃. In one embodiment, the flux may be activated at a lower temperature, for example, from about 100 ℃ to about 300 ℃.

Fig. 1E is a cross-section of the microelectronic device 104 shown in fig. 1D after further processing. The reflow process has begun, during which time the solder paste matrix, such as the solder paste matrix 220 shown in fig. 2, has volatilized and the metal particle composition, such as the metal particle composition 218, has reflowed into the solder bumps 117, having a particle size ranging from about 50nm to less than or equal to about 20 μm. The reflow process described for coupling the substrate 110 to the wire interconnects 128 may be performed prior to the method of assembling the microelectronic device package. In one embodiment, the process can be performed simultaneously with other thermal treatments of the microelectronic device package. In one embodiment, the process may be performed after assembling certain elements of the microelectronic device package, including forming a metal particle composition die attach embodiment. These and other embodiments are discussed subsequently.

Fig. 1F is a cross-section of the microelectronic device 105 shown in fig. 1D after further processing. In one embodiment, the interconnect substrate 122 is a material that can be dissolved after the wire interconnect 128 is soldered in place. In one embodiment, the interconnect substrate 122 is a low-k dielectric material that may be used as an underfill material. In one embodiment, the interconnect template 122 may be softened during reflow of the solder bumps 117.

In one embodiment, the bond pads 112 have a substantially square footprint and an edge dimension of approximately 106 μm. In one embodiment, the pitch of two adjacent bond pads 112 is approximately 175 μm. The interconnect substrate template 122 is configured to substantially mate with a given substrate having a bond pad width and pitch matching configuration.

The microelectronic device 105 includes a mounting substrate 130 coupled to the substrate 110 by wire interconnects 128 and reflowed solder bumps 117. In one embodiment, the mounting substrate 130 is a second level substrate having mounting substrate bond pads 132 and mounting substrate solder bumps 134. In one embodiment, the mounting substrate solder bump 134 is substantially the same metal or alloy as the wire interconnect 128, and it may be a reflowed nanosolder. Thus, significant electromigration is eliminated because the material of the solder bump and the wire interconnect are substantially the same metal or alloy. Similarly, thermal mismatch is substantially eliminated because the material of the reflowed nanosolder bump and the wire interconnect are substantially the same metal or alloy.

Fig. 6 is a cross-section of a package 600 according to an embodiment. The substrate 610, which may be a die of a processor, for example, includes bond pads 612 for electrical communication from the substrate 610 to the outside world. In one embodiment, the bond pad 612 is a copper metallization upper layer that can contact any of several metallization layers. The reflowed nanosolder bumps 617 are bonded to the substrate 610 and to the wire interconnects 628 according to various embodiments set forth in the present disclosure.

In one embodiment, each of the wire interconnects 628 has a thickness ranging from about 20 μm to about 106 μm. In one embodiment, the wire interconnect 628 has a thickness of about 40 μm. In one embodiment, the wire interconnects 628 have a height-to-width aspect ratio ranging from about 0.5: 1 to about 5: 1. In one embodiment, the wire interconnects 628 have a height-to-width aspect ratio ranging from about 1: 1 to about 4: 1. In one embodiment, the wire interconnects 628 have a height-to-width aspect ratio ranging from about 2: 1 to about 3: 1. In one embodiment, the wire interconnects 628 have a height to width aspect ratio of about 3.5: 1.

Package 160 includes a mounting substrate 630 in communication with substrate 610 through mounting substrate bond pads 632. The mounting substrate bond pads 632 are soldered to the wire interconnects 628 having mounting substrate solder bumps 634. The mounting substrate solder bump 634 may also be produced from reflowed nanosolder according to any of the embodiments set forth in the present disclosure.

In one embodiment, the mounting substrate 630 is a second level substrate, such as an interposer (interposer) of a processor. The mounting substrate 630 is also raised with a backplane bump (bump)636 for mounting to a backplane, such as a motherboard.

Fig. 7 is a cross-section of a microelectronic device 700 during processing according to an embodiment. The apparatus 700 includes a die 710 including a plurality of die bond pads 712. The reflowed nanosolder bump 717 couples the die 710 to other electrical connections. The apparatus 700 further includes a wire interconnect 728 according to any of the wire interconnect embodiments set forth in this disclosure. The wire interconnect 728 is coupled with the mounting substrate 730 by a reflowed solder bump 717 produced from a nano-solder paste according to any of the nano-solder paste embodiments set forth in this disclosure.

In one embodiment, the device 700 includes a backplane bump 736 and a backplane 738, such as a motherboard. In one embodiment, die 710 is bonded to a heat sink 742, such as an integrated heat spreader (HIS), by a thermal interface 740. An interconnect template 722 is also illustrated according to one embodiment. The interconnect template 722 is shown also acting as an underfill material that can be converted and reflowed to protect the electrical connections between the die 710 and the mounting substrate 730.

The bump embodiments set forth in this disclosure may also be applicable to wire bonding techniques. When the melting point starts in the range of about 400 ° or less, the wire bonding process may be performed under the condition that the thermal equilibrium of the wire bonding apparatus is maintained. Furthermore, the bonding wire may be substantially the same metal or alloy as the nano-solder composition.

Fig. 8 is a process flow diagram 800 according to various embodiments. The processing of the nano-solder paste is performed during the formation of the die attach and/or solder bump, respectively, and during the method of assembling the packaged die.

At 810, a nano-solder paste embodiment is patterned on a substrate according to any of the embodiments set forth herein.

At 820, a wire interconnect is formed in an interconnect template according to any of the embodiments set forth herein. Between 810 and 820, the process may cycle in either direction; through 811 or 821.

At 830, the nanosolder composition is reflowed on the substrate. By way of illustration in fig. 1E, reflowed nanosolder-derived bumps 117 are shown as forming metal components at a significantly lower temperature than the melting temperature of the individual metals as macroscopic bulk materials. At 831, the process flow may continue from the process of reflowing the nanoparticle solder paste to a method of assembling the die into a package. At 832, one process embodiment completes.

Optionally, in the wire-bonding technique, the process of molding the nanoparticle solder paste powder on the die is performed sequentially during the placement of the wire-bonded solder bumps to the die.

At 840, the die including the solder or nanoparticle solder paste is assembled into a package. By way of illustration, fig. 6 shows an assembly of a die 610 having at least one mounting substrate 630. At 841, the process flow may continue from the method of assembling the die into a package, followed by a process of reflowing the nanosolder composition into a solder bump. At 842, one method embodiment is complete.

FIG. 9 is an illustration of a computing system 900, according to an embodiment. One or more of the above-described embodiments of the metal particle composition, the die-attach composition, and/or the solder bump composition may be used in a computing system, such as computing system 900 of fig. 9. Any embodiment, alone or in combination with any other embodiment, is hereinafter referred to as a metal particle composition embodiment.

The computing system 900 includes at least one processor (not shown), for example, enclosed in a package 910, a data storage system 912, at least one input device, for example, a keyboard 914, and at least one output device, for example, a monitor 916. Computing system 900 includes a processor that processes data signals and may include, for example, a microprocessor available from Intel Corporation. In addition to the keyboard 914, the computing system 900 may include another user input device, such as a mouse 918. The computing system 900 may correspond to any of the structures that include reflowed nanosolder or wire interconnects with reflowed nanosolder. Accordingly, package 910 (including the die) and backplane 920 may include these structures.

For purposes of this disclosure, a computing system 900 incorporating components in accordance with the claimed subject matter may include any system employing a microelectronic device system, for example, may include at least one of the reflowed nanosolder embodiments coupled with a data storage device such as Dynamic Random Access Memory (DRAM), polymer memory, flash memory, and phase change memory. In this embodiment, the reflowed nanosolder embodiment is coupled to any combination of these functionalities by being coupled to a processor. However, in one embodiment, the reflowed nanosolder composition embodiments set forth in this disclosure are coupled to any of these functionalities. For one example embodiment, the data storage device includes an embedded DRAM cache on a die. Additionally, in one embodiment, the reflowed nanosolder composition embodiment(s) coupled to a processor (not shown) is a component of a system having reflowed nanosolder composition embodiments coupled to a data storage device of a DRAM cache. Additionally, in one embodiment, a reflowed nanosolder composition embodiment is coupled to the data storage device 912.

In one embodiment, the computing system may also include a die that includes a Digital Signal Processor (DSP), a microcontroller, an Application Specific Integrated Circuit (ASIC), or a microprocessor. In this embodiment, the reflowed nanosolder composition embodiment is coupled to any combination of these functionalities by being coupled to a processor. For an example embodiment, a DSP (not shown) is part of a chipset that may include a stand-alone processor (in package 910) and the DSP is part of the chipset on the backplane 920. In this embodiment, a reflowed nanosolder composition embodiment is coupled to the DSP, and there may be a separate reflowed nanosolder composition embodiment coupled to the processor in the package 910. Additionally, in one embodiment, the reflowed nanosolder composition embodiment(s) are coupled to a DSP mounted on the same board 920 as the package 910. It may now be appreciated that in connection with reflowed nanosolder composition embodiments as set forth by the various embodiments of the present disclosure and their equivalents, reflowed nanosolder composition embodiments may be combined as set forth with respect to computing system 900.

The reflowed nanosolder composition embodiments set forth in this disclosure may be applicable to devices and apparatuses other than conventional computers. For example, the die may be packaged with a reflowed nanosolder composition embodiment and disposed in a portable device such as a wireless communicator or a handheld device such as a personal data assistant. Another example is a die that may be packaged and disposed in a vehicle such as an automobile, locomotive, watercraft, aircraft, or spacecraft using the reflowed nanosolder composition embodiments.

In another embodiment, the operation of the computing system 900 is performed with current densities that would otherwise be detrimental to conventional block and wire interconnect structures. In one embodiment, the operation of computing system 900 employs approximately 10³amp/cm²And about 10⁶amp/cm²Current density in between. In one embodiment, the operation of computing system 900 employs approximately 10⁴amp/cm²And about 10⁶amp/cm²Current density in between. In one embodiment, the operation of computing system 900 employs approximately 10⁵amp/cm²And about 10⁶amp/cm²Current density in between. In one embodiment, the operation of computing system 900 is adapted to be greater than 10⁶amp/cm²But below a current density that would cause the particular material of the wire interconnect and reflowed nanosolder bump to reach solidus.

The "abstract" is provided in accordance with 37c.f.r. § 1.72(b), which requires an abstract that allows the reader to quickly ascertain the nature and gist of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

In the foregoing detailed description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments of the invention require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate preferred embodiment.

It will be readily understood by those skilled in the art that various other changes in the details, materials, and arrangements of the parts and method stages which have been described and illustrated in order to explain the nature of this invention may be made without departing from the principles and scope of the invention as expressed in the subjoined claims.

Claims (21)

1. A wire interconnect article comprising:

a solder bump disposed on the bond pad, wherein the solder bump comprises a first metal having a particle size in a range from about 50 nanometers to about 20 micrometers; and

a wire interconnect in contact with the solder bump, the wire interconnect comprising substantially the same metal as the first metal.

2. The wire interconnect article of claim 1, wherein the wire interconnect has a thickness ranging from about 20 to about 106 microns.

3. The wire interconnect article of claim 1, wherein the wire interconnect has a thickness from about 40 microns.

4. The wire interconnect article of claim 1, wherein the wire interconnect comprises a composite of a seed layer shell and a plated core.

5. The product of wire interconnects of claim 1, wherein the wire interconnects have an aspect ratio of between about 0.5: 1 and 5: 1.

6. The wire interconnect product of claim 1, further comprising a wire template encasing said wire interconnect.

7. The wire interconnect article of claim 1, wherein the wire interconnect is a metal or alloy selected from the group consisting of silver, copper, gold-tin alloy Au80Sn20, tin-silver, and combinations thereof.

8. A process for forming a wire interconnect product, comprising:

forming a nanoparticle solder paste on a substrate;

contacting the nanoparticle solder paste with a wire interconnect, the nanoparticle solder paste comprising a metal that is substantially the same metal as the wire interconnect; and

reflowing the nanoparticle solder paste to form a wire interconnect product.

9. The process of claim 8, wherein the nanoparticle solder paste comprises an average particle size ranging from about 2nm to about 50 nm.

10. The process of claim 8, wherein reflowing is performed at a reflowed first temperature, after which the solder bumps have a reflowed second temperature greater than the reflowed first temperature.

11. The process of claim 8, further comprising:

forming the wire interconnect in a support, wherein the step of forming the wire interconnect is selected from the following steps: plating the wire interconnect in the standoff via, inserting the wire interconnect into the standoff via, and combinations thereof.

12. The process of claim 8, further comprising:

the solder bump and wire interconnect product is coupled to a substrate selected from the group consisting of a first level mounting substrate, a second level mounting substrate, a package, a motherboard, and combinations thereof.

13. A method of assembling a microelectronic device package, comprising:

forming a solder precursor on the die active surface, wherein the solder precursor comprises a first metal having a particle size in a range of less than or equal to about 20nm contained therein, and the solder precursor comprises a melting temperature of equal to or less than about 400 ℃; and

coupling the die to a mounting substrate.

14. The method of assembling a microelectronic device package according to claim 13, further comprising:

reflowing the solder precursor, selected from the following steps: reflowing before coupling the die, reflowing during coupling the die, reflowing after coupling the die, and combinations thereof.

15. The method of assembling a microelectronic device package according to claim 13, further comprising:

an integrated heat spreader is connected to the die.

16. A method of operating a microelectronic device, comprising:

passing an electrical current through a solder bump and wire interconnect product, wherein the electrical current is in the range of a solder bump and a microelectronic device, the microelectronic device comprising a solder bump disposed on a bond pad, the solder bump comprising a first metal having a particle size in the range of from 50 nanometers to about 20 micrometers, a wire interconnect in contact with the solder bump.

17. The method of claim 16, wherein the solder bump and wire interconnect product are in contact with a die bond pad, and wherein the current density is at 10³amp/cm²And 10⁶amp/cm²In the meantime.

18. The method of claim 16, wherein the solder bump and wire interconnect product are in contact with a die bond pad, and the current density is at 10³amp/cm²And 10⁶amp/cm²And passing a current through the solder bump comprises operating the processor as a microelectronic device.

19. A microelectronic system, comprising:

a microelectronic die disposed on the mounting substrate;

a solder bump coupling the microelectronic die to the mounting substrate, the solder bump comprising:

a first metal having a particle size in a range from about 50 nanometers (nm) to less than or equal to about 20 micrometers (μm), and the solder composition comprises a melting temperature equal to or less than about 400 ℃; and

a dynamic random access data storage device coupled with the die.

20. The microelectronic system of claim 19, wherein said system is disposed in one of: computers, wireless communicators, hand-held devices, automobiles, locomotives, airplanes, boats, and spacecraft.

21. The microelectronic system of claim 19, wherein said microelectronic die is selected from the group consisting of data storage devices, digital signal processors, microcontrollers, application specific integrated circuits, and microprocessors.