HK1129143A - A method and system related to implementing information of satellite signal received from several kinds of satellite system - Google Patents

Description

Method and apparatus for performing signal correlation for satellite signals received from multiple satellite systems

Technical Field

The present invention relates to signal correlators for digital signal receivers, and more particularly, to a method and apparatus for performing signal correlation for signals received from satellites in a variety of satellite systems, such as Global Positioning System (GPS) satellites and galileo system satellites.

Background

Global Navigation Satellite Systems (GNSS) utilize satellite signals from Global Positioning System (GPS) satellites and galileo system satellites to determine position using satellite signals from either system. However, satellite signal receivers are typically designed to receive satellite signals from a satellite system, such as the global positioning system or the galileo system, but not both. Thus, the receiver must wait for at least four visible GPS satellites to provide a signal strong enough for the satellite signal receiver to acquire the signal. A constellation of 24 GPS satellites is generally sufficient for users to determine their location in outdoor areas, for example, 4 to 8 satellites are generally visible to a receiver. But when the GPS receiver is operated in a region where trees, mountains, or buildings block the view of the sky, the receiver will not be able to determine the exact location, or will not operate at all.

In order for a GNSS receiver to receive satellite signals at low signal amplitudes, assistance information is sent to the receiver enabling the receiver to acquire and track the signals. The aiding information includes satellite orbit information, timing synchronization information, doppler frequency information, etc. GNSS receivers typically have correlation circuits (correlation circuits) that locate and track correlation peaks of received satellite signals. The aiding information is used to help the correlator circuit identify the appropriate code phase and frequency estimates to use for acquiring and tracking the satellite signals.

The correlator circuits between the galileo receiver and the GPS receiver are different since each GNSS system uses a different modulation method. For example, GPS satellites transmit pseudorandom noise (PRN) modulated signals using 1023 chips of repetition in 1 millisecond, while galileo systems use 4092 chips in 4 milliseconds, but also add a Binary Offset Carrier (BOC) code that "spreads" the signal to twice the GPS signal bandwidth, i.e., 4092 bit PRN codes are modulated with binary signals at twice the PRN code rate.

Due to the differences in these signals, receivers for GPS signals and galileo signals are incompatible. Thus, to generate an accurate position, a receiver designed for a single satellite system must have sufficiently strong signals from four satellites in the satellite system. In certain situations, this is not possible and the receiver will either not be able to calculate the position or it will take a long time to calculate the position. As another alternative, the receiver has a correlator circuit dedicated to each satellite system; this doubles the size of the circuitry in the receiver.

Accordingly, there is a need for an improved satellite signal receiver that can acquire satellite signals from a variety of satellite systems using a common correlator circuit.

Disclosure of Invention

The present invention provides a method and apparatus for correlating satellite signals received from a plurality of satellite systems. The method and apparatus provide a plurality of channels, each of which is capable of receiving and processing satellite signals from a plurality of satellite systems. In one embodiment, each channel is capable of receiving signals from GPS satellites and/or Galileo satellites. With partial correlation (partial correlation) techniques, a correlator in each channel computes a full convolution between an input signal (e.g., a GPS signal or a galileo signal) and a pseudorandom noise (PRN) code reference.

Drawings

For the present invention to be more readily understood, the following detailed description of the invention is provided in conjunction with the accompanying drawings, in which:

FIG. 1 is a spectral diagram of a BOC modulated pseudo-random noise signal forming a Galileo satellite signal;

FIG. 2 is a graph comparing an autocorrelation function of a Galileo signal using full correlation with an autocorrelation function produced by a "filtered" Galileo signal;

FIG. 3 is a block diagram of a GPS receiver that constitutes the present invention;

FIG. 4 is a schematic diagram of a tuner for receiving both GPS signals and Galileo signals;

FIG. 5 is a waveform diagram produced by FIG. 1 when receiving GPS signals;

FIGS. 6A and 6B are flow charts of methods of operation of the embodiment of the present invention of FIG. 3;

FIG. 7 is a diagram illustrating an example of calculating a full convolution using a conventional method;

FIG. 8 is a schematic diagram of a method of calculating a full convolution using the present invention;

FIG. 9 is an embodiment of a code lookup apparatus suitable for use with the invention of FIG. 3;

FIG. 10 is an embodiment of a two-dimensional code shift register suitable for use in the alternate embodiment of the present invention of FIG. 3;

FIG. 11 is a block diagram of a GNSS receiver that may comprise another embodiment of the present invention;

FIG. 12 is a waveform diagram of accumulated magnitude in high resolution mode;

FIG. 13 is an embodiment of a code lookup apparatus suitable for use in FIG. 11;

FIG. 14 is a flow chart of a method of operation of the embodiment of the invention of FIG. 11.

Detailed Description

There are some differences between GPS signals and galileo signals that must be processed by a GNSS receiver. First, the binary offset carrier frequency (BOC) code is used by the Galileo system, but not by the GPS system. The BOC code is a binary signal with a code rate twice the PRN code rate to remodulate the signal to form a dual lobe signal that is empty in the center of the GPS signal spectrum. Each lobe has a similar bandwidth as the GPS signal. In order for the correlation circuitry of a dual system GNSS receiver to be able to process both galileo signals and GPS signals, the BOC code must be removed or compensated. The galileo signal uses the L1F signal (L1 band RF signal) to carry two sub-channels (L1B and L1C components), the L1B sub-channel carries the data component (navigation data is sent at 250 symbols per second using BOC modulated 4096 chip spreading codes), and the L1C sub-channel carries the pilot component (secondary codes are transmitted at 25 bits/epoch using BOC modulated 4096 chip spreading codes). In the final Galileo system design, the secondary code may not be used. The receiver 100 may tune to one of these sub-channels or process them. The repeating Galileo PRN code for the two sub-channels is four times as long as the GPS code, i.e., 4096 chips repeated every 4 milliseconds versus 1023 chips repeated every 1 millisecond. The code used for each subchannel is different. The Galileo PRN code is currently undefined and thus the receiver must have a mechanism to update the code used.

Another aspect of galileo signals requires attention. The data has a bit length equal to one epoch (epoch) length of the Galileo PRN code. Thus, a bit may invert the code after each epoch, which limits the coherent integration period of the Galileo signal to one epoch. To achieve a longer coherent integration period, the effect of the PRN code correlation on the data needs to be accounted for (this process is called "data erasure"). Once the data effects are removed, correlators can be used to coherently integrate PRN codes for multiple epochs. Furthermore, if a secondary code is used, it must be removed from the pilot channel in the same way that data is processed (erased). The data and secondary code are synchronized with each other and with the PRN code epochs, and like the data, the secondary signal also has a bit duration that is the same as the epoch length. Thus, the coherence length is limited to an epoch without erasing the secondary code.

FIG. 1 is a graph 100 of the frequency spectrum 102 of a BOC modulated pseudorandom noise (PRN) signal, like that transmitted by a Galileo satellite. The spectrum 102 has two main side lobes, an Upper Sideband (USB)104 and a Lower Sideband (LSB)106, and the dashed spectrum 108 represents the spectrum of the signal transmitted by the GPS satellites.

FIG. 2 is a graph 200 of an autocorrelation function (ACF)202 of Galileo satellite signals. Function 202 represents the autocorrelation function 204(ACF 204) of the entire signal, and function 206 represents the ACF of the USB (or LSB) only, i.e., the ACF of the "filtered" galileo signal. For comparison, the ACF 208 is shown with a dashed line of GPS signals. The unfiltered Galileo signal has a narrower (in time) ACF 204, e.g., about +/-0.4 chips, which requires better spacing than the correlation used to correlate a +/-1.0 chip GPS signal. By filtering the Galileo signals, their correlation response (correlation response) becomes similar to the GPS signals, allowing the correlation spacing to be the same when the GPS and Galileo signals are received.

In one embodiment of the invention, the dual system GNSS receiver of the invention utilizes the entire signal (ACF 204), in an alternative embodiment the receiver processes only one sideband (ACF 204), while in a further embodiment the GNSS receiver utilizes the signal sideband for signal acquisition and utilizes the entire signal during signal tracking. In all cases, the GNSS receiver of the present invention uses common correlation circuitry to process both GPS and Galileo signals. Each embodiment of the GNSS receiver is described below.

The present invention utilizes various schemes for each different point of the GPS/galileo signal to enable a single GNSS receiver to process both galileo and GPS signals. The first problem, the BOC code, can be handled by filtering the Galileo signal to produce the USB, LSB, or both prior to correlation, or by correlating the entire Galileo signal. The correlation may be calculated on the data component, the pilot component, or both. The second problem, code length, is solved by running the correlation circuitry at least 4 times faster than in GPS signal processing, assuming USB or LSB signal processing only. Alternatively, the receiver operates at the same rate as when processing GPS signals, but only correlates 1/4 for a possible delay of the galileo signal. The third problem, the undefined PRN code, is solved by using a random access memory to store the PRN code of the Galileo signal. Thus, changes in the code require small changes or updates to the memory. Such updates may be done by downloading, rather than actually changing the physical memory.

Fig. 3 shows a block diagram of a dual system Global Navigation Satellite System (GNSS) receiver 300 of the present invention. While a GNSS receiver is used as a platform in which the invention can be embodied, forming an application of the invention, other platforms that require correlation of signals from two different systems can also be used with the invention.

In one embodiment of the invention, the GNSS receiver 300 receives and processes satellite signals from at least two different satellite positioning systems. For example, in each channel of the receiver, signals from at least one GPS satellite and/or at least one galileo satellite may be processed using common circuitry.

Signals (e.g., GPS and/or galileo signals) are received by the antenna 301. A radio frequency to intermediate frequency converter (RF/IF converter) 302 filters, amplifies and frequency shifts the signal for digitization by an analog-to-digital converter (a/D) 303. The devices 301, 302 and 303 are substantially identical to those used in a conventional GPS or galileo receiver; however, the RF bandwidth of the system is approximately doubled in order to increase the spectral occupancy of the BOC modulated galileo signal.

Continuing with FIG. 3, the output of A/D303 is connected to a set of processing channels 304 implemented in digital logic₁、304₂...304_n(where n is an integer). Each processing channel 304_nSignals from GPS satellites or galileo satellites can be processed. The signal in a particular channel is digitally tuned by a tuner 305, driven by a Numerically Controlled Oscillator (NCO) 306.

Fig. 4 shows a block diagram of a tuner 305 capable of processing galileo signals and GPS signals. The tuner includes a pair of mixers 400 and 402, a quadrature splitter 404, a pair of filters 406 and 408, and a signal selector 410 (e.g., a 6:2 multiplexer or two 3:1 multiplexers). In operation, the NCO signal is coupled to the splitter 404,this applies a 0 degree phase shifted NCO signal to mixer 404 and a 90 degree phase shifted NCO signal to mixer 402. The result of mixing the NCO signal with the digital satellite signal is an in-phase component (I) and a quadrature component (Q). These I and Q components are filtered or unfiltered. In one embodiment of the invention, the USB filter 406 is used to select the USB portion (I) of the BOC modulated PRN signal_USB、Q_USB) For further processing. Alternatively, the LSB filters 410 and 412 may be used to select the LSB portion (I) of the signal_USB、Q_USB) For further processing. In a final embodiment, no filtering is performed and the I, Q component forms the output of tuner 305. When a GPS signal is received, no filtering process is applied and the signal is acquired as unfiltered I and Q signals. The signal selector 414 is used to select which signal is the output of the tuner.

Tuner 305 serves primarily two purposes. First, the remaining IF frequency components after RF/IF conversion are removed. Second, the satellite doppler frequency shift due to satellite motion, user motion, and reference frequency error is removed. In an assisted satellite positioning system receiver, the receiver is provided with almanac and/or ephemeris for both GPS and galileo satellites. In this way, the receiver 300 can determine the satellites that are in view of the receiver. Thus, an estimated initial Doppler value can be obtained using a Doppler shift estimate. Knowing which GPS and galileo satellites are in view enables the receiver to allocate appropriate channels to receive GPS or galileo satellites known to be in view even if doppler estimation is not available. If the receiver has no aiding information, the receiver channel performs a blind search (blind search) for GPS satellites and then for Galileo satellites, and vice versa.

The USB filter 406 (or LSB filter 408) is a composite filter centered on the upper lobe 104 of the spectrum 102. By filtering one sideband, the USB signal is a "Binary Phase Shift Keying (BPSK) -like" signal that can be processed (e.g., correlated) in the same manner as the GPS signal. The result of using one sideband is an approximately 3dB loss in signal strength, with a slight "rounding" of the correlation function, see fig. 2, ACF 206 and the bottom of the correlation function, which is 2-chip wide.

Once the signal is received using the correct frequency, the output of tuner 305 is a baseband signal consisting of an in-phase component (I) and a quadrature component (Q). As previously described, these components may or may not be filtered. Correlator circuits in the processing channel can be used for either GPS signals or galileo signals by filtering processes in the tuner to produce BPSK-like signals. When an unfiltered galileo signal is selected, which is not BPSK-like signal, a different processing than the GPS signal is required. In some examples, as discussed below, it is beneficial to use an unfiltered galileo signal. Although the selector 410 selects among three complex signals, in a particular receiver, the tuner will establish one sideband or the other. Thus, for example, the tuner has only one USB filter 406, i.e., LSB 408 is not required. In such an arrangement, the selector 410 is used to select the I and Q signals when the GPS signal is to be processed and to select the I signal when the Galileo signal is to be processed_USBAnd Q_USBA signal. If an unfiltered Galileo signal is to be processed, the selector 410 selects the I and Q signals and the receiver is tuned to the channel carrying the Galileo signal. Selector 410 is controlled by CPU 314. In one embodiment of the present invention, the selector 410 will select between the composite USB Galileo signal and the composite GPS signal.

Returning to fig. 3, decimation circuit 307 processes the output of tuner 305. The output of the decimation circuit 307 is a series of complex signal samples having a I, Q component, output at a rate that is exactly synchronized with the timing of the input signal. In one embodiment of the invention, the decimation operation is a simple pre-increment that sums all of the input signal samples during one output sample period. A Numerically Controlled Oscillator (NCO)308 is used to time the sampling process. For example, if P is 2, the code NCO 308 is set to produce 2 xf_sFrequency of (f) here_sIs f_o(PRN code chip rate for GPS/Galileo signals), is suitable for Doppler shifting. Note that if it is to be processed, it is not filteredGalileo signals of waves (with narrow autocorrelation function), the value of P is at least 4. The NCO adjusts to doppler shift based on external input from firmware instructions. Since the Doppler shift is not the same for each satellite, for each channel 304_nA separate code NCO 308 and decimation circuit 307 are required. It is noted that it is not required that the input sample rate be f_sInteger multiple because the code NCO 308 can generate arbitrary frequencies. If the decimation circuit 307 is a pre-adder, the number of samples added typically rotates between two values, so that the correct sample timing over the long term is maintained. For example, if the input sample rate is 10MHz and the desired sample rate is 2.046MHz, the pre-adder would add 4 or 5 samples, thus keeping the desired sample rate at an average level.

The decimation circuit 307 further comprises a quantizer (not shown) whose output reduces the number of bits of the signal component before further processing of the signal. In one embodiment of the invention, 2-bit quantization is used.

The signal samples from the decimation circuit 307 are connected to a convolution processor 309. The convolution processor 309 performs a partial correlation process (described below) on the I, Q component of the unfiltered galileo signal, the I, Q component of the upper or lower sideband of the galileo signal, or the I, Q component of the GPS signal. When correlating Galileo signals, correlation may be performed on the pilot component, the data component, or both. The convolution processor 309 generates partial correlation results to be accumulated in signal Random Access Memories (RAMs) 310a and 310 b. In particular, the RAMs 310a and 310b maintain a complex vector that integrates all or part of the full convolution between the input signal and a reference PRN code (e.g., a GPS PRN code, a Galileo PRN code, or a Galileo pilot code). The convolution result has a peak at a point corresponding to a high correlation between the signal and the reference. As will be discussed in detail below, the relative positions of these peaks for the various satellite signals are used to ultimately calculate positioning information.

The convolution processor 309 and signal RAMs 310a and 310b accumulate convolution results for multiple epochs of GPS signals, repeating over a nominal 1 millisecond interval. For example, if a 10 millisecond signal is processed, the values in RAM310a and 310b are the sum of multiple GPS correlation results (partial correlations) generated over at least one GPS epoch. Since Galileo signals have an epoch that is 4 milliseconds long, a 4 millisecond signal establishes a correlation result over one Galileo epoch. All individual correlation results have similar characteristics because the timing of the decimation operation ensures that samples are taken at the same instant in each epoch. Accumulating similar results from the correlations improves the signal-to-noise ratio and enhances the receiver's ability to detect weak signals. This process is called coherent integration, which, as will be discussed, can be combined with magnitude integration to generate an average of the correlation results over a period of seconds.

The length of time to perform the coherent integration interval is limited by a number of factors, including uncompensated doppler shift, satellite signal navigation data bits, and phase shift due to movement of the receiver 300. These factors introduce slow but seemingly random phase variations in the signal. These phase changes cause destructive interference that affects coherent integration over a period of tens of milliseconds. Thus, to achieve a long averaging interval, receiver 300 performs a second step of magnitude accumulation. Specifically, the signals stored in the signal RAMs 310a and 310b are periodically output to the complex normalizer 311, which generates complex magnitude values of the complex convolution vectors. The complex magnitude values are accumulated by adder 312 and stored in magnitude RAM 313. Each time the complex magnitude of the signal is calculated, the signal RAMs 310a and 310b are cleared to allow another coherent integration to occur. This process continues until the desired number of magnitude accumulations is complete. For example, when performing correlation on GPS signals, if the coherent averaging interval is 10 milliseconds and 200 magnitude accumulations are expected, the entire process would run for 2 seconds. For Galileo signals, one quarter of the magnitude accumulation is used over a 2 second period.

For Galileo signals, as mentioned above, the L1B subchannel contains a data signal that periodically inverts the L1B PRN code during an epoch, while the L1C subchannel contains a secondary code that periodically inverts the L1C PRN code during an epoch. Such inversion limits the coherent integration period to only 4 milliseconds. Thus, in order to have a coherent integration period longer than one epoch, the data and secondary code need to be removed from the signal. Although this removal may be performed at any point in the signal processing, one convenient location is after the correlation is performed and before the coherent integration is performed. To remove the data and secondary code, the correlation result is multiplied by a removal signal, e.g., +1 and-1, as appropriate. The series of values used to remove the secondary code are known a priori codes stored in memory.

After the convolution process, the magnitude RAM 313 has a vector containing the complex magnitude of the convolution result, integrated to improve the signal-to-noise ratio. The vector is further processed by software algorithms executed by CPU 314 to generate pseudorange data used to generate a receiver position, as will be discussed below. It is noted that the CPU computational load for these steps is modest compared to a conventional software tracking loop signal receiver or FFT-based correlator. In execution, any intensive calculations of correlation and integration are done prior to software processing.

Fig. 5 shows a detailed block diagram of the convolution processor 309 (and also the convolution result processing circuit 500), in particular details how full convolution can be generated by reusing a small block of circuitry. The operation of the circuitry in this embodiment may be better understood by reference to the flowchart of fig. 6, reflecting the operation of the processor 309 of fig. 5, in conjunction with fig. 5, and by comparison with the simple examples of fig. 7 and 8.

Although the present invention may be implemented by parallel correlating the entire GSP signal or the filtered galileo signal or a portion thereof with an appropriately selected reference code, the following discussion focuses on the use of a partial correlator. As will be appreciated by those of ordinary skill in the art from the following description, a partial correlator may be used to correlate a received signal to produce a full convolution for either a Galileo signal or a GPS signal without accumulating partial correlations.

The signal from the decimation circuit 307 is connected to shift registers 501a and 501b that process I, Q components, respectively. Each shift register 501a and 501b is P × K in length, where P is the desired number of samples per chip and K is selected as a design parameter. Further, K is a factor of 1023. The variable M defines the total number of partial correlations performed to generate a full convolution using the length K correlation. For simplicity, the remaining discussion focuses on embodiments that process GPS signals when P-2 (samples spaced apart by 1/2 chips), K-22, and M-31. However, since the galileo epoch is 4 times as long as the GPS epoch, the processing speed for processing the galileo signal must be 4 times faster than that used for the GPS signal, and P-3, K-33 (i.e., M-124 for the filtered galileo signal) is maintained. If the number of samples processed at any one time in the correlator is doubled (K66), then the rate at which galileo signals are processed is only twice the speed of GPS processing. In one embodiment discussed below, the correlator has 132 taps (P × K taps) using a clock rate that is twice as fast as the speed required to process the GPS signals. In this embodiment, half of the available taps (K33) are used to correlate the GPS signals. Those skilled in the art will appreciate that the number of taps may vary depending on the clock rate used, i.e., the shorter the correlator, the longer it takes to perform the correlation, and the faster the clock rate required to ensure that the entire epoch of the GPS and galileo signals are correlated.

If the galileo signal is unfiltered and the correlation function is to be less than one chip wide, then P-4, K-33, M-124, the correlator uses 132 taps and the clock rate will be 8 times the clock rate during correlation of the GPS signal. The method of passing signals through the shift register in advance does not need a circuit to double buffer the signals, and reduces the cost and complexity of implementation. Shift registers 501a and 501b are used to correlate the I, Q component of the GPS signal and also to the I of the filtered Galileo signal_USB、Q_USBComponent (or I)_LSBAnd Q_LSB) A correlation is performed.

When processing Galileo signals, the convolution processor 309 must be able to correlate L1B (data) with the L1C (pilot) PRN code. In one embodiment of the present invention, when processing Galileo signals, the shift registers 501a and 501b store the sampled signals, and the PRN code for the L1B signal (data channel) and the PRN code for the L1C signal (pilot channel) are provided in a multiplexed fashion. Thus, when a sample is held in a register, both PRN codes will correlate with the sample at all possible delays, as will be discussed in detail below. To correlate the L1B and L1C signals, the clock rate must be doubled to ensure that all of the delays of L1B and L1C are correlated before the next signal sample is applied to registers 501a and 501 b.

At timing P x f by code NCO 308_o(e.g. 2 f)_o) At this rate, the signal passes through the shift registers 501a and 501b in advance. The signal remains in place in the shift register for several clock cycles so that a series of partial correlation operations can be performed. In particular, a total of M partial correlations are performed, where M1023/K or 31 for the GPS signal and M4096/K or 124 for each of the filtered L1B and L1C galileo signals. For an unfiltered Galileo signal, a four times partial correlation is performed. Each partial correlation operation includes fast vector multiply and add operations between each signal shift register content and a code segment containing a code of P × K (e.g., 132) code samples. The fast vector multiply and add occurs in circuits 502a and 502 b. Circuits 502a and 502b include multipliers 510a and 510b, respectively, and adders 512a and 512 b. This operation includes multiplying each of the 132 signal samples in the signal register 501a or 501b by 132 code samples and adding the results in the adders 512a and 512 b. For Galileo signals, all 132 taps are used in each vector multiplication operation. For GPS signals, half of the taps are used in each vector multiplication operation. This operation occurs simultaneously in I, Q channels, respectively. This operation is mathematically called inner product (inner product) and is defined as:

the output of the vector multiply and add operations is re-quantized to keep the numbers within a small range to avoid overflow of the RAMs 504a and 504 b. The quantizer is not shown for simplicity. In one embodiment, the re-quantization has a resolution of 2 bits.

For a GPS signal, the 66 code samples include 33 unique code samples and 33 copies of the code samples. Thus, for each unique code sample, a copy is used to double the number of code samples. For an unfiltered Galileo signal, the 33 unique code samples are each extended to 4 samples, two of which have a first polarity, followed by two samples of opposite polarity. Thus, each unique sample is followed by a sample having the opposite polarity. For the filtered Galileo signal, 66 code samples are extended to 132 samples.

The results of the vector multiply and add operations are accumulated by adders 503a and 503b and processed by convolution result processing circuit 500. The circuit 500 includes signal RAMs 310a, 310b, a composite normalizer 311, an adder 312, and a magnitude RAM 313, and the accumulation process includes reading current values from the RAMs 310a and 310b for a particular time delay, adding the just-calculated partial correlation results, and writing the added sum back into the RAMs 310a and 310 b. By appropriately combining the partial correlation results corresponding to a particular time delay, the full correlation corresponding to that time delay can be calculated. As described previously, this process continues for as many signal epochs as are expected to be needed to enhance the signal-to-noise ratio. Thus, adders 503a and 503b serve two purposes: merging partial correlations in an epoch; the correlation results are accumulated over several epochs.

When performing the correlation of Galileo signals, it is first necessary to select the signal type to be correlated: USB signal, LSB signal and unfiltered signal, and then select the associated signal component selected: a pilot component (L1C) or a data component (L1B) in each signal type. Each of these signals can be coherently correlated using a partial correlation process alone and the results of the respective correlation processes accumulated in the signal RAMs 310a, 310b, 310c, and 310 d. Typically, only the USB or LSB signal is processed. At a minimum, one of these signals is correlated, e.g., the L1C USB signal; however, correlation can be performed on combinations of 6 signal types and components by multiplexing the use of vector multipliers 502a and 502b (or having multiple registers and/or multiplier operations in parallel) and selecting different code portions for correlation at the appropriate time. Alternatively, a different convolution processor 309 may be used for each signal component. Generally, for GPS signals, RAMs 310a and 310b are used to accumulate the results of the GPS signal correlation process. For Galileo signals, both the L1B and L1C sub-channel signals are correlated. In this case, the signal RAM is divided into two parts 310a and 310c, and also 310b and 310 d. The L1B and L1C results are accumulated separately within each RAM partition. In this manner, each signal is accumulated independently. If only L1B or L1C is used, then only RAMs 310a and 310b are used.

Because the Galileo signal includes data on the L1B subchannel and/or the secondary code of the L1C subchannel, which inverts the signal phase after each PRN code epoch (e.g., a 4 millisecond period), its correlation interval is only 4 milliseconds unless the data or secondary code is removed. If removal is desired, the removal may be performed by a set of multipliers 525a and 525b, which are driven with the data code or secondary code, depending on whether the associated pilot or data channel is being correlated. Code source 527 outputs either +1 or-1 for the duration of an epoch. The secondary code is known a priori and is stored in memory. The data is unknown and must be derived by the CPU 314 from previously received satellite navigation information or from assistance data received from the network. In either case, once the data or secondary code is "erased," the correlation interval can be extended so that correlation can be performed over multiple epochs of data to increase the sensitivity of the receiver. If no quadratic code is used (as may be performed by Galileo systems), the L1C subchannel is available for signal acquisition due to the long correlation interval.

The outputs of signal RAMs 310a, 310b, 310c, and 310d are combined in composite normalizer 311 to form the magnitude of the signal. The I, Q waveforms in these RAMs 310a, 310b, 310c, and 310d may be considered the real and imaginary parts of the composite waveform. Forming the magnitude comprises: the square of each component, the results are summed and the square root of the summed result is taken. Several approximations to this magnitude are available to simplify the circuit. In one embodiment, the composite magnitude is approximated by taking I, Q scalar values (scalar magnitudes) alone and determining which is larger. The magnitude may also be approximated by taking the larger magnitude and adding it to half of the smaller magnitude.

For Galileo signals, coherent correlations of up to 9 different signal correlations are accessible in signal RAMs 310a, 310b and are non-coherently summed to form the input to normalizer 311. The various correlation results may be selectively combined, for example, the combination of the individual L1B correlation, L1B and L1C correlation results, the combination of the correlation result of the unfiltered signal and the correlation result of the filtered signal.

The result of the magnitude operation is scaled to keep its value within a small range, avoiding overflow of the RAM 313. For simplicity, the scaler (scaler) is not shown in the figure. In one embodiment, the scaling includes shifting the magnitude result by 3 bits (i.e., dividing by 8).

Another possibility is to accumulate signal power instead of signal magnitude. In this case, the operation in circuit 500 is a power estimation, typically calculated by taking the sum of the squares of I, Q. Alternatively, additional non-linear operations may be used to generate a value representative of I, Q magnitude or power.

The output of the composite normalizer 311 is accumulated into a magnitude RAM 313 by an adder 312. The accumulation process includes: the current magnitude for a particular latency is read from RAM, the results of the just calculated magnitudes are added, and the added sum is written back into RAM 313. As previously described, the magnitude accumulation operation lasts as many cycles as desired to achieve signal-to-noise enhancement.

Vector multipliers 502a and 502b perform M partial correlations for each shift of the signal. The code lookup circuit 508 generates a reference code sample for each partial correlation. The lookup is controlled by two lookup indices. First, the GPS code must be selected from 1 of the 32 codes. This choice remains constant throughout the convolution process and is determined when the processing channel is configured to perform correlation for a particular satellite signal. The second index is a segment index (segment index) between 1 and M. Each GPS code comprises 1023 chips, which are divided into M non-overlapping segments, each segment comprising K adjacent code chips. The lookup index identifies which code fragments are needed. The output of the code lookup circuit is K chips that make up the segment. The process of selection is controlled by control/addressing logic 514. For Galileo signals, the code consists of 4096 chips, which are divided into M non-overlapping segments, each segment consisting of K adjacent chips. The galileo code segments for the L1B and L1C sub-channels are both looked up in the same way as for the GPS code segment, i.e. using the code and segment index.

For GPS, the PRN is a known code (1023 chip gold code) that can be generated and stored in the look-up table 408 as needed. For galileo, this code is a so-called "memory code", which is not specified in advance and cannot be generated mathematically. Thus, the 4096 chips would be provided by the Galileo specification and stored in memory for loading into the code look-up table 508.

The code spreader 509 takes as its input K chips of a segment and spreads the segment into K × P code samples. The code spreader uses a particular technique, depending on whether GPS signals or galileo signals are being processed. For both the GPS signal and the filtered galileo signal, the spreading operation includes converting each chip into P identical code samples. For an unfiltered galileo signal, P ═ 4, the spreading operation includes using two positive code samples and two inverse code samples. The output of the code spreader 509 forms the reference code that is input to the vector multipliers 502 a-b. In one example, the output of the code spreader 509 is 66 samples consisting of 33 unique GPS chip values or copies of filtered galileo chip values, or 132 samples consisting of unique unfiltered galileo chip values, each of which has an additional positive value and two negative values.

The architecture shown in fig. 5 requires a specific PRN code rate f_oFaster clocks. For example, if a rate of two samples (P ═ 2) per PRN code chip is used, K and M are 33 and 31, respectively, it is necessary to achieve full convolution at 2f_oIs performed 31 times per shift of the signal shift register. Generally, at least one clock cycle is required to read and write to the RAMs 110a and 110 b. Assuming one clock cycle, the minimum clock rate required to achieve full convolution is:

f_clk＝1×31×2×f_o＝1×31×2×1.023MHz≈63.5MHz

this rate is easily implemented in existing integrated circuit logic.

For the filtered Galileo signal, the clock rate is twice the GPS clock rate to ensure that the entire 4 milliseconds of signal are processed in the same time as the GPS signal processing. For unfiltered Galileo signals, the clock rate is four times the GPS clock rate to ensure that 4 milliseconds of the signal are processed and to accommodate the need to increase P from 2 to 4.

It is noted that the present invention can also be used to compute subsets of a full convolution. This is particularly important when processing galileo signals where the clock rate is less than eight times the GPS correlator clock rate. In this case, the partial correlation is performed less than M times for each shift of the signal shift register. In this case, the total delay range will be less than P × 1023 that makes up the full convolution. In particular, if M is performed₂Sub-partial correlation, then M is generated₂xKxP delay value. The clock rate of the processor is reduced by a rate M₂and/M. In addition, the size of the RAM is also reduced by the same ratio M₂and/M. Thus, this option is useful in systems that do not have computational or memory resources to handle full convolution.

In one embodiment of the invention, the correlation of Galileo signals is performed using the same clock rate and partial correlation used in GPS signals. Thus, only one epoch 1/4 is correlated at any one point in time. To ensure that the correlation is performed using the timing that produces the correlation peak in 1/4 of an epoch at which the correlation is performed, the GNSS receiver first acquires signals from the GPS satellites to establish an accurate timing for the receiver, and then acquires galileo signals using the timing estimated from the acquisition of the GPS signals. Since initially there will be significantly more GPS satellites than galileo satellites, the likelihood of establishing the timing of the receiver from signals from GPS satellites before receiving galileo signals is very high.

Or in another scheme, the acquisition of the galileo signal is performed on the pilot component first, and then the data component is acquired. The secondary code (if any) that is expected to be used as part of the pilot component is known and is easily removed to achieve a longer correlation interval for the L1C subchannel. Once the satellite timing is known, the L1B subchannel signals can be correlated using a short (4 msec) correlation interval without erasing the data. Alternatively, the GPS signal may be acquired after timing synchronization is achieved using its long correlation interval. The short (4 msec) correlation interval of either sub-channel can be used to acquire the galileo signal without erasing data or secondary codes from the sub-channel.

Other choices of K and M allow further design tradeoffs to be performed, but since the prime factors of 1023 are 3, 11, and 31, the choices of K and M are limited. Reducing K reduces the size of the shift registers 501a and 501b and the complexity of the vector multipliers 502a and 502b, and is therefore desirable, but reducing K requires a greater M and a greater clock rate. K may be selected to be 3, 11, 31, 33, 93, which require clock rates of 695MHz, 190MHz, 67.5MHz, 63.5MHz, and 22.5MHz, respectively (it is generally assumed that P is 2 and each offset is associated with 1 clock cycle). Based on the available technology at the time of the example, K66 is selected in one embodiment. By using further techniques, it becomes feasible to choose K11, with a clock rate of 190MHz, and the logic complexity can be further reduced. In this way, the architecture achieves the best fit trade-off between rate and logic complexity.

The order of the code segments is controlled by control logic 514, which also identifies the correct addresses of RAMs 310a, 310b and 313. As will be discussed below, partial correlations are generated in a non-continuous sequence, such that the generation of RAM addresses is non-trivial.

The operation of the circuit of fig. 5 may also be understood with reference to the flow chart of fig. 6. The method 600 begins at step 650 and then proceeds to step 652 where it is selected whether the processing channel is to process Galileo signals or GPS signals. If the method 600 selects a Galileo signal, the method 600 proceeds to step 654. In step 654, the method detects a signal to be processed, i.e., filtered or unfiltered. At step 656, the method determines which sub-channel (L1B or L1C) or both will be processed. If only L1B is to be processed, then at step 650, the L1B PRN code is selected for use. If only L1C is to be processed, then at step 658, the L1C PRN code is selected for use. If both L1B and L1C are processed, the method 600 selects the L1B PRN code at step 666 and the L1C PRN code at step 668. While the described embodiment may select the signals to be correlated, a simple embodiment may perform the correlation only for the Galileo sub-channel, L1C. In such an embodiment, steps 654, 656, 660, 666, and 668 would not be used, and the embodiment selects the L1C code at step 658.

If the GPS signal selected in step 652 is to be processed, the method 600 selects a GPSPRN code in step 662.

At step 601, the method 600 begins the preloading of the signal shift registers 501a and 501 b. At this point, the convolution process can begin. At step 602, one or more code segments of the selected PRN code are accessed for a particular partial correlation.

At step 603, the code segment is spread by a code spreader to P samples per PRN chip. As described above, for unfiltered galileo signals, a reversed polarity chip code is used, whereas for GPS a replica of the chip code is used. If the Galileo signal is filtered, the Galileo signal code is extended in the same manner as the GPS code.

Next, at step 604, a delay index and corresponding RAM address are calculated. The delay index indicates that some point of the full convolution will be updated by the partial correlation. As shown in the example discussed in connection with fig. 8, the delay index jumps in a non-linear but deterministic manner. The address calculation is a function of the signal shift (signal shift) and the number of code segments.

In step 605, partial correlations are calculated using vector multipliers 502a and 502 b. At step 664, the data or secondary code is removed, if necessary. At step 606, the result of the vector multiplication is accumulated into the signal RAM at the location indicated by the delay index. At step 670, method 600 queries whether both L1B and L1C sub-channels are being correlated. If both L1B and L1C sub-channel signals are in process, the method proceeds to step 603 and repeats steps 603, 604, 605, 664 and 606 for the L1B code and then for the L1C code, and vice versa. Then at step 607 a check is made to determine if the end of the coherent integration interval has been processed and if not the method returns to step 602 and repeats the above steps for the next code segment.

If at step 607 the check indicates that partial correlations have been completed for all code segments (i.e., M partial correlations), the method proceeds to step 608. In step 608, the signal registers 501a, 501b, 501c, and 501d are shifted by one sample.

The method 600 then proceeds to step 609 where a check is performed to see if the last shift has reached the end of the coherent integration interval. If not, the process loops back to step 602. If the detection indicates that the coherent integration interval is over, the method continues to step 610 where the signal magnitude is calculated by the composite normalizer 311. The resulting results are added using adder 312 and stored into magnitude RAM 313. Next, in step 611, a test is performed to determine if all magnitude accumulations are complete. If so, the method ends at step 612, and if not, processing continues with performing the next partial correlation at step 601.

Fig. 7 and 8 illustrate by way of a simple example how the invention accumulates full convolution results using partial correlation. For clarity of description, these figures depict the convolution of a very short length 6 code, rather than a 1023 GPS PRN code or a 4092 Galileo PRN code for satellite signals. To further simplify the example, one sample per chip is used, i.e. P ═ 1. Fig. 7 depicts the convolution by the standard matched filtering method and fig. 8 depicts the same convolution by combining partial correlations. The detailed description of fig. 8 is helpful in understanding the overall operation of the present invention. Both methods form the same convolution result.

Fig. 7 illustrates the operation of a prior art matched filter for a length 6 signal. The operation starts at a time denoted as shift 0. At this point in time, 6 consecutive signal samples that make up the entire period of the signal are located in signal shift register 701. The individual samples are indicated by capital letters A, B, C, D, E and F. Code samples of the entire length 6 code are stored in the reference register 702, represented by the lower case letters a, b, c, d, e, and f. At the time of shift 0, vector multiplication and addition are performed to generate a correlation result at the time of shift 0. Each signal sample is multiplied by a corresponding code sample and the results summed to obtain a correlation result 703.

Next, the signal shift register 704 advances by one sample, as shown by shift 1. The signal is periodic so that the new sample introduced on the left side of the register is the same as shifted out to the right. The shifted contents of register 704 are now samples with indices F, A, B, C, D and E. The code is not shifted. The vector multiply and add produces a correlation result 705 at the time of the shift by 1. The process of shifting also lasts 5 additional shifts, when all 6 correlation results make up the available full convolution.

Fig. 8 shows how the same convolution results are obtained by the partial correlation method. As described, the present invention requires partitioning the code into M segments of length K. In the simple embodiment of fig. 8, the length 6 code is divided into 3 segments of length 2, i.e., K-2 and M-3. The operation starts at a time denoted as shift 0. At this time, two signal samples are held in the signal shift register 801. The signal samples are identified by capital letters a and B. The 6 samples of the code are contained in 3 segments of length 2 per segment. The first code segment 802 includes 2 code samples, denoted by the lower case letters a and b. The signal remains in its place to perform 3 partial correlation operations, resulting in partial correlation results 803a, 803b, and 803 c. The first partial correlation result is generated by vector multiplication and addition between the contents of the signal register and the first code segment (segment 1). The second and third results are produced by vector multiplication of the signal register with the second and third code segments, respectively. It is noted that the signal register holds its position for a sufficient time that all three vector multiplications have been performed, and that the code does not shift during this time, but a different code segment is selected.

The partial correlation results are integrated into memory via signal path 805. For example, at shift 0, the partial correlation result from the first code section is added to the correlation result 804. At shift 2, the partial correlation result from the second code section is added to the correlation result 806. At shift 4, the partial correlation result from the third code section is added to the correlation result 808.

After performing the three partial correlations, the signal is shifted. At this stage, the signal register contains samples F and a, as shown by shift 1. Again, three partial correlation results are generated using the same three code segments as before. The results from these partial correlations are added to the correlation results 810, 812, 814, respectively, at shifts 1, 3, and 5. This process continues for 4 additional signal shifts, at which point full convolution results are obtained. It can be seen that this operation needs to produce a total of 18 partial correlation results, adding to the 6 full results to form a convolution.

The structure depicted in fig. 8 depicts two important features of the present invention. First, it is apparent that only a length 2 shift register and vector multiply and add unit are used to produce a full convolution for a length 6 code. This requires less circuitry than in fig. 7, where the devices are 6a in length. Second, in FIG. 8, the code samples are taken from a fixed code segment that is the same for each shift, and each code segment is a separate non-overlapping portion of the code. Thus, as will be discussed further below in fig. 9 and 10, a simple lookup or register approach may be used to provide the code to the vector multiplier. These methods require less circuitry than other structures, which require, for example, large blocks of code bits to be available in a more complex set of permutations. The present invention also eliminates the need to provide a code generation circuit.

FIG. 9 illustrates a block diagram of one embodiment of the code lookup circuitry 508. Table 901 contains the stored values of all 1023 bits for each of the 32 codes plus 4092 bits of each Galileo code (L1B or L1C). Because Galileo code is not predefined, the code must be loaded into circuitry 508. As such, the circuit 508 may be a random access memory. Table 901 is organized by a number of sub-tables, one for each code. Each sub-table is further composed of M segments of length K, where K × M is 1023 (or 4092), the selection of K and M being described above. Multiplexer 902 selects a particular code based on the selected value. The output of the multiplexer 802 is a specific sub-table for the desired code. Multiplexer 903 selects a particular segment based on a segment select value between 1 and M. The output of the multiplexer 903 is a specific code segment 904 of length K that contains the code bits that are provided to the code expander 509.

It should be noted that multiplexer 903 must have a high rate in order to change the code segment for each partial correlation, i.e., each clock cycle. Therefore, all code bits need to be pre-stored in the table 901, rather than being generated in real time in the conventional manner of a GPS code generator.

The circuit of fig. 9 is described below. In practice, there are a number of different circuit designs that are functionally equivalent. In particular, the logic synthesis process used in modern ASIC designs will produce some form of logic gates that implement the same actions as described above rather than having to use multiplexers in the manner described above.

Fig. 10 shows a block diagram of another alternative embodiment of the code lookup circuit 508. 1023 (or 4092) code bits corresponding to a particular code are stored in 1023 (or 4092) bi-directional shift registers 1001, which are grouped into M rows of length K. The shift register operates in two modes: run mode and load mode. Typically, two sets of 4092 shift registers are used to provide galileo L1B and L1C codes synchronously. When processing Galileo signals, the shift registers are fully loaded, whereas when processing GPS signals, only 1023 registers are filled. Alternatively, for GPS signals, four codes are used to load all 4092 registers.

In the run mode, each register 1001 is configured to shift its sample into the shift register of its previous row, except that the sample of the shift register of the top row is shifted into the shift register of the bottom row. In the operating mode, the direction of displacement is indicated by the solid arrow in 1001. By clocking all registers, each row of code bits will cycle, so that at any one time the top row contains one of the M code segments of length K. The top row of bits is provided to code spreader 509. The registers are fast-looping so that a different code segment is available for each partial correlation.

In the load mode, each register is configured to shift its sample into the shift register of its next column, except that the shift register of the last column shifts its sample into the shift register of the first column in the row above. The shift direction in the load mode is indicated by the dashed arrow in 1001. The lower left shift register 1004 is connected to the code memory 1002, which is typically a flash memory. The code memory stores 1023 GPS code bits for each of the 32 codes, and 4092 Galileo code bits for each of the L1B and L1C codes. When the code lookup circuitry 508 is configured for a particular code, the registers are set in load mode, the memory is accessed to provide code bits for the corresponding code, and then clocked through (clock through) the registers. After all bits are clocked through, the code resides in a register in M segments of length K. The circuit is then ready for use in a run mode.

Another alternative to using shift registers is a RAM, which stores all necessary GPS and galileo codes. The RAM is used to select code segments to apply to the vector multipliers 502a and 502 b.

FIG. 11 illustrates a block diagram of one embodiment of a GNSS receiver 1100 that is capable of operating in multiple resolution modes. The GNSS receiver 1100 may include a convolution processor 1109 that may operate in either a standard resolution mode or a high resolution mode. In addition, the digital signal samples in standard resolution mode are spaced 1/2 (i.e., P-2) apart by the PRN code chip spacing. The digital signal in the high resolution mode has a sample interval of 1/5 (i.e., P5) of the PRN code chip interval. Thus, the code NCO 1108 and decimation circuit 1107 operate at multiple sampling rates. Those skilled in the art can readily devise other sampling interval values and understand that the present invention can operate in more than two resolution modes.

The embodiment of fig. 11 has similar devices to the embodiment shown in fig. 3. Operation of devices having the same reference numerals as in fig. 3 is as described above in connection with fig. 3. The decimation circuit 1007, code NCO 1108, convolution processor 1009 and mode selection processor 1102 operate as described below to enable the use of multiple resolution modes. Fig. 11 further includes a mode selection processor 1102. The mode selection processor 1102 processes the received signal to determine whether the processing channel 1104 should operate in a high resolution or standard resolution mode.

It should be noted that at standard resolution (i.e., P-2), the least squares estimation algorithm uses only 4 points over the entire width of the correlation. In the presence of noise, this limits the accuracy of the curve fitting process. Furthermore, in some cases, the center of the triangle (i.e., the point of maximum correlation within the ACF) is between the observed correlation values. In this case, the observed correlation value and the observed signal-to-noise ratio are significantly lower than if the peak of the triangle were close to the observation point. The high resolution mode includes a plurality of closely spaced points in the least squares estimation process, which improves accuracy and signal-to-noise ratio.

Specifically, FIG. 12 shows the accumulated magnitude waveform in a high resolution mode for either the GPS signal or the filtered Galileo signal. For an unfiltered Galileo signal, the peak is narrower, but the concepts described below are the same. Graph 1200 shows convolution magnitude values (axis 1208) near a peak corresponding to latency of a signal processed in high resolution mode. The points on the chip axis 1210 are spaced apart by a distance equal to the PRN code chip length divided by P, where P is the signal sample rate and the PRN code chip rate f_oThe ratio of. In the high resolution example, P is 5, so the spacing between the dots is 1/5 chip intervals, or approximately 200ns (nanoseconds). (this interval in time corresponds to a distance difference of about 60 meters). To achieve high accuracy pseudorange measurements, the convolved outputs are typically further processed in CPU 314.

In standard resolution processing, a number of interpolation techniques are available to estimate the correct time delay using the discrete correlation values provided by the convolution. One embodiment uses a least squares estimation algorithm to determine the signal parameters that best fit the noisy data. The correlation response exhibits a convex triangular form 1202. The width 1203 of triangle 1202 is 2 PRN code chips, corresponding to 11 sample points (in the case of P ═ 5). The high 1204 of triangle 1202 is for the magnitude of noise in the convolution that does not correspond to the time lag of the signal. The magnitude of this noise is estimated from the data or pre-calculated based on design parameters such as amplifier noise figure, cable and filter losses and system temperature. The peak 1205 and center 1206 of the triangle 1202 are unknowns corresponding to signal magnitude and delay. Both parameters can be estimated using a least squares method to fit the noisy data points to a triangle with a particular peak and center.

One benefit of the high resolution mode over the standard resolution mode is that the convex triangular correlation response is sampled at twice the point. As will be appreciated by those of ordinary skill in the art, the accuracy of the fitting process depends on the number of values used in the estimation. Furthermore, in high resolution mode, the ratio of the peak to bottom values of the triangle is increased, which indicates an improved signal-to-noise ratio, in part because the available correlation points are close to the maximum correlation point. In this way, high resolution mode can be used to reliably identify and measure correlation peaks that cannot be discerned in standard mode. This is very advantageous when dealing with low energy signals such as those received indoors from SPS satellites.

As will be described in fig. 13, these two modes of operation are achieved by dynamically changing the values of the parameters P, K and M to achieve the desired resolution. In one embodiment, in the standard mode, P is 2 (i.e., two samples per PRN code) and in the high resolution mode, P is 5 (i.e., five samples per PRN code). The correlation point spacing is 1/P chip wide and it is clear that the resolution is better for larger P values. As mentioned above, K is chosen as a design parameter, which is a factor of 1023. For simplicity, the following description focuses on one particular embodiment of P-2 and K-33 in the standard mode and P-5 and K-11 in the high resolution mode.

When processing an unfiltered galileo signal, the sampled signal uses 3 normal samples and 2 inverse samples (inverted samples) on the first chip, then 2 normal samples and 3 inverse samples on the second chip, and then repeats for each subsequent chip, because P-5 cannot be divided exactly by 2. Alternatively, P-6 is used to sample the unfiltered galileo signal in the high resolution mode, so that normal sampling and inverse sampling can be used alternately over all chips. Of course, if the Galileo signal is filtered to generate a BPSK-like signal, then normal sampling is used for the entire signal.

FIG. 13 depicts a block diagram of another embodiment of a convolution processor 1109 suitable for operation of the present invention in multiple resolution modes. For simplicity, only the I channel of the process is shown, but it is clear that the Q channel comprises the same processing devices. In the current embodiment, the convolution processor 1109 includes a shift register 1301, a vector multiplication circuit 1302, an adder 1303, a code extender 1309, and a code lookup table 1308. The code extender 1309 further includes a standard code extender 1304 and a high resolution code extender 1305. The I signal from the decimation circuit 1107 is coupled into the shift register 1301. The shift register 1301 has a variable length because the value of P × K changes for the standard and high resolution modes. In particular, the shift register 1301 must hold 66 samples in the standard mode and 55 samples in the high resolution mode. As such, shift register 1301 includes 66 devices to support both lengths. In high resolution mode, the last 11 devices are deactivated.

In either the normal mode or the high resolution mode, the signal advances in the shift register 1301 at the rate of Pf0, as controlled by the timing of the code NCO 1108. The signal maintains its position for several clock cycles in order to perform a series of partial correlation operations. In particular, a total of M partial correlations are performed, where M is 1023/K. For the present example, M is 31 in the standard mode and 93 in the high resolution mode. Each partial correlation operation includes fast vector multiply and add operations between the contents of shift register 1301 and the code segment containing P × K code samples. This operation is performed by vector multiplier 1302, which includes multiplier 1310 and adder 1312. Similar to shift register 1301, vector multiplier 1302 has a variable length to support standard and high resolution modes of operation.

The related operations include: each of the P × K signal samples in the shift register 1301 is multiplied by P × K code samples (formed by spreading the code samples by the code spreader 1309), and the multiplication results are added in the adder 1312. As mentioned above, this operation is mathematically referred to as the inner product. The results of the vector multiplication and addition are accumulated by adder 1303 and processed by convolution result processing circuit 500 in the same manner as described in fig. 5.

The code look-up table 1308 generates the reference code samples for each partial correlation and organizes them to provide code segments for standard and high resolution modes. First, a code must be selected from available GPS or Galileo codes. The selection is constant throughout the convolution process and is determined when configuring the processing channel to perform correlation for a particular satellite signal. The second index is the segment index between 1 and M. In the present example, the number of samples per segment in the standard mode is 33 and 11 in the high resolution mode. To support both modes, the code look-up table 1308 includes 93 segments 1307 of 11 chips each. The 93 segments 1307 are further organized into 3 groups 1306 a-c, where each group has 31 segments. The output of each group 1306 a-c (an 11 chip segment) is accessed by a code spreader 1309.

In the standard mode, the output segments of each group 1306 a-c are combined to form a wide segment of 33 chips. In particular, the selection of the segments is made between 1 and 31. The selection of segments and the selection of codes are used to multiplex 3 segments 1307 of 11 samples from groups 1306 a-c. The segments 1307 are concatenated to form a 33 sample wide segment that is input to the standard code spreader 1304. In high resolution mode, the segment selection is from 1 to 93. Only one segment 1307 is selected from the groups 1306 a-c. The 11 sample segment 1307 then accesses the high resolution code spreader 1305.

In the standard mode, the standard code extender 1304 is active, which extends a 33 sample wide code segment to 66 samples. In the high resolution mode, the high resolution code expander 1305 is active, expanding the 11 sample code segment to 55 samples. Although the code expander 1309 is shown as including a standard code expander 1304 and a high resolution code expander 1305, those of ordinary skill in the art will appreciate that they may be functionally combined into one code expander 1309.

The clock rate is changed between the standard mode and the high resolution mode. For example, in standard mode, as described in connection with FIG. 5, a clock rate of about 63.5MHz supports full convolution at P, K and M of 2, 33, and 31, respectively, in real time, requiring two clock cycles per RAM cycle. In the current embodiment, the high resolution mode parameters P, K and M are 5, 11, and 93, respectively, so the clock rate to produce full convolution is:

f_clk＝5×93×2×f_o＝5×93×2×1.023MHz≈952MHz

because this rate is difficult to achieve in existing integrated circuit logic, and because the size of the RAM will grow from 2046 samples to 5115 samples, to reduce the cost and complexity of the convolution processor 1009, it may be desirable to generate a less than the full convolution when operating in the high resolution mode.

Thus, in an embodiment, in high resolution mode, a sub-full convolution is calculated by reducing the number of partial correlations performed for each shift of the input signal. As will be described below in connection with fig. 14, the partial correlations are selected to produce correlation points for a particular region of interest in the full convolution. In this alternative embodiment, the required clock rates are:

f_clk＝5×L×2×f_o

where L is a value less than M and represents the partial correlation quantity for each input cyclic shift. Thus, the total number of generated correlation points is P × K × L. For example, in one embodiment, L is 12, P × K × L is 660, or 1/8 of a C/a code epoch. In this example, the required clock rate is

f_clk＝5×12×2×1.023MHz≈123MHz

Which is a value comparable to the clock rate in standard mode.

Because only a subset of the full convolution is produced, it is necessary to select the portion of interest that contains the signal peak. FIG. 14 shows a flow diagram of a method 1400 of operation for computing a plurality of correlation results. The method 1400 begins at step 1402. In step 1404, a check is performed to determine if sufficient external aiding information is present to enable direct use of the high resolution mode. The aiding information may take several forms, including estimates of pseudoranges and local clock biases for the satellites of interest. If the side information is accurate enough, the method transitions to high resolution mode in step 1410. However, often, the local clock bias is not known. For example, estimated pseudoranges, the most recently known receiver position, may be obtained from stored ephemeris, but the local clock bias is not known unless the receiver maintains accurate time-of-flight or is externally synchronized. If there is not sufficient external assistance information, then pseudorange measurements are performed in standard mode in step 1406. In step 1406, a full convolution is obtained using the standard resolution. After one or more measurements are performed in the standard mode, the local clock bias is estimated in step 1408. This step may optionally include estimating a timestamp error. The method 1400 then transitions to the high resolution mode at step 1410. In this regard, the signal delay is limited to a number of windows containing correlation peaks at standard resolution, which are calculated in step 1412. After the range window is calculated, the method 1400 measures pseudoranges in high resolution mode (i.e., using high resolution correlation peaks) in step 1414. The method 1400 ends at step 1416.

When processing a galileo signal, the high resolution mode may be used to switch to using the unfiltered galileo signal, using both the data and pilot components, and so on. Since Galileo signals provide a number of different signal options for correlation, once the estimate of time is known and the high resolution mode can be invoked, more signal processing can be used on the other signal components. By using USB only (or LSB only) to acquire at 3dB signal reduction, a large segment (or all) of the galileo code can be correlated using the L1C subchannel. Once the timing is obtained from processing only the L1C USB signal (or the L1C LSB signal), a portion of the code near this timing estimate can be processed in standard or high resolution mode using the filtered L1B sub-channel, or the unfiltered galileo signal for L1B and/or L1C.

Method 1400 allows for more advantageous use of high resolution modes, despite the limitation that only partial convolutions are calculated. The high resolution mode may be invoked for all subsequent satellite signal acquisitions as long as at least one GPS or galileo satellite is detected in the standard mode. In the high resolution mode, the sensitivity of the correlation process is increased so that more satellites can be detected. Furthermore, as described above, the accuracy of all measurements is improved in the high resolution mode.

Although various embodiments which incorporate the teachings of the present invention have been shown and described in detail herein, those skilled in the art can readily devise many other varied embodiments that still incorporate these teachings.

Claims (21)

1. An apparatus for processing signals from a plurality of satellite systems, comprising:

a tuner for selecting and single sideband filtering a first signal from a satellite within a first satellite system or selecting a second signal from a satellite within a second satellite system;

a convolution processor coupled to the tuner for correlating the filtered first signal or the second signal with a selected portion of a reference code to produce at least one partial correlation and accumulating the at least one partial correlation to produce a full convolution.

2. The apparatus of claim 1 wherein the first satellite system is a galileo system.

3. The apparatus of claim 1, wherein the first satellite system is a global positioning system.

4. The apparatus of claim 1, wherein the tuner further comprises:

a quadrature tuner for generating an in-phase component and a quadrature component of the first or second signal;

a complex single sideband filter connected with the quadrature tuner for filtering the first signal.

5. The apparatus of claim 1, wherein the convolution processor comprises:

a partial correlator for performing correlation on a portion of the filtered first signal or the second signal.

6. The apparatus of claim 1, further comprising:

a decimation circuit coupled between the tuner and the convolution processor for subsampling the filtered first signal or the second signal, wherein the subsampling pitch used by the decimation circuit is a plurality of selectable sampling pitches.

7. The apparatus of claim 6, wherein the decimation circuit uses a first sampling pitch during the first mode and a second sampling pitch during the second mode, and wherein the first sampling pitch is greater than the second sampling pitch.

8. The apparatus of claim 1, wherein the filtered first signal comprises at least one of an upper sideband signal and a lower sideband signal.

9. The apparatus of claim 1, wherein the convolution processor further comprises a correlation circuit configured to perform a correlation on at least one of a pilot component and a data component of the filtered first signal.

10. A method of calculating a correlation of a digital signal and a pseudorandom reference code, comprising:

receiving at least one of a first signal from a first satellite system or a second signal from a second satellite system, wherein the first signal has an additional code;

single sideband filtering the first signal to generate a filtered first signal;

correlating the filtered first signal or the second signal with a pseudorandom reference code to produce a first partial correlation;

accumulating the first partial correlations to generate a full convolution;

timing and frequency synchronization is established using the full convolution.

11. The method of claim 10, wherein the first signal is a satellite signal from a galileo satellite and the second signal is a satellite signal from a GPS satellite.

12. The method of claim 10, wherein the additional code is a bi-phase offset carrier code.

13. The method of claim 10, wherein the step of performing correlation further comprises:

dividing the pseudo-random reference code into a plurality of code segments;

selecting a code segment;

forming an inner product between the selected code segment and the first signal or the second signal without additional codes to generate a partial correlation;

repeating the selecting and forming steps to produce a plurality of second partial correlations;

adding the plurality of second partial correlations as each second partial correlation is generated to form a plurality of second correlations.

14. The method of claim 10, wherein the receiving step further comprises:

selecting a first or second sampling interval for the first or second signal, wherein the first sampling interval is greater than the second sampling interval.

15. The method of claim 10, wherein the filtering step generates at least one of an upper sideband signal and a lower sideband signal.

16. The method of claim 10, wherein the step of performing correlation further comprises: performing correlation on at least one of a data component or a pilot component of the filtered first signal.

17. An apparatus for processing signals from a plurality of satellite systems, comprising:

a tuner for selecting and single sideband filtering a first signal from a satellite in a first satellite system or selecting a second signal from a satellite in a second satellite system;

a convolution processor coupled to the tuner for correlating the filtered first signal or the second signal with a reference code to generate a full convolution.

18. The apparatus of claim 17 wherein the first satellite system is a galileo system and the second satellite system is a global positioning system.

19. The apparatus of claim 17, wherein the convolution processor comprises:

a partial correlator for performing correlation on a portion of the filtered first signal or the second signal.

20. A method of calculating a correlation of a digital signal and a pseudorandom reference code, comprising:

receiving at least one of a first signal from a first satellite system or a second signal from a second satellite system, wherein the first signal has an appended code;

single sideband filtering the first signal to generate a filtered first signal;

correlating the filtered first signal or the second signal with a pseudorandom reference code to generate a full convolution;

timing and frequency synchronization is established using the full convolution.

21. The method of claim 20, wherein the first signal is a satellite signal from a galileo satellite and the second signal is a satellite signal from a GPS satellite.