HK1129950B - Surface mountable lightemitting element - Google Patents

Abstract

A chip that can be mounted on a surface includes a circuit device and a base.The circuit device comprises a top layer and a bottom layer, each having a top contact and a bottom contact.The base comprises a substrate having a base top surface and a base bottom surface.The top surface of the base includes a top electrode bonded to the bottom contact, and the bottom surface of the base includes first and second bottom electrodes electrically isolated from each other.The top electrode is connected to the first bottom electrode, and the second bottom electrode is connected to the top contact through a vertical conductor.An insulation layer is bonded to a surface of the circuit device and a portion of a vertical surface covering the bottom layer.The vertical conductor includes a metal layer bonded to the insulation layer.

Description

Surface mountable light emitting element

Technical Field

The present invention relates to a light emitting device, and more particularly, to a light emitting device mountable on a surface.

Advances in Light Emitting Diodes (LEDs) have led some devices to use them as light sources instead of traditional light sources such as fluorescent lamps and incandescent bulbs. Light emitting diode light sources have energy conversion efficiencies approaching or exceeding conventional light sources. Furthermore, led light sources have a lifetime that far exceeds that of conventional light sources. For example, a fluorescent light source has a lifetime of approximately 10000 hours, whereas a light emitting diode has a lifetime of approximately 100000 hours. Moreover, the daylight lamp light source is completely without any warning when it is out of operation. In contrast, led light sources tend to darken before they fail, thus giving the user a suitable warning.

Unfortunately, leds have certain disadvantages when used to replace conventional light sources. First, leds emit light in a relatively narrow spectrum, providing a light source that can only be perceived to a specific color, and therefore a certain number of leds emitting light in different narrow spectrums need to be packaged together, or the leds need to be covered with one or more phosphors to cause the leds to excite the phosphors to provide the desired output spectrum.

In addition, a single led has a limited light output. Even high power leds are best available in only a few watts. Further, as mentioned above, a certain number of leds need to be combined in a light emitting element to provide a desired output spectrum. Thus, to provide a light source with any output spectrum in excess of several watts, a certain number of leds need to be combined in a single unit.

To provide such multiple led devices, a number of led dies are typically attached to some type of substrate. The manner of connection can be divided into two types. The first type relies on wire bonding to connect one or more electrodes on the die to corresponding electrodes on the substrate. There are problems with this connection. First, wire bonding needs to be performed separately. Second, the bond wires are vulnerable and need to be protected. Typical protection methods include placing the die and wire bonds in some transparent encapsulation material. Unfortunately, the encapsulant can age causing light absorption. In addition, the stress applied by the encapsulant to the wire bonds may cause premature device failure. Furthermore, packaging is an additional assembly step that results in additional cost. Further, the encapsulation material typically limits the maximum tolerable temperature of the component. In addition, the encapsulation material stresses the light emitting diode material such that the required operating voltage is increased. Third, the wire bonding generally blocks part of the light emitted from the led, thereby reducing the efficiency of the light source. Finally, it is noted that the wire bond damage can be a significant factor in the overall device damage.

The second connection method, in principle, avoids wire bonding, thus solving the problem caused by wire bonding. These methods are typically flip-chip (flip-chip) methods. In these methods, the light emitting diode can be fabricated on a transparent substrate by depositing multiple layers on the substrate. Since these multiple layers used to construct the light emitting diode are well known to those skilled in the art, the details of these layers are not discussed herein. A light emitting diode includes three primary layers, an n-type layer typically deposited first on a substrate, an active layer for generating light, and a p-type layer. Electrons flowing from the n-type layer to the active layer region combine with holes flowing from the p-type layer to the active layer region in the active layer.

In order to light the led, a potential needs to be applied between the n-type layer and the p-type layer. But the n-type layer is buried in the aforementioned multilayer stack. There are two basic configurations for dealing with this connection problem. In a first configuration, the n-type and p-type connections are made through electrodes on the outer surfaces of the layers. This type of element is classified as a vertical device in the following discussion. The second type of element is classified as a lateral device. In lateral type elements, the connection of the buried layer is provided by etching the upper layer of the buried layer to expose the buried layer. In the example described above, portions of the p-type layer and portions of the active layer of the device are removed to expose the underlying n-type layer. The connection to the n-type layer is provided by depositing a metal layer on the exposed layer. In devices connected by wire bonds, one of the wire bonds is attached to the metal layer. Such devices are referred to as lateral-type devices because the current must flow laterally from the exposed platform to reach the active layer. Flip-chip leds are an example of such a lateral type device.

In a flip chip LED, the connection of the n-type layer is achieved by etching part of the p-type layer and part of the active layer of the device to expose the n-type layer. A conductive layer is deposited on the exposed n-type layer mesa and used to make the layer connections. To mount the chip on a carrier, such as a printed circuit board, the chip is inverted so that the contacts on the top of the leds match the pads (pads) on the printed circuit board. The wafer is thus bonded to the printed circuit board.

Although flip-chip leds avoid the problems of wire bonding, new problems arise. First, the chip must be placed on a printed circuit board or the like. This operation requires a high degree of accuracy, since the contacts are very small and close to each other. End product manufacturers may not have the facility to achieve such precise placement under general economic considerations. Therefore, these components are typically packaged on a separate carrier like a small printed circuit board with pads that are spaced further apart, thus reducing the accuracy required by the end product manufacturer to place the components. Unfortunately, this solution increases the volume of the packaged component and therefore limits the density of leds in the end product. Furthermore, this solution increases the cost expenditure of the final leds, since the leds have to be individually connected to the carrier.

Second, flip chip bonding to the carrier, whether the final printed circuit board or the intermediate carrier described above, involves process steps that may result in layer-to-layer shorting of the leds. These short-circuiting phenomena occur during the joining process or after a certain period of time has elapsed during the lifetime of the component. These short circuits cause the yield of the led to be reduced and the cost to be increased.

Third, the cut mesas used to provide the n-type layer contacts occupy a substantial portion of the surface area of the die. This substantial area does not produce light because the cleaved mesa passes through the active layer. Thus, the total amount of light per unit area leaving the element is greatly reduced.

Disclosure of Invention

The present invention provides a device comprising a circuit device and a base, the circuit device comprising a plurality of semiconductor layers having a top layer and a bottom layer, the top layer comprising a top surface having a top contact on the top surface and the bottom layer having a bottom surface and a bottom contact on the bottom surface, a potential difference being required to operate the circuit device between the top contact and the bottom contact; and the base comprises a substrate having a base top surface and a base bottom surface, the base top surface bonded to the bottom layer and the base bottom surface comprising a first bottom electrode and a second bottom electrode electrically isolated from each other, the bottom contact connected to the first bottom electrode by a first conductor and the second bottom electrode connected to the top contact by a second conductor; wherein the bottom layer comprises an insulating layer bonded to a surface of the bottom layer and wherein the second conductor comprises a metal layer bonded to the insulating layer, the insulating layer preventing contact between the second conductor and the bottom layer.

The invention can be used to construct a surface mountable light emitting device comprising an active layer, and a first semiconductor layer and a second semiconductor layer, the active layer being located between the first and second semiconductor layers. The first semiconductor layer has a top surface including the top contact, and the second semiconductor layer has a bottom surface including the bottom contact. When a potential is applied between the top contact and the bottom contact, holes and electrons combine in the light-emitting element to generate light.

Drawings

FIG. 1 is a cross-sectional view of a flip-chip LED mounted on a printed circuit board.

Fig. 2 is a top view of an led according to an embodiment of the present invention.

Fig. 3 is a cross-sectional view taken along line 3-3 of fig. 2.

Fig. 4 is a bottom view of the light emitting diode 40.

Fig. 5 is a top view of a portion of a wafer having a plurality of leds.

Fig. 6 is a cross-sectional view taken along line 6-6 of fig. 5.

Fig. 7 is a partial top view of a base having multiple elements.

Fig. 8 is a cross-sectional view taken along line 8-8 of fig. 7.

FIG. 9 is a cross-sectional view of a portion of the light emitting section and a portion of the base section before bonding.

FIG. 10 is a cross-sectional view of a portion of the light emitting section and a portion of the base section after bonding.

FIG. 11 is a cross-sectional view of a portion of the base portion and the light-emitting portion after bonding and removing the substrate.

Fig. 12 is a top view of a light emitting diode according to another embodiment of the present invention.

Fig. 13 is a top view of a light emitting diode according to another embodiment of the present invention.

Fig. 14 is a cross-sectional view taken along line 14-14 of fig. 13.

Figure 15 is a top view of a base wafer according to the present invention.

Fig. 16 is a cross-sectional view taken along line 16-16 of fig. 15.

Fig. 17 to 20 illustrate a method for manufacturing a light emitting diode having the structure of the light emitting diode 200.

Fig. 21 is a top view of a partially bonded wafer before dicing.

Fig. 22 is a cross-sectional view of a light emitting diode according to another embodiment of the present invention.

Detailed Description

The present invention can be more readily understood by reference to a light emitting diode. However, as discussed in detail below, the present invention may be used to construct a number of different circuit devices having base portions that are substantially the same size as the integrated circuit chip. These bases provide a function similar to the sub-mounts discussed above, but without the limitations discussed above.

The advantages provided by the light emitting diode of the present invention can be more readily understood with reference to fig. 1. Fig. 1 is a cross-sectional view of a flip-chip led 20 mounted on a printed circuit board 31. The light emitting diode 20 is fabricated on a transparent substrate 21 by depositing an n-type layer 22, an active layer 23, and a p-type layer 24 as described above. A reflective electrode 29 is deposited over layer 24. the reflective electrode 29 serves both as an electrical contact for spreading current through layer 24 and as a mirror for reflecting light generated in the active layer and directed toward electrode 29. The electrode 29 is connected to a corresponding electrode 32 on the printed circuit board 31 via a solder ball 27.

As described above, to provide electrical connections to layer 22, a mesa (mesa) as shown at 25 is etched in the stack. An electrode 26 is deposited on the platform and connected to a corresponding electrode 33 on a printed circuit board 31 via electrode 28 and solder ball 30.

The size of the platform 25 is preferably as small as possible, since the area 34 occupied by the platform 25 is not capable of generating any luminescence and therefore represents wasted space from the standpoint of generating luminescence. On the other hand, the platform 25 should be large enough to accommodate the solder ball 30. Thus, the typical platform 25, occupying approximately 30% of the die surface area, also consequently results in a reduction in the maximum light output.

It should be noted that the configuration shown in fig. 1 is not optimized from the point of view of current spreading in the layer 22. Ideally, the n-type contact should provide uniform current flow throughout the active layer 23. However, the configuration as shown in fig. 1 produces non-uniform current flow, where the area closest to the platform receives more current than the area further away from the platform.

In addition, the light emitted from the light emitting diode 20 needs to exit through the substrate 21. The choice of material for the substrate 21 is limited by the lattice constant of the material used for the layer 22, and the material of the layer 22 is determined by the desired light spectrum to be generated by the led 20.

Referring now to fig. 2-4, a light emitting diode of the present invention is illustrated. Fig. 2 is a top view of a light emitting diode 40, fig. 3 is a cross-sectional view of the light emitting diode 40 taken along line 3-3 in fig. 2, and fig. 4 is a bottom view of the light emitting diode 40. The LED 40 can be considered to comprise two main parts, a light emitting portion 58 and a base portion 59, bonded together. It should be noted that the led 40 is a vertical type device, and therefore, the above-mentioned lateral type device problem can be avoided.

The light emitting section 58 includes an n-type layer 41 and a p-type layer 42 sandwiching an active layer 43, and generates light when holes and electrons are injected from the layer 42 and the layer 41, respectively, into the active layer 43 and combine. As described above, each of these layers may include some sub-layers; however, these sub-layers are not the focus of the present invention, so their function is not described in detail here. Electrical energy is applied between the layers 41 and 42 through electrodes 45 and 44, respectively. In order to prevent the light emitting portion 58 from contacting the ambient environment, a transparent insulating layer 49 is used to cover the light emitting portion 59.

The base 59 can be considered to provide some metal wiring on or through the insulating substrate 48. The base 59 provides two functions. First, base 59 provides a connection for electrodes 44 and 45 to coplanar contacts 51 and 52, respectively, on the bottom of led 40. The present invention connects the metal layer 53 to the contact 51 through a vertically oriented metal wire 46 to achieve the connection between the electrode 44 and the contact 51. The metal layer 53 is bonded to the electrode 44.

The connection between electrode 45 and contact 52 is provided by a metal filled via 47. It should be noted that electrode 45 may also be a metal filled via. The metal filled via 45 extends through the light emitting portion 58 and the metal filled via 45 is isolated from the active layer 43 and p-type layer 42 by a layer of insulating material shown at 57.

The base 59 also provides a support structure for the light emitting diodes 40. The thickness of the typical light emitting portion 58 is less than 5 micrometers (μm). Therefore, when the light emitting diode 40 needs to be handled and bonded to many products by attaching the light emitting diode 40 thereto, the light emitting part is often too weak to survive. The base 59 typically has a thickness of about 100 μm.

In addition, the base portion 59 provides a large enough bonding pad (mounting pads) to allow the LED 40 to be surface mounted to a printed circuit board or the like. As discussed in detail below, the cross-sectional area of the electrode 45 is as small as possible. Therefore, some precision is required for the alignment (alignment) of the electrodes 45 and 47. As discussed in detail below, the desired accuracy may be provided by using a separate base that may then be attached to the printed circuit board with less accuracy.

As described above, the size of the electrode 45 is as small as possible. The portion of the light-emitting portion consumed by electrode 45 cannot produce a significant amount of light emission that escapes from the top surface of the light-emitting diode 40. Therefore, minimizing the cross-sectional area of the electrode 45 maximizes the total light output. However, based on one of multiple considerations, the electrode 45 must be larger than some minimum size. First, the diameter of the channel (via) through layers 41-43 has a minimum dimension that is dictated by the etch system used to construct the channel. Generally, a maximum aspect ratio (aspect ratio) can be obtained from the channel opening process. The aspect ratio is typically less than 10: 1. That is, the channel cannot have a depth more than 10 times its diameter. In this embodiment of the invention, the depth of the channel is the thickness of the layers 41-43, as mentioned above, which is approximately less than 5 μm. Thus, the channel may be less than 1 μm.

The second consideration is the resistance of the electrode 45. In high power leds, electrode 45 is required to conduct a current greater than 350mA without requiring a significant voltage difference. Since the resistance of the conductive path is inversely proportional to the channel cross-sectional area, the required current imposes another restriction on the cross-sectional area of the electrode 45. To some extent, this limitation can be overcome by using a metal with higher conductivity, such as copper or gold; however, the cross-sectional area of the channel still has a lower limit. In high current applications, the channel is typically larger than 50 μm.

A method of manufacturing a light emitting diode according to an embodiment of the present invention will be discussed in detail as follows. As described above, a light emitting diode according to the present invention can be regarded as a light emitting portion and a base portion bonded together. Referring now to fig. 5 and 6, a method of fabricating the light emitting diode is illustrated. Fig. 5 is a top view of a portion of a wafer 60 having a plurality of leds. Exemplary light emitting diodes are shown at 68 and 69. Fig. 6 is a cross-sectional view of a portion of the wafer 60 along line 6-6 of fig. 5.

First, the n-type layer 73, the p-type layer 71 and the active layer 72 are deposited on a substrate 75. Thereafter, a metal layer is deposited over the p-type layer and patterned to provide the p-type electrode 64. The metal layer may comprise multiple sublayers providing different functions such as solderability (solderability) and adhesion (adhesion). In addition, proper selection of the materials of the sublayers may allow an electrode to act as a highly reflective mirror. Since these structures are well known and not central to the present invention, they will not be discussed in detail here. The reader is referred to U.S. patent nos. 6,552,359, 5,585,648, 6,492,661 and 6,797,987 for a detailed understanding of these functions.

These semiconductor layers are then etched to provide boundary regions 61 and channels 62. These border regions 61 separate the different leds and include scribe lanes (scribes lanes) for separating the final product. The channels 62 are lined with an insulating material 66. These border areas 61 may also be lined with insulation as shown at 67. The gasket layer of these border areas 61 is optional. The present invention simplifies the process by reducing the number of masking steps used to prevent the insulating material from entering the boundary region and including this liner layer. After the insulator deposition, the top surface of the light emitting portion may be planarized to facilitate bonding to the base portion if a relatively flat surface is required for the bonding process. Chemical Mechanical Polishing (CMP) can be used to provide a relatively flat surface, if desired.

Referring now to fig. 7 and 8, a method of manufacturing the base is illustrated. Fig. 7 is a top view of a portion of the base 80, and fig. 8 is a cross-sectional view taken along line 8-8 of fig. 7. The base may be constructed on any suitable substrate 81. As in the above example, the base does not contain any electronic components other than the conductors for connecting to the electrodes on the bottom surface of the base. Thus, any insulating substrate can be used as long as it provides the required structural strength and provides a surface upon which the conductors can be fabricated. However, embodiments in which the base includes circuit elements may also be constructed. In this case, the substrate is determined according to the properties of the circuit elements to be included and the manufacturing method of the circuit elements. For example, silicon substrates are attractive candidates for use in circuit devices on a silicon substrate.

The base 80 includes electrodes on its top and bottom surfaces that are connected together by vertically running conductors. The vertical conductors are typically fabricated by etching a via extending from the top surface to the bottom surface of the substrate 81 and filling in a suitable conductive metal. The electrodes on the top surface of the base portion 80 provide connections to corresponding electrodes on the light-emitting portion. Typically, there are two types of electrodes for each light emitting diode. These electrodes are shown at 82 and 83 in the figure. As will be described in more detail below, electrode 83 provides a connection to the n-type layer of the light emitting diode and electrode 82 provides a connection to the p-type layer. The area between the electrodes on the top surface of the base may optionally be filled with an insulating material as shown at 86 and 87. If the area between the electrodes 82 and 83 is filled with an insulator, the embodiment shown at 87 can be easily constructed because the same process steps can be used to fill the area with an insulating material. After the insulator is deposited, the top surface of the base 80 may be planarized, optionally using a process such as chemical mechanical polishing. Whether or not the surface needs to be planarized depends on the extent to which the process of bonding the base portion to the light-emitting portion can accommodate the uneven surface.

As described above, the electrodes described on the top surface of the base 80 are connected to the corresponding electrodes described on the bottom surface. Electrode 82 is connected to electrode 85 via a plugged metal via 88. Electrode 83 is preferably the top surface of a plugged metal via 89, the plugged metal via 89 being connected to electrode 84 at the bottom surface. The electrodes are shown in dashed lines in fig. 7 for the sake of clarity of the shape of said electrodes on the bottom surface.

In one embodiment, the base is constructed from a conventional silicon wafer thinned to a desired thickness. In this embodiment, the via openings are first etched in the wafer using Reactive Ion Etching (RIE). A thermal oxidation process is used to form a silicon dioxide insulating layer covering the entire exposed surface of the silicon wafer including the via openings. A small amount of metal is deposited on the surface of the via opening to form a plating layer on the metal to increase the thickness of the vertical via conductor. Although the via openings need not be completely filled with metal, they may be filled with metal. The typical metal used in the present invention to coat these via openings is copper. Because the plating process creates an uneven surface around the via openings, the surface of the wafer needs to be planarized using chemical mechanical polishing. The chemical mechanical polishing does not remove the silicon dioxide insulating layer. After planarization, the top and bottom patterned metal layers are deposited on the oxide layer.

It should be noted that the via openings need not be completely filled with metal. A metal layer lining the interior of the via openings and having a sufficient thickness to provide vertical connection of the metal layers on the top and bottom surfaces of the base.

The light emitting portions and base portions are prepared at a wafer level. The light emitting portion and base portion are then bonded together and further processing is performed on the light emitting portion to complete the electrical connection with the base portion.

Reference is now made to fig. 9, which is a cross-sectional view of a portion of the light emitting section and base section before bonding, as described above. The light-emitting portion is placed upside down so that the channel shown at 62 in the figure is positioned above one end of the electrode 83. The electrodes shown at 64 in the figure on the light-emitting section 60 are positioned adjacent to the corresponding electrodes 82 on the base section.

Referring now to fig. 10, a cross-sectional view of the base portion and the light emitting portion after bonding. The electrodes on each section are joined to corresponding electrodes on the other sections. Any suitable means of engagement may be used with the present invention. The bonding operation is preferably performed at the wafer level. Wafer level bonding techniques are well known and, therefore, will not be discussed in detail herein. It should be noted that thermal compression bonding (thermocompression bonding) techniques are well suited for bonding these portions of the present invention. These techniques involve pressing the two parts together and heating so that the corresponding metal pads on each part are bonded. Thermal compression bonding (thermocompression bonding) has been described for bonding pads constructed of copper, gold, and aluminum. In addition, the region corresponding to the insulator has a planar surface and is juxtaposed to other planar insulator surfaces where the insulator is constructed of silicon dioxide. Finally, bonding techniques may be applied to cover one of these surfaces with an appropriate solder ball.

Referring now to FIG. 11, a cross-sectional view of a light-emitting portion and a base portion after bonding and removing a substrate 75 is shown. The manner in which the substrate 75 is removed generally depends on the composition of the substrate 75. Gan leds built on sapphire (sapphire) emit light at a wavelength that is not absorbed by sapphire but is strongly absorbed by gan, so that it impinges on the gan layers through a sapphire substrate, which may be separated from the gan layers. Energy from this light source is concentrated at the gan-sapphire junction, causing the gallium atoms to liquefy along the sapphire junction. Thereafter, the sapphire substrate may be separated from the gallium nitride layer while the gallium nitride layer remains attached to the base. This process is known as laser lift off and is described in U.S. patent nos. 6,071,795, 6,420,242 and 5,335,263. The process is suitable for use in light emitting sections constructed from AlGaAs, AlInGaP, AlInGaN, or GaAsP. It should be noted that the thickness of the semiconductor portion in this element is less than 10 μm.

Referring to fig. 11, when the substrate is removed by Chemical Mechanical Polishing (CMP), portions of the n-type layer 73 are also removed leaving the channel openings open. If the substrate is removed using the laser lift off method described above, the insulating layer blocking the open ends of the channels must be removed using an additional process step. For example, the layer 73 must be masked and an etchant applied to remove the end portions of the insulator. In addition, the invention can also apply chemical mechanical polishing on the exposed layer to remove the insulator at the opening end of the channel. Any suitable method that preserves the insulator on the regions corresponding to the active layer and the p-type layer may be employed.

After the via openings for connecting the n-type electrode are opened again, a metal is deposited in the insulating via openings in the gan to complete the connection between layer 73 and electrode 83 as shown at 95. The openings of the border areas 96 may optionally be filled with metal or a photoresist layer for deposition of the metal connections 95. In an embodiment, the openings of the border areas remain open during the final metallization process. A transparent insulator layer is then deposited overlying layer 73. The layer then fills the border regions 96 to provide the cladding layer (encapsulation layer) as shown at 49 in fig. 3. To facilitate dicing of the wafer into individual dies, the boundary regions 96 along the dicing streets may be left uncoated.

Refer back to fig. 3. Electrode 45 provides electrons to layer 41 and electrode 44 provides holes during operation of light emitting diode 40. The current is ideally uniformly diffused so that the electrons and holes are uniformly distributed over the surface of the active layer 43. This is accomplished substantially by injecting holes into layer 42 through electrode 44, since electrode 44 covers most of the surface of layer 42. In contrast, electrode 45 covers only a small portion of the surface of layer 41, and thus the electron distribution in layer 41 is substantially smaller than desired.

In one embodiment of the present invention, this problem is solved by a top electrode comprising a plurality of thin spokes that distribute the current uniformly over the surface of the layer 41. Referring now to fig. 12, therein is a top view of a light emitting diode according to another embodiment of the present invention. The led 100 has a top layer 101 similar to layer 41 described above. The electrode 102 is connected to the light-emitting layer through a metal filled via 103 in the center of the layer 101. A plurality of thin electrodes 102 extend outward from the metal filled vias 103 to provide direct current paths to other portions of layer 101. Since light is emitted from the layer 101, the size of the spokes and their number are selected to minimize light loss due to light reflection or light absorption by the spoke metal. Although the thin electrodes are arranged in a radial pattern, it should be noted that other patterns may be used that allow the electrodes to not block too much of the surface area while spreading the current uniformly. In one embodiment of the present invention, the light emitting surface area occupied by the thin electrode is less than 20% of the light emitting area.

The above-described embodiments of the present invention employ a configuration in which the n-type layer is located on the top surface of the entire wafer and light is emitted from that surface. This configuration conforms to most commonly used methods for fabricating light emitting diodes in which the n-type layer is deposited first on the substrate to minimize the problem of diffusion of the p-type dopants into other layers.

This configuration is advantageous in view of the fact that in many material systems the p-type layer has a greater resistance than the n-type layer, and current diffusion to provide the active layer a uniform charge density is a greater problem for the p-type layer. As mentioned earlier, in the above embodiments, the p-type layer contacts the larger top electrode, and thus there is no significant problem of non-uniform current flow through the layer.

However, other led configurations may be employed with the present invention. To simplify the following discussion, the layer is defined as the top layer of the light emitting diode if light is emitted from the layer, and the layer connected to the base is defined as the bottom layer. The above definition is independent of the doping of these particular layers. For example, in some material systems used to fabricate light emitting diodes, the p-type layer may be deposited first without significant diffusion problems. In this example, the top layer would be the p-type layer.

In the above embodiments of the present invention, the led is a simple three-layer device, in which the active layer is sandwiched between a p-type layer and an n-type layer. In practice, each of the three layers may comprise multiple layers comprising different alloy compositions and different doping levels to improve characteristics such as light output, ohmic contact, efficiency and current spreading. These structures are well known to those skilled in the art.

In the above embodiments of the present invention, the led is a simple three-layer device, in which the active layer is sandwiched between a p-type layer and an n-type layer. This structure is commonly referred to as a p-i-n diode. As described above, in many material systems, the p-type layer causes current spreading and resistance problems. It should be noted that the n-type and p-type layers can be considered as resistors that would lose power, and the lost power would not generate any light. Thus, the high resistance layer results in low efficiency and high operating temperature. Many sophisticated light emitting diode designs attempt to minimize the thickness of the p-type layer to alleviate these problems. In these devices, the other layers of the device are n-type layers to provide better current spreading. Since such light emitting diodes are known to those skilled in the art, they will not be discussed in detail herein. It should be noted that a tunnel diode junction (a tunnel diode junction) is introduced into the led body to provide an a transition of p-type layer. That is, the light emitting diode has an n-p-i-n structure in which the n-p junction is a reverse biased tunneling diode and the p-type layer is relatively thin. Since the current spreading function is achieved by the n-type layer, the p-type layer can be relatively thin, and therefore the problems associated with the high resistance of p-type materials can be significantly alleviated. Proper selection of materials and dopants shows that the loss caused by the tunnel junction is greater than that obtained by increasing current diffusion and reducing device resistance.

In the above embodiments of the present invention, a metal filled via is formed to extend from the top surface of the led to the bottom surface of the led through the led to connect the top layer of the light emitting portion to an electrode corresponding to the top surface of the base portion, and then to a pad on the bottom surface of the base portion. However, other modes of connecting the top layer of the led to an electrode on the bottom surface of the base can be used.

Referring now to fig. 13 and 14, therein are shown light emitting diodes according to another embodiment of the present invention. Fig. 13 is a top view of a light emitting diode 200, and fig. 14s is a light emitting diode of an embodiment. Fig. 13 is a top view of a light emitting diode 200, and fig. 14 is a cross-sectional view of the light emitting diode 200 taken along line 14-14 in fig. 13. Light emitting diode two is shown in cross-section of light emitting diode 200 along line 14-14 in fig. 13. The led 200 includes a light emitting portion 210 and a base portion that perform similar functions as described above with respect to the led 40. Light-emitting section 210 includes an active region 212 sandwiched between a p-type layer 213 and an n-type layer 211. Electrode 217 provides electrical contact to layer 213 and electrode 217 is deposited on the surface of layer 213. Electrode 215 provides electrical contact to layer 211, and electrode 215 is deposited on the surface of layer 211 after the light-emitting portion has been bonded to base portion 220.

The base 220 comprises a plurality of electrodes deposited on an insulating substrate 221. Electrodes 223 and 224 provide contacts to connect electrodes 217 and 215 to an external circuit. The electrode 214 is deposited on the substrate 221 before the light-emitting section 210 is bonded to the base section 220. Electrode 214 bonds the two parts together and provides part of the electrical path to connect layer 213 to electrode 223. The remainder of this electrical path is provided by a vertical conductor 222. Similarly, a vertical conductor 218 is used to complete the connection between electrode 215 and electrode 224.

A method of fabricating a light emitting diode having the configuration of light emitting diode 200 will be discussed in detail below. Referring first to fig. 15 and 16, a portion of a base wafer 240 is illustrated ready for bonding to a light emitting portion wafer. Fig. 15 is a top view of a wafer 240, and fig. 16 is a cross-sectional view of a portion of the wafer 240 showing three elemental devices 241-243 along line 16-16 of fig. 15. The wafer 240 is constructed on an insulating substrate 250. The deep trenches shown at 252 are first etched and metallized to provide electrical connections to the top and bottom surfaces of substrate 250. Optionally, the trenches may be completely filled with metal. The examples shown in these figures, the cross-section of the trenches is rectangular; however, other shapes may be employed. After the trenches are etched, patterned metal layers 251 and 257 are deposited on the top and bottom surfaces of substrate 250 to provide the various electrodes for the base of each device.

The method of fabricating the light emitting portion is similar to that of fig. 5 and 6 and, therefore, will not be discussed again. It should be noted that in this embodiment, the channel shown at 62 in fig. 5 and 6 is not fabricated.

Referring now to fig. 17-20, a method of fabricating a light emitting diode having the structure of light emitting diode 200 is illustrated. A wafer having light emitting portions is initially bonded to a wafer having base portions. Fig. 17 shows two wafers that have been aligned but still separated and not yet bonded. The light emitting wafer 270 includes an active layer 274 sandwiched between a p-type layer 273 and an n-type layer 272 that have been deposited onto a substrate 271. Light emitting wafer 270 also includes a patterned electrode layer 275 that provides an electrical connection to layer 272. Trenches 276 have been etched through layers 272-275.

The two wafers are such that the electrodes 275 and 251 in each led are bonded together and the gap pairs between the electrodes 251 are located in the trenches shown at 276. Note that in each device, a portion of trench 252 is located under a portion of electrode 251, as shown at 281, such that trench 252 is electrically connected to electrode 251 at the location shown at 281. The remaining portion of trench 252 does not contact electrode 251, and thus, a non-conductive gap 282 is formed between trench 252 and the corresponding portion of electrode 251 of the wafer adjacent to the device. Reference is now made to fig. 18. After the wafers are bonded, the substrate 271 is removed and the trenches 276 are filled with an insulator such as SiO2 as shown at 277. A trench 278 is etched in insulator 277 as shown in fig. 19. The trench is located above a portion of trench 252. Trench 278 may extend the length of trench 252 or only a portion of that length. Thereafter, a patterned electrode 279 is deposited over portions of layer 272, as shown in FIG. 19. Electrode 279 also extends into trench 278. Optionally, one or more additional layers of transparent material may be applied over the wafer to protect the top surface. These layers are omitted to simplify the drawing.

In the final step of the process, the components are separated by dicing the bonded wafer. In one embodiment, the elements are cut along cut line 285 as shown in FIG. 20. This cut separates trench 252 into two vertically oriented electrodes 287 and 288. Electrode 287 becomes electrode 222 in fig. 14 and electrode 288 becomes electrode 218 in fig. 14.

Referring now to fig. 21, a top view of a partially bonded wafer is shown prior to dicing. As described above, the top electrode 279 can comprise a plurality of linear conductors 291 that spread current to the top surface of the light emitting element.

In the above embodiment, an insulating layer prevents the bottom layer from shorting to the vertical conductors that connect the base portion to the top layer of the device. In one embodiment discussed above, the insulating layer extends to the top surface of the top layer. It should be noted, however, that the insulating layer need not extend to the top surface. The invention can be operated as long as the insulating layer covers part of the bottom layer and the active layer, so that the vertical conductor can not be short-circuited with any of the other layers.

Although the present invention is discussed with respect to light emitting diodes as the light emitting devices, the devices used in embodiments of the present invention to be bonded to the base may be constructed of different integrated circuits or circuit components. To simplify the following discussion, the integrated circuit is defined to include devices that are made up of a single circuit element. The invention is particularly useful where the device needs to be bonded to the base, which requires a first contact at the top surface of the device and a second contact at the bottom surface of the device, and the device has one or more layers that need to be protected from shorting to the conductor when the conductor is connected to the upper surface of the device. For example, a vertical surface emitting laser (VCSELs) has a similar structure, and thus a surface mountable VCSELs can be provided in accordance with the present invention that engage a base.

It should be noted that the base area of a device according to the present invention is sized to approximate the area of the end product and, therefore, the end products can be placed more closely as compared to integrated circuit devices comprised of dies or wafers in conventional integrated circuit packages. The invention is particularly useful for providing a surface mountable wafer wherein the base twice the area is less than the top surface area of the integrated circuit wafer or die.

Particularly useful elements for the construction of the invention are those in which the circuit arrangement is constructed of AlGaAs, AlInGaP, AlInGaN, or GaAaP family materials that can be placed on a silicon or ceramic substrate. As described above, the gallium nitride element layer can be separated from the sapphire substrate thereunder by a laser irradiation method. Furthermore, silicon substrates provide sufficient heat transfer and are therefore suitable for high power components.

The embodiments of the present invention described above can be directly viewed as a circuit device having two electrodes, one on the bottom surface and one on the top surface. In this example, the base also contains two corresponding electrodes that are connected to the electrodes of the circuit device and terminate in pads on the bottom surface of the final wafer. However, devices having more than two device electrodes and more than two pads on the bottom surface of the base portion can also be constructed.

As described above, the embodiments of the present invention employ a single layer of electrodes over the led and on the top surface of the base layer. However, embodiments having one or more of the electrodes comprising multiple layers may also be constructed. Furthermore, the multilayer may also comprise insulating sub-layers with different spatial patterns which are connected in the layers by vertical connections. For example, the layers are useful for the light emitting diode having contacts located elsewhere on the surface that are wired to the base layer rather than directly beneath the contacts.

Furthermore, these layers are useful for the case where the vertical links have very large diameters. If a thick base is used, the minimum size of the vertical channels may be set by the etching process used to form the channels. Since these processes limit the aspect ratio (aspect ratio) of the etched holes, and typically also limit the 1/4 where the channel diameters are larger than the depth of the channel hole, the size of the channel top surface can be relatively large to limit the size and location of the bottom electrode of the light emitting diode. This problem can be alleviated by covering the top surface of the base with a thin insulating layer having a smaller via over one end of a larger metal filled via. An electrode of the desired size and position may then be deposited on the insulating layer.

Referring now to fig. 22, therein is a cross-sectional view of a light emitting diode according to another embodiment of the present invention. The light emitting diode 300 includes a light emitting portion 310 similar to the light emitting portion described above. The connection of layer 313 is provided by electrode 311, and electrode 311 is connected to vertical conductor 312. To simplify the drawing, the insulating layer in the channel with the vertical conductors 312 passing through has been omitted. The cross-sectional area of vertical conductor 312 preferably has a small cross-sectional area, but still retains the ability to provide electrical connection to layer 313.

Electrode 311 is connected to bottom electrode 323 by metal filled via 322. As described above, the minimum diameter of the channel is determined by the thickness of the layer through which the channel is etched. The light emitting portion 310 is generally much thinner than the base portion 320. For example, the light emitting part 310 may be 10 micrometers (μm). In contrast, the base 320 must be thick enough to prevent fracture of the final part, and therefore typically has a thickness greater than 100 microns. Thus, the width of channel 322 is typically much greater than channel 312. In some cases, vias 322 are so wide that the size of electrode 314 needs to be limited to prevent shorting to the metal in vias 322. However, it is better to have the electrode on the bottom surface of the light emitting section as large as possible to optimize current spreading within the light emitting section. The embodiment of fig. 22 overcomes this problem by employing a three-layer top electrode 325, wherein the three-layer top electrode 325 has two patterned metal layers separated by an insulating layer 326. The upper metal layer is patterned to provide electrodes 328 and 329. Electrode 328 provides a connection to via 322 through a small channel in layer 329, and thus provides a transition from via 312 to via 322 without placing much restriction on the size of electrode 314. Electrode 329 provides a connection between electrode 314 and electrode 332 via electrode 331, which electrode 331 is an underlying patterned layer of electrode 325.

The above-described embodiments of the present invention utilize metal-filled vias to implement the vertical conductors. However, other types of vertical conductors may be employed. For example, vertical conductors with appropriate silicon doping may also be employed. These structures are conventional and, therefore, will not be discussed in detail herein.

Various modifications can be made by those skilled in the art in light of the foregoing description and accompanying drawings. Accordingly, the invention is to be limited solely by the scope of the following claims.

Claims (17)

1. A surface mountable light emitting device includes a circuit device and a base,

the circuit device comprises a multi-layer semiconductor layer having a top layer and a bottom layer, the top layer comprising a top surface having a top contact on the top surface and the bottom layer having a bottom surface and a bottom contact on the bottom surface, a potential difference being required to be applied across the top contact and the bottom contact to operate the circuit device; and

the base portion comprises a substrate having a base top surface and a base bottom surface, the base top surface being bonded to the bottom layer and the base bottom surface comprising a first bottom electrode and a second bottom electrode electrically isolated from each other, the bottom contact being connected to the first bottom electrode by a first conductor and the second bottom electrode being connected to the top contact by a second conductor;

wherein the circuit device comprises an insulating layer bonded on a surface of the multi-layer semiconductor layer and wherein the second conductor comprises a metal layer bonded to the insulating layer, the insulating layer preventing contact of the second conductor with the underlying layer.

2. The device of claim 1 wherein said base portion comprises a top electrode bonded to said base portion top surface, said first conductor comprises a conductor connecting said top electrode to said first bottom electrode.

3. The device of claim 2, wherein the circuit device comprises a light emitting device comprising an active layer, and a first semiconductor layer and a second semiconductor layer, the active layer being between the first and second semiconductor layers, the first semiconductor layer having a top surface comprising the top contact and the second semiconductor layer having a bottom surface comprising the bottom contact, holes and electrons combining in the light emitting device to generate light when a potential is applied between the top contact and the bottom contact.

4. The device of claim 3 wherein the circuit device comprises AlGaAs, AlInGaP, AlInGaN, or GaAsP.

5. The device of claim 1, wherein the substrate comprises a silicon wafer or a ceramic material.

6. The device of claim 3, wherein the light-emitting device comprises a light-emitting diode.

7. The device of claim 3 wherein the light emitting device comprises a laser diode.

8. The device of claim 3, wherein said light emitting device comprises a conductive path extending from said top surface of said first semiconductor layer to said bottom surface of said second semiconductor layer, said conductive path comprising a metal layer electrically insulated from said second semiconductor layer and said active layer by said insulating layer and said active layer.

9. The device of claim 3, wherein said first semiconductor layer, said active layer, and said second semiconductor layer comprise outer surfaces and wherein said insulating layer comprises an insulating layer bonded to said outer surfaces.

10. The device of claim 3, wherein said top contact covers less than 20% of said first semiconductor layer.

11. The component of claim 1 wherein the circuit device thickness is less than 10 microns.

12. The device of claim 1 wherein said bottom contact comprises a mirror.

13. The device of claim 1 wherein said second conductor comprises a metal conductive path connecting said base top surface to said second bottom electrode.

14. The device of claim 1 wherein the second conductor comprises a metal layer bonded to an outer surface of the substrate.

15. The device of claim 1, wherein the first conductor comprises a metal layer bonded to another surface of the substrate.

16. The device of claim 2, wherein said first conductor comprises a metal conductive path connecting said top electrode to said first bottom electrode.

17. The device of claim 3, wherein said bottom surface of said base has an area less than twice said top surface area of said second semiconductor layer.