HK1135229B - Method for reducing charge loss in analog floating gate cell - Google Patents

Description

Method for reducing charge loss in analog floating gate cells

RELATED APPLICATIONS

This application relates to and claims priority from U.S. provisional patent application No.60/868,456 filed on 12/4 of 2006 by Radu a.

Technical Field

The present invention relates to the field of non-volatile programmable integrated circuits using standard CMOS technology.

Background

The floating gate reference circuit generates a reference voltage in response to charge stored on a floating gate of the non-volatile memory transistor. Typically, the non-volatile memory transistor is programmed by programming a thin oxide of the capacitor. However, when a bias voltage is applied for a long time (especially at a high temperature), charges may leak through the thin oxide, undesirably affecting the generated reference voltage. Accordingly, it is desirable to have a circuit for accurately programming non-volatile memory transistors in a floating gate reference circuit and then maintaining the programmed charge for a long period of time.

Disclosure of Invention

Accordingly, the present invention provides a voltage reference circuit that provides a single-ended reference voltage in response to a programmed threshold voltage of a first non-volatile memory (NVM) transistor. Initially, the threshold voltage of the first NVM transistor is programmed through a tunneling capacitor that shares a floating gate with the first NVM transistor. The floating gate is separated from the programming terminal (i.e., commonly connected source/drain regions) of the tunneling capacitor by a thin oxide layer. The threshold voltage of the first NVM transistor is programmed by applying a programming voltage to a programming terminal of the tunneling capacitor, thereby inducing Fowler-Nordheim tunneling through the thin oxide layer.

During normal operation of the voltage reference circuit, the first NVM transistor is connected in a current mirror configuration with the second NVM transistor. A differential amplifier having inputs coupled to the drains of the second NVM transistor and the first NVM transistor provides a reference voltage as an output. Further, during normal operation, the programming terminal of the tunneling capacitor is connected to a semiconductor structure (e.g., a third NVM transistor) that is configured to have the same electrical and thermal characteristics as the floating gate of the first NVM transistor. As a result, during normal operation, the voltage at the programming terminal remains substantially equal to the voltage of the floating gate of the first NVM transistor over a wide range of operating conditions, thereby minimizing charge loss through the tunneling capacitor.

The present invention will be more fully understood in view of the following embodiments and the accompanying drawings.

Drawings

FIG. 1 is a circuit diagram of a portion of a CMOS floating gate voltage reference circuit, according to one embodiment of the present invention.

FIG. 2 is a partial circuit diagram of the CMOS floating gate voltage reference circuit of FIG. 1 configured to set the threshold voltage of the NVM transistors according to one embodiment of the present invention.

FIG. 3 is a partial circuit diagram of the CMOS floating gate voltage reference circuit of FIG. 1 configured to perform an erase operation on NVM transistors according to one embodiment of the present invention.

FIG. 4 is a partial circuit diagram of the CMOS floating-gate voltage reference circuit of FIG. 1 configured to program NVM transistors according to one embodiment of the present invention.

FIG. 5 is a partial circuit diagram of the CMOS floating gate voltage reference circuit of FIG. 1 configured in a normal mode of operation according to one embodiment of the present invention.

FIG. 6 is a circuit diagram of a portion of a CMOS floating gate voltage reference circuit according to an alternate embodiment of the present invention.

Detailed Description

FIG. 1 is a circuit diagram of a portion of a CMOS floating gate voltage reference circuit 100 according to one embodiment of the present invention. The circuit 100 includes a p-channel MOS transistor 101-.

In general, CMOS floating-gate voltage reference circuit 100 generates a reference output voltage V at the output of comparator 115_OUTThe input of comparator 115 is coupled to the drains of NVM transistors 104 and 105. Initially, capacitor 109 (i.e., floating gate 125 of NVM transistor 105) is programmed with the desired charge while controlling the voltage applied to the control gate and floating gate of NVM transistor 104. After programming is complete, of comparator 115The output is fed back to the control gate and floating gate of NVM transistor 104 to produce an output reference voltage V_OUT. In one embodiment, the CMOS voltage reference circuit 100 uses two NVM transistors, where the floating gate of one of the NVM transistors is discharged (by, for example, UV irradiation) while the floating gate of the other NVM transistor is programmed with the desired charge. In another embodiment, a complete CMOS voltage reference circuit may be implemented as described in commonly owned U.S. patent application No.11/355,394 or commonly owned U.S. patent application Ser. No. 11/611,665.

Non-volatile memory transistors 104, 105, and 106 include floating gates 124, 125, and 126, respectively, and control gates 134, 135, and 136, respectively. NVM transistors 104-106 have the same geometry and lateral (transversal) structure. The body region of NVM transistor 104 and 106 is grounded. Each of the non-volatile memory transistors 104-106 has a standard double polysilicon gate structure with a dielectric thickness large enough (e.g., greater than 100 angstroms) to prevent charge leakage from the floating gate 124-126. In one embodiment, each of the floating gates 124-126 is separated from the corresponding control gate 134-136 by a dielectric having an effective silicon dioxide thickness of about 150-250 angstroms. The dielectric may be a sandwich structure of, for example, silicon oxide/silicon nitride/silicon oxide (ONO). The control gates 134 and 135 of memory transistors 104 and 105 are capacitively coupled to their respective floating gates 124 and 125 by the dielectric. Due to considerations disclosed below, the control gate 136 and floating gate 126 of NVM transistor 106 are electrically shorted to the drain of NVM transistor 106 for reasons that will be explained.

A capacitor 109 having a capacitance value C1 is coupled between floating gate 125 and control gate 135 of non-volatile memory transistor 105. Capacitor 109 increases the capacitive coupling to floating gate 125 and also helps to reduce the required programming voltage.

Tunneling capacitor 107 is formed from a floating gate transistor having commonly coupled source and drain regions, a control gate in common with control gate 135 of NVM transistor 105, and a floating gate in common with floating gate 125 of NVM transistor 105.

In the depicted embodiment, tunneling capacitor 107 has a thin dielectric (about 60-120 angstroms of effective silicon dioxide) that can conduct current at high voltage biases in the range of about 6 to 12 volts. As described in more detail below, a tunneling current passes through the thin dielectric of tunneling capacitor 107 to floating gate 125, thereby changing the threshold voltage of non-volatile memory transistor 105 to a desired level. More specifically, tunnel capacitor 107 allows floating gate 125 to be electrically charged by Fowler-Nordheim conduction by applying a large voltage (of either polarity) across the thin dielectric of tunnel capacitor 107. Such physical processes are well known to those skilled in the art of EEPROM memory devices.

The sources of the non-volatile memory transistors 104 and 106 are commonly connected to the drain of an n-channel transistor 108. The source of N-channel transistor 108 is coupled to ground and the gate of N-channel transistor 108 is coupled to receive the BIAS signal N-BIAS from BIAS control circuit 140. The drains of non-volatile memory transistors 104, 105, and 106 are coupled to the drains of p-channel transistors 101, 102, and 103, respectively. The source and body regions of p-channel transistor 101-103 are commonly connected to V_DDA voltage source terminal. The gates of p-channel transistors 101 and 102 are commonly connected to the drain of p-channel transistor 102. Thus, p-channel transistors 101 and 102 are arranged in a current mirror configuration. In the described embodiment, the p-channel transistors 101 and 102 are the same transistor. As a result, the p-channel transistors 101-102 and the non-volatile memory transistors 104-105 form two matched circuit branches.

The gate of P-channel transistor 103 is coupled to receive the BIAS signal P-BIAS from BIAS control circuit 140. The drain of p-channel transistor 103 and the drain of NVM transistor 106 are coupled to switch 112 at terminal 121. Switches 110 and 111 are configured to selectively couple the control gate 135 of non-volatile memory transistor 105 to ground or erase voltage terminal VPE, respectively. Switches 112, 113, and 114 are configured to selectively couple source/drain regions of tunnel capacitor 107 to terminal 121, programming voltage terminal VPW, or ground, respectively.

The input of differential amplifier 115 is coupled to the drains of p-channel transistors 101 and 102. The output of differential amplifier 115 is coupled to programming logic (not shown) and provides an output reference voltage V_OUTThe reference voltage output terminal.

In general, the circuit 100 operates as follows. Initially, the non-volatile memory transistor 104 is controlled to have a charge close to zero. Fig. 2 is a circuit diagram illustrating setting of floating gate charge of NVM transistor 104 according to one embodiment of the present invention. In this embodiment, the floating gate 124 of the non-volatile memory transistor 104 is initially discharged to a neutral state by Ultraviolet (UV) radiation, such as a UV erase process using standard EEPROM memory processing. Note that the floating gates 125-126 of transistors 105-106 are typically discharged simultaneously with the floating gate 124. However, after the initial discharge ends, the threshold voltage of the non-volatile memory transistor 104 remains substantially the same throughout the operation of the circuit 100. That is, there is no intentional (interfacial) charge transfer in the floating gate 124 or outside the floating gate 124 after the threshold voltage has been set in the non-volatile memory transistor 104.

After the threshold voltage has been set in the nonvolatile memory transistor 104, an erase operation is performed on the nonvolatile memory transistor 105. FIG. 3 is a circuit diagram of an erase operation performed on NVM transistor 105 according to one embodiment of the present invention. The current through N-channel transistor 108 is set to a desired level by the N-BIAS signal before performing the erase operation. The erase operation sets an initial large negative charge (corresponding to a high threshold voltage) on the floating gate 125 of the non-volatile memory transistor 105. To perform the erase step, the output of comparator 115 is coupled to the control gate 134 of NVM transistor 104. Switch 114 is closed and switch 112 is opened 113, thereby applying a voltage of 0 volts to the source/drain regions of tunnel capacitor 107. Switch 111 is closed and switch 110 is opened so that the erase signal applied to erase terminal VPE is coupled to control gate 135 of NVM transistor 105 and tunneling capacitor 107. The erase signal changes from a low voltage of 0 volts to a high voltage of 15 volts. During this operation, the voltage applied across the thin dielectric of tunnel capacitor 107 generates a Fowler-Nordheim tunneling current that charges floating gate 125 with negative charge.

As a result, the threshold voltage of the non-volatile memory transistor 105 is increased to a relatively large value, typically in the range of 2 to 8 volts. The final potential of the floating gate 125 and the corresponding threshold voltage of the non-volatile memory transistor 105 depend on the highest value of the applied erase signal. In this step, the exact threshold voltage of the non-volatile memory transistor 105 is not critical, as the threshold voltage only sets an acceptable initial state before the non-volatile memory transistor 105 is subsequently programmed.

Next, the non-volatile memory transistor 105 is programmed. More specifically, IN a closed loop cycle, the floating gate 125 of non-volatile memory transistor 105 is programmed with a precise positive charge using the voltage applied to the control gate 134 of memory transistor 104 (i.e., the IN pin) as a reference voltage.

Fig. 4 is a circuit diagram for programming NVM transistor 105 according to one embodiment of the present invention. During this programming operation, the output of comparator 115 is decoupled from NVM transistor 104 and reference voltage V is decoupled_REFTo the control gate 134 (i.e., the IN pin) of NVM transistor 104.

Switch 113 is closed and switches 112 and 114 are opened, thereby coupling programming terminal VPW to the source/drain regions of tunnel capacitor 107. Switch 110 is closed and switch 111 is opened, thereby coupling the control gate 135 of NVM transistor 105 and tunneling capacitor 107 to ground. A program signal is applied to the program terminal VPW, wherein the program signal is boosted to a positive value greater than 10 volts. Because control gate 135 is grounded, the voltage applied across the thin dielectric of tunnel capacitor 107 creates a Fowler-Nordheim tunneling current that removes negative charge from floating gate 125. As a result, the threshold voltage of the nonvolatile memory transistor 105 is lowered. Note that the high voltages applied across the tunnel capacitor 107 have different polarities during the erase operation and the program operation.

With moreIs removed from the floating gate 125, the threshold voltage of transistor 105 continues to decrease, resulting in increased current flow through non-volatile memory transistor 105. Programming of non-volatile memory transistor 105 continues until the leakage current through NVM transistor 105 equals the leakage current through memory transistor 104. When the leakage current of NVM transistor 105 becomes greater than the leakage current through memory transistor 104, the output of differential amplifier 115 changes state, thereby signaling the programming logic (not shown) to stop the programming operation (by turning off the programming signal applied to programming terminal VPW). At this point, the threshold voltage of non-volatile memory transistor 105 is programmed to accurately represent the reference voltage V applied to the control gate 134 of NVM transistor 104 during programming_REFThe value of (c).

Thus, a normal operating mode is initiated in which NVM transistors 104 and 105 are coupled to differential amplifier 115 such that differential amplifier 115 outputs reference voltage V_OUTThe reference voltage V_OUTCorresponding to the programmed threshold voltage of NVM transistor 105. In this way, a stable and accurate reference voltage is provided at the low impedance node.

Fig. 5 is a circuit diagram illustrating a normal operation mode according to one embodiment of the present invention. The bias control circuit 140 is shown in more detail in fig. 5. In the illustrated embodiment, BIAS control circuit 140 includes a p-channel transistor 141, an N-channel transistor 142, and an N-BIAS voltage generator 145.

To initiate the normal operating mode, the output of comparator 115 is coupled to the control gate 134 of NVM transistor 104 (and from an external reference voltage V)_REFDecoupling NVM transistor 104). Switch 110 is closed and switch 111 is opened, thereby coupling the control gate 135 of NVM transistor 105 and tunneling capacitor 107 to ground. In addition, switch 112 is closed and switches 113 and 114 are opened, thereby connecting the source/drain regions of tunnel capacitor 107 to terminal 121.

Under these conditions, p-channel transistors 101-102 cause the same current to flow through the drains of NVM transistors 104 and 105, respectively. NVM transistor coupling via differential amplifier 115Any imbalance between the leakage currents of 104 and 105 amplifies. The output of differential amplifier 115 is fed back to the control gate 134 of NVM transistor 104, ensuring that the currents through NVM transistors 104 and 105 are equal and the two floating gates 124 and 125 are held at the same voltage. As a result, the reference voltage V is output_OUTCorresponding to the programmed voltage of the floating gate 125.

By closing switch 112, the source/drain regions of tunneling capacitor 107 are commonly connected to the drain of PMOS transistor 103, the drain of NVM transistor 106, the control gate 136 of NVM transistor 106, and the floating gate 126 of NVM transistor 106. The connection provided by the switch 112 is important for the following reasons.

The thin dielectric of tunnel capacitor 107 is a source of unwanted charge leakage from capacitor 109 when the voltage across the thin dielectric has a value other than 0 volts. The charge loss through the thin dielectric of tunnel capacitor 107 increases with temperature.

To eliminate charge leakage through the thin dielectric of tunnel capacitor 107, switch 112 connects the programming terminal (i.e., source/drain region) of tunnel capacitor 107 to the same potential as floating gate 125 and exhibits the same temperature dependence as floating gate 125. As a result, the same temperature-based voltage change occurs on floating gate 125 and source/drain regions of tunnel capacitor 107. Thus, a zero voltage difference is maintained across the floating gate 125 and the source/drain regions of tunnel capacitor 107 as temperature changes, thereby minimizing charge leakage.

The terminal 121 is provided with the same potential and the same temperature dependence as the floating gate 125 in the following manner. In the bias control circuit 140, the p-channel transistor 141 is the same as the p-channel transistor 101-103, and the n-channel transistor 108 is three times as large as the n-channel transistor 142. As a result, the current flowing through n-channel transistor 142 (and therefore the current flowing through p-channel transistor 141) is equal to one-third of the current flowing through n-channel transistor 108. Because the p-channel transistors 141 and 103 are arranged in a current mirror configuration, the current flowing through the p-channel transistor 103 is equal to the current flowing through the p-channel transistor 141, or equal to one-third of the current through the n-channel transistor 108. Thus, the current through NVM transistor 106 is also equal to one-third of the current through n-channel transistor 108.

The remaining two thirds of the current through n-channel transistor 108 flows through p-channel transistors 101 and 102. As described above, the configuration of these p-channel transistors 101-102 results in substantially equal currents through these transistors. Thus, the current flowing through each of the p-channel transistors 101 and 102 is approximately equal to one-third of the current through the n-channel transistor 108. Thus, substantially equal currents flow through p-channel transistors 101, 102, and 103. Thus, substantially equal currents also flow through the associated NVM transistors 104, 105, and 106.

As described above, NVM transistor 106 has the same geometry and lateral structure as NVM transistors 104 and 105. However, the drain, control gate 136, and floating gate 126 of NVM transistor 106 are electrically shorted. Because floating gate 126 of NVM transistor 106 is the same as floating gate 125 of NVM transistor 105, the electrical and thermal characteristics of these floating gates are substantially the same. Thus, by coupling the source/drain regions of tunnel capacitor 107 to floating gate 126 of NVM transistor 106, the electrical and thermal characteristics of the source/drain regions of tunnel capacitor 107 are substantially the same as the electrical and thermal characteristics of floating gate 125. Keeping the currents through these NVM transistors 105 and 106 equal will cause these NVM transistors to have substantially the same operating conditions.

Under these conditions, a zero voltage drop is maintained between the source/drain regions of tunnel capacitor 107 and floating gate 125, substantially eliminating charge loss from capacitor 109 through the thin dielectric of the tunnel capacitor.

The present invention advantageously increases the accuracy of the programmed reference voltage, increases the stability of the programmed reference voltage over time, reduces the current consumption required to implement the reference voltage circuit, and occupies a small (preserve) total circuit area.

FIG. 6 is a circuit diagram of a portion of a CMOS floating gate voltage reference circuit 600 in accordance with an alternative embodiment of the present invention. Because CMOS floating gate voltage reference circuit 600 is similar to CMOS floating gate voltage reference circuit 100 (fig. 1), similar elements are designated with similar reference numerals in fig. 1 and 6. In the embodiment of fig. 6, the floating gate 124 and the control gate 134 of the non-volatile memory transistor 104 are electrically shorted, effectively making the transistor 104 a standard gate transistor exhibiting a standard threshold voltage. In this embodiment, initially, the floating gate 124 of the transistor 104 need not be discharged to a neutral state by exposure to UV radiation in the manner described above in connection with fig. 2. However, the CMOS floating gate voltage reference circuit 600 can be controlled in a similar manner as described above in connection with FIGS. 3, 4 and 5 to implement erase, program and normal modes of operation, with similar results.

While the invention has been described in conjunction with specific embodiments, it is to be understood that modifications may be made to those embodiments by those skilled in the art. Accordingly, the invention is to be limited only by the following claims.

Claims (19)

1. A method of providing a reference voltage in an integrated circuit, comprising:

programming a threshold voltage of a first non-volatile memory transistor (NVM) through a tunneling capacitor, wherein the first NVM transistor and the tunneling capacitor share a first floating gate and the tunneling capacitor has a programming end separate from the first floating gate; followed by

Coupling the programming end of the tunneling capacitor to a second NVM transistor, the second NVM transistor having a second floating gate and the second floating gate having electrical and thermal characteristics selected to match electrical and thermal characteristics of the first floating gate; and

generating a single-ended reference voltage in response to a programmed threshold voltage of the first NVM transistor while coupling the programming end of the tunneling capacitor to the second floating gate of the second NVM transistor.

2. The method of claim 1, wherein the step of programming the threshold voltage of the first NVM transistor comprises: applying a programming voltage across the programming terminal of the tunneling capacitor and the first floating gate.

3. The method of claim 1, further comprising:

coupling a third NVM transistor in a current-mirror configuration with the first NVM transistor during the step of programming the threshold voltage of the first NVM transistor; and

applying a reference voltage to the third NVM transistor during the step of programming the threshold voltage of the first NVM transistor.

4. The method of claim 3, further comprising:

coupling the first NVM transistor and the third NVM transistor to a differential amplifier during the step of programming the threshold voltage of the first NVM transistor; and

terminating the step of programming the threshold voltage of the first NVM transistor when the output of the differential amplifier switches.

5. The method of claim 3, further comprising: initializing a threshold voltage of the third NVM transistor to a neutral state by discharging a third floating gate of the third NVM transistor prior to programming the threshold voltage of the first NVM transistor.

6. The method of claim 5, wherein initializing a threshold voltage of the third NVM transistor comprises: exposing the third NVM transistor to ultraviolet radiation, i.e., UV radiation.

7. The method of claim 1, further comprising: coupling a third NVM transistor in a current mirror configuration with the first NVM transistor during the step of generating the single-ended reference voltage.

8. The method of claim 7, further comprising: coupling the first NVM transistor and the third NVM transistor to inputs of a differential amplifier during the step of generating the single-ended reference voltage, wherein the differential amplifier provides the single-ended reference voltage.

9. The method of claim 7, wherein during the step of generating the single-ended reference voltage, a first current flows through the first NVM transistor, the method further comprising: flowing a current equal to the first current through the second NVM transistor during the step of generating a single-ended reference voltage.

10. The method of claim 1, further comprising: erasing the first NVM transistor through the tunneling capacitor prior to programming a threshold voltage of the first NVM transistor.

11. The method of claim 1, wherein the threshold voltage of the first NVM transistor is programmed by Fowler-Nordheim tunneling.

12. A voltage reference circuit for generating a reference voltage, comprising:

a first non-volatile memory transistor (NVM transistor) having a first floating gate configured to store programmed charge, wherein a reference voltage is generated in response to the programmed charge stored on the first floating gate;

a tunneling capacitor sharing a first floating gate with a first NVM transistor, wherein the tunneling capacitor has a programming end separate from the first floating gate;

a second NVM transistor having a second floating gate, and the second floating gate having electrical and thermal characteristics selected to match electrical and thermal characteristics of the first floating gate of the first NVM transistor;

a first switch configured to couple the programming terminal to a second floating gate of the second NVM transistor during a normal operating mode in which the voltage reference circuit generates the reference voltage.

13. The voltage reference circuit of claim 12, further comprising: a second switch configured to couple the programming terminal to a programming voltage during a programming mode in which a programmed charge is stored on the first floating gate.

14. The voltage reference circuit of claim 12, wherein the programming terminal comprises commonly coupled source/drain regions of floating gate transistors forming a tunneling capacitor.

15. The voltage reference circuit of claim 12, further comprising:

a third NVM transistor coupled in a configuration that shares a source with the first NVM transistor; and

a differential amplifier having inputs coupled to the first and third NVM transistors and an output configured to provide a reference voltage.

16. The voltage reference circuit of claim 15, wherein the first NVM transistor is the same as the second and third NVM transistors.

17. The voltage reference circuit of claim 12, wherein the second NVM transistor comprises:

a drain region, wherein the first switch is coupled between the drain region and the programming terminal;

a control gate coupled to the drain region; and

a second floating gate coupled to the control gate.

18. The voltage reference circuit of claim 17, wherein the second NVM transistor further comprises: a source region commonly coupled to a source region of the first NVM transistor.

19. The voltage reference circuit of claim 12, further comprising: a bias transistor configured to introduce a current through the second NVM transistor that is equal to a current through the first NVM transistor.