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HK125795A - Overvoltage protection circuit for mos components - Google Patents

Overvoltage protection circuit for mos components Download PDF

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Publication number
HK125795A
HK125795A HK125795A HK125795A HK125795A HK 125795 A HK125795 A HK 125795A HK 125795 A HK125795 A HK 125795A HK 125795 A HK125795 A HK 125795A HK 125795 A HK125795 A HK 125795A
Authority
HK
Hong Kong
Prior art keywords
diff
oxide transistor
mos
protection circuit
wann
Prior art date
Application number
HK125795A
Other languages
German (de)
French (fr)
Inventor
Terletzki Hartmud
Lothar Risch Dr
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of HK125795A publication Critical patent/HK125795A/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention relates to an overvoltage protection circuit for MOS components consisting of a resistor (R), a field oxide transistor (FOX) and a thin oxide transistor (DOX). The breakdown of the parasitic dipole transistor inside the field oxide transistor is optimised so that the latter can with certainty leak off all the energy of an overvoltage pulse against the reference potential (VSS?). The measures described reduce the thermal damage known as 'spiking' which can cause the MOS component to break down.

Description

The invention relates to a circuit for protecting against surges for MOS components within the meaning of claim 1.
Today's MOS components have a high failure rate due to electrostatic discharges from man and machine in their manufacture and handling. To reduce the negative effects of these electrostatic discharges, also called ESD (= electrostatic discharge), there are basically two possibilities. One can provide a potential-free environment for the MOS component, for example by transporting it in special foam bodies or one develops a special circuit for the protection of the component, which can also be integrated on the MOS component.
Err1:Expecting ',' delimiter: line 1 column 86 (char 85)Err1:Expecting ',' delimiter: line 1 column 289 (char 288)Err1:Expecting ',' delimiter: line 1 column 229 (char 228)
European registration EP 0 217 525 is known for a protective device which provides surge protection at the output of a circuit to be protected by means of a field-oxide transistor.
The purpose of the invention is to specify an improved circuit for the protection of MOS components against surges, which takes up as little space as possible and safely diverts the surge at the input terminals against a reference potential.
These tasks are solved by the features specified in the identifying part of claim 1.
Err1:Expecting ',' delimiter: line 1 column 362 (char 361)
Patent claims 2 to 7 concern a preferred design of the protective circuit, which is described in more detail there.
Err1:Expecting ',' delimiter: line 1 column 413 (char 412)
The circuit is designed to be connected in such a way that the source connection of the FOX field-oxide transistor, the source connection of the DOX thin-oxide transistor and the gate connection of the DOX thin-oxide transistor are connected to a reference potential. The reference potential in this case is the VSS mass gate. The drain connection and the drainage connection of the FOX field-oxide transistor are connected to a connection to the resistor and to a further connection to the POS A or POS B. The gate connection for the MOS A or MOS A can be connected to a connection to the A or MOS A or to another gate connection.
The resistance R of the RC low pass member serves to limit the current when overvoltages occur, since the DOX transistor cannot dissipate high energies when overvoltage against the reference potential VSS.For this purpose, the FOX field oxide transistor is used, which works as a parasitic bipolar transistor operating in a loop-breaking mode under an ESD load and dissipates the energy of the ESD pulse against the reference potential.
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Err1:Expecting ',' delimiter: line 1 column 77 (char 76)
Err1:Expecting ',' delimiter: line 1 column 234 (char 233)
Figure 4 shows the inventive part of the surge protective circuit, which is constructed in the same way as in Figure 1. It contains a field-oxide transistor, a resistor and a thin oxide transistor. Figure 4 shows the area of the field-oxide transistor which is formed by the insulation layer Loc'', the two n+ diffusion regions n-Diff'', n-Diff'', the oxidation layer Ox'', and the aluminium layers Al'Diff', Al'Iso'. In this case, the n+ diffusion layer n-Diff' is placed above the drainage area, wherein the n+ diffusion region K has contact with the diffusion layer Ox'Diff' diffusion layer, and the n+ diffusion region K has contact with the oxide layer K, and the n+ diffusion region n' is located below the n+ diffusion layer Al'Diff' and the n+ diffusion region K is situated below the Al'Diff' diff' diff'dition layer Al'Iso. The n+ diffusion region is defined as the area wherein the n+ diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff'Diff', and the n'Diff'Diff'Diff'Diff'
The field-oxide transistor of the protective circuit operates at ESD stress as described at the outset as a parasitic npn-bipolar transistor operating in an avalanche break, whereby the collector connection at the n+-doped diffusion region n-diff'', the emitter connection at the n+-doped diffusion region n-diff'' and the base connection within the p-conducting semiconductor substrate p-Sub' can be imagined. The following steps, which are an essential part of the invention, allow the parasitic bipolar transistor to be optimized in its break behaviour so that the protective circuit can connect the overvoltages against the over-spatial transitions in a reference frame.In this case, the mass of the VSS is to be switched. Therefore, the aluminium layer Al' with VSS and the aluminium layer Al' with the connection P of the MOS component must be connected. In order to be able to use the transistor function at all, the two n+-done diffusion regions of the feldspar transistor should have a minimum distance from each other. The minimum distance is determined by the leakage current and the punch-through behavior of the feldspar transistor. The height of the leakage current should not exceed 10 μA. The maximum distance between the two n+ diffusion regions is determined by the start-up time of the parasitic bipolar transistor, so that the base or the cross section of the feldspar transistor should not exceed a length of 1,5 μm.Err1:Expecting ',' delimiter: line 1 column 654 (char 653)Otherwise, the avalanche can only break through at higher voltages.
The n+ diffusion areas n-diff'' and n-diff''' should have a diffusion height greater than 1020 cm−3, while the low-dotted n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Wann n-Ann n-Wann n-Ann-Nann n-Wann n-Nann-Nann-Nann-Nann-Nann n-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-Nann-
The field implant below the Locos stage 'Loc'' which increases the base doping in this region to a doping concentration of 1 x 1017 cm−3 should have a depth of 1.2 μm. The following information can be used to dimension the other components of the protective circuit, such as the resistor R and the thin oxide transistor DOX, which are switched as shown in Figure 1. The diffusion resistor should not exceed 1 kOhm, while the field-controlled diode-switched DOX transistor DOX should have a channel width of 0.2 μm, approximately to select the factor greater than the minimum channel width. For example, a transistor with a diameter of between 60 and 1.2 μm should be selected.
Both field effect transistors of the protective circuit can also be formed as p-channel transistors, merely by switching the p and n regions, leaving the basic circuit intact.
The field-oxide transistor FOX' is shaped and constructed in a convex pattern as described in Figure 4. The channel spacing of the field-oxide transistor should not be less than 200 μm, with the channel itself being formed by two chamber-shaped n+ non-conductive dotation zones. The first n+ dotation zone D1 is connected to the mass Vss input, while the second n+ non-dode zone D2 is connected to an E+ dotation zone P of the MOS-B dotation zone. The last n+ non-dode zone D1+ is located between the n+ non-dode transistor and the second n+ non-dode zone D2+ D2+ dotation zone D. Its construction is significantly smaller than the first one, and the gate is located at the end of the D0+ non-dode zone.

Claims (7)

  1. Overvoltage protection circuit for MOS components which contains an MOS field oxide transistor (FOX) with parasitic bipolar transistor, an MOS thin oxide transistor (DOX) and a resistor (R), in which a first diffusion region (n-Diff''') forms a source region and a second diffusion region (n-Diff'') a drain region and both diffusion regions have a different conducting type from the substrate (p-Sub''), the first diffusion region (n-Diff''') is connected to a first terminal of the MOS field oxide transistor (FOX), the second diffusion region (n-Diff'') to a second terminal of the MOS field oxide transistor (FOX), and in which the first terminal of the MOS field oxide transistor (FOX), and a first terminal and a gate terminal each belonging to the MOS thin oxide transistor (DOX) are connected to a common reference potential, and in which a first terminal of the resistor (R), and the second terminal and a gate terminal each belonging to the MOS field oxide transistor (FOX) are connected to an input terminal (P) of the MOS component, and a second terminal of the resistor (R) is connected to a second terminal of the MOS thin oxide transistor (DOX) and to a terminal point (A) of the protection circuit, characterised in that the spacing between the first and second diffusion region (n-Diff''', n-Diff'') is so chosen that its minimum is determined by a leakage current limit of the MOS field oxide transistor and its maximum by a specified switch-on time of the parasitic bipolar transistor, in that a semiconductor zone (n-W) which is of tub-shaped construction and which is similarly and more lightly doped than the second diffusion region (n-Diff'') is disposed beneath the second diffusion region (n-Diff''), and in that the second diffusion region (n-Diff'') overlaps the semiconductor zone (n-W) of tub-shaped construction.
  2. Overvoltage protection circuit according to Claim 1, characterised in that the MOS thin oxide transistor (DOX) and the MOS field oxide transistor (FOX) are constructed as p-channel transistor.
  3. Overvoltage protection circuit according to Claim 1, characterised in that the MOS thin oxide transistor (DOX) and the MOS field oxide transistor (FOX) are constructed as n-channel transistor.
  4. Overvoltage protection circuit according to any of Claims 1 to 3, characterised in that the resistor (R) is constructed as resistive diffusion track.
  5. Overvoltage protection circuit according to any of Claims 1 to 4, characterised in that the MOS field oxide transistor (FOX) is constructed with an increased base doping in order to suppress a charge movement between the first and second diffusion layer (n-Diff''', n-Diff'') in normal operation.
  6. Overvoltage protection circuit according to any of Claims 1 to 5, characterised in that the MOS field oxide transistor (FOX) of the protection circuit is disposed in a meander fashion on a semiconductor substrate.
  7. Overvoltage protection circuit according to any of Claims 1 to 6, characterised in that the protection circuit is integrated with the MOS component on a semiconductor substrate.
HK125795A 1989-03-08 1995-08-03 Overvoltage protection circuit for mos components HK125795A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE3907523A DE3907523A1 (en) 1989-03-08 1989-03-08 PROTECTIVE CIRCUIT AGAINST OVERVOLTAGE FOR MOS COMPONENTS

Publications (1)

Publication Number Publication Date
HK125795A true HK125795A (en) 1995-08-11

Family

ID=6375854

Family Applications (1)

Application Number Title Priority Date Filing Date
HK125795A HK125795A (en) 1989-03-08 1995-08-03 Overvoltage protection circuit for mos components

Country Status (7)

Country Link
EP (1) EP0462108B1 (en)
JP (1) JP2797259B2 (en)
KR (1) KR0165897B1 (en)
AT (1) ATE103417T1 (en)
DE (2) DE3907523A1 (en)
HK (1) HK125795A (en)
WO (1) WO1990010952A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4118441A1 (en) * 1991-06-05 1992-12-10 Siemens Ag CIRCUIT ARRANGEMENT TO PROTECT AGAINST OVERVOLTAGE ON INPUTS OF INTEGRATED MOS CIRCUITS
DE69231494T2 (en) * 1991-12-27 2001-05-10 Texas Instruments Inc., Dallas ESD protection device
DE59308352D1 (en) * 1993-05-04 1998-05-07 Siemens Ag Integrated semiconductor circuit with a protective agent
GB2336241B (en) * 1998-01-15 2000-06-14 United Microelectronics Corp Substrate-triggering electrostatic dicharge protection circuit for deep-submicron integrated circuits

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5715459A (en) * 1980-07-01 1982-01-26 Fujitsu Ltd Semiconductor integrated circuit
US4734752A (en) * 1985-09-27 1988-03-29 Advanced Micro Devices, Inc. Electrostatic discharge protection device for CMOS integrated circuit outputs

Also Published As

Publication number Publication date
EP0462108A1 (en) 1991-12-27
ATE103417T1 (en) 1994-04-15
EP0462108B1 (en) 1994-03-23
WO1990010952A1 (en) 1990-09-20
KR0165897B1 (en) 1998-12-15
JPH04504030A (en) 1992-07-16
DE59005132D1 (en) 1994-04-28
JP2797259B2 (en) 1998-09-17
DE3907523A1 (en) 1990-09-20
KR920702025A (en) 1992-08-12

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Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20040118

PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)