HK1220306B - Method and system for implementing correlated multi-sampling with improved analog-to-digital converter linearity - Google Patents

Description

Method and system for implementing correlated multi-sampling with improved analog-to-digital converter linearity

Technical Field

Examples of the present invention generally relate to image sensors. More particularly, examples of the present invention relate to methods and systems for reading out image data from image sensor pixel cells, including performing analog-to-digital conversion. Examples of the present invention include methods and systems for implementing correlated multi-sampling with improved analog-to-digital converter linearity.

Background Art

High-speed image sensors are widely used in many applications across a wide range of fields, including automotive, machine vision, and professional video capture. The continued demand from the consumer market for high-speed slow-motion video and standard high-definition (HD) video with reduced rolling shutter effects is further driving the development of high-speed image sensors.

In a conventional complementary metal oxide semiconductor ("CMOS") pixel cell, image charge is transferred from a photosensitive device (e.g., a photodiode) and converted to a voltage signal within the pixel cell on a floating diffusion node. The image charge can be read out of the pixel cell into a readout circuit and then processed. In conventional CMOS image sensors, the readout circuit includes an analog-to-digital converter (ADC). ADCs are inherently subject to nonlinear errors due to the specific architecture of each ADC. Nonlinear errors, including integral nonlinearity (INL) and differential nonlinearity (DNL), cause the output of the ADC to deviate from an ideal output. For example, the ideal output may be a linear function of the input.

Because these nonlinear errors are inherent to the ADC, it is impossible to remove the effects of these errors through calibration. The negative effects of nonlinear errors on image sensors include reducing the dynamic range of the image charge (e.g., input signal) that can be processed by the ADC of the readout circuit and reducing the effective resolution of the ADC.

Summary of the Invention

In one aspect, the present invention provides a method for implementing correlated multi-sampling (CMS) with improved analog-to-digital converter (ADC) linearity in an image sensor. The method includes: acquiring, by a readout circuit, image data from a first row of a color pixel array; generating, by an ADC circuit included in the readout circuit, a plurality of uncorrelated random numbers for a plurality of ADC pedestals for the first row, the ADC pedestals including a first ADC pedestal and a second ADC pedestal; storing, by a successive approximation register (SAR) included in the ADC circuit, the first ADC pedestal; sampling, by the ADC circuit, the image data from the first row relative to the first ADC pedestal stored in the SAR to obtain first sampled input data; and converting, by the ADC circuit, the first sampled input data from analog to digital to obtain a first ADC output value; upon obtaining the first ADC output value, storing, by the SAR, the second ADC pedestal; sampling, by the ADC circuit, the image data from the first row relative to the second ADC pedestal stored in the SAR to obtain second sampled input data; and converting, by the ADC circuit, the second sampled input data from analog to digital to obtain a second ADC output value.

In another aspect, the present invention provides a method for implementing correlated multi-sampling (CMS) with improved analog-to-digital converter (ADC) linearity in an image sensor. The method includes: generating, by an ADC circuit, a plurality of uncorrelated random numbers used as a plurality of ADC pedestals for sampling from a first row; storing, by a successive approximation register (SAR) included in the ADC circuit, a different one of the ADC pedestals before each sampling of image data; sampling, by an ADC circuit included in a readout circuit, the image data from the first row a plurality of times relative to the plurality of ADC pedestals stored in the SAR to obtain a plurality of sampled input data; and converting, by the ADC circuit, each of the plurality of sampled input data from analog to digital, wherein the conversion by the ADC circuit includes performing a binary search using the SAR.

In yet another aspect, the present invention provides an imaging system comprising a color pixel array for acquiring image data, the pixel array comprising a plurality of rows and columns; a readout circuit coupled to the color pixel array to acquire image data from a first row in the color pixel array, wherein the readout circuit comprises an analog-to-digital conversion (ADC) circuit to: generate a plurality of uncorrelated random numbers for use as a plurality of ADC pedestals for sampling from the first row; store a different one of the ADC pedestals in a successive approximation register (SAR) included in the ADC circuit before each sampling of the image data; sample the image data from the first row a plurality of times relative to the plurality of ADC pedestals stored in the SAR to obtain a plurality of sampled input data, wherein the image data is sampled on a digital-to-analog (DAC) circuit included in the ADC circuit; and convert each of the plurality of sampled input data from analog to digital, wherein conversion by the ADC circuit comprises performing a binary search using the SAR and the DAC circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements throughout the figures unless otherwise specified. It should be noted that references to "an" or "one" embodiment of the invention are not necessarily to the same embodiment, and are intended to mean at least one. In the drawings:

1 is a block diagram illustrating an example imaging system including readout circuitry implementing correlated multi-sampling with improved ADC linearity, according to one embodiment of the present invention.

2 is a block diagram illustrating details of the readout circuitry of FIG. 1 according to one embodiment of the present invention.

3 is a block diagram illustrating details of the ADC circuit in FIG. 2 according to one embodiment of the present invention.

4 illustrates a timing diagram of input and output signals in the ADC circuits of FIGS. 2 and 3 , according to one embodiment of the present invention.

5 is a flow chart illustrating a method for implementing correlated multi-sampling with improved analog-to-digital converter linearity according to one embodiment of the present invention.

Corresponding reference symbols indicate corresponding components throughout the several views of the drawings. Those skilled in the art will appreciate that the elements in the drawings are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be exaggerated relative to other elements to help improve understanding of the various embodiments of the present invention. Furthermore, to facilitate a less obstructed understanding of these various embodiments of the present invention, common but well-understood elements that are useful or necessary in commercially viable embodiments are generally not depicted.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, embodiments of the present invention may be practiced without using these specific details. In other cases, well-known circuits, structures, or technologies are not shown to avoid obscuring the understanding of this description.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearance of the phrases "in one embodiment" or "in an embodiment" in multiple places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. The particular features, structures, or characteristics may be included in an integrated circuit, an electronic circuit, a combinational logic circuit, or other suitable components that provide the described functionality.

An example according to the present invention describes an image sensor readout circuit that implements correlated multi-sampling (CMS) while reducing nonlinear errors in ADC circuitry included in the readout circuitry. In one example, the nonlinear errors in the ADC circuitry are reduced by oversampling (CMS) within the row time in addition to randomizing the ADC pedestal. According to the present invention, the image sensor readout circuitry can calculate and utilize an average of the errors of multiple samples to reduce the nonlinear errors in the ADC circuitry.

FIG1 is a block diagram illustrating an example imaging system 100 including a readout circuit 110 implementing correlated multi-sampling with improved ADC linearity, according to one embodiment of the present invention. Imaging system 100 may be a complementary metal oxide semiconductor (“CMOS”) image sensor. As shown in the depicted example, imaging system 100 includes a pixel array 105 coupled to control circuitry 120 and readout circuitry 110, which is coupled to function logic 115 and logic control 108.

The illustrated embodiment of pixel array 105 is a two-dimensional ("2D") array of imaging sensors or pixel cells (e.g., pixel cells P1, P2, ... Pn). In one example, each pixel cell is a CMOS imaging pixel. As illustrated, each pixel cell is arranged into rows (e.g., rows R1 through Ry) and columns (e.g., columns C1 through Cx) to acquire image data of a person, location, object, etc., which can then be used to render an image of the person, location, object, etc.

In one example, after each pixel cell has acquired its image data or image charge, the image data is read out by readout circuitry 110 via column bit lines 109 and then passed to function logic 115. In one embodiment, logic circuitry 108 can control readout circuitry 110 and output the image data to function logic 115. In various examples, readout circuitry 110 can include amplification circuitry (not illustrated), analog-to-digital conversion (ADC) circuitry 220, or other. Function logic 115 can simply store the image data or even manipulate it by applying post-image effects (e.g., cropping, rotation, red-eye removal, brightness adjustment, contrast adjustment, or other). In one example, readout circuitry 110 can read out image data one row at a time along a readout column line (illustrated), or can use a variety of other techniques (not illustrated), such as serial readout or simultaneous full parallel readout of all pixels.

In one example, control circuitry 120 is coupled to pixel array 105 to control operational characteristics of pixel array 105. For example, control circuitry 120 may generate a shutter signal for controlling image acquisition. In one example, the shutter signal is a global shutter signal that simultaneously enables all pixels within pixel array 105 to simultaneously capture their corresponding image data during a single acquisition window. In another example, the shutter signal is a rolling shutter signal that sequentially enables each row, column, or group of pixels during successive acquisition windows.

FIG2 is a block diagram illustrating details of readout circuitry 110 of imaging system 100 of FIG1 implementing correlated multi-sampling with improved ADC linearity, according to one embodiment of the present invention. As shown in FIG2 , readout circuitry 110 may include scanning circuitry 210, ADC circuitry 220, and a random number generator (RNG) 230. Scanning circuitry 210 may include amplification circuitry, selection circuitry (e.g., a multiplexer), and the like to read out image data one row at a time along readout column bit lines 109, or may read out the image data using a variety of other techniques, such as serial readout or simultaneous, fully parallel readout of all pixels. Random number generator (RNG) 230 may be coupled to ADC circuitry 220 to generate a random value used as an ADC pedestal (Nx). Using this random value, ADC circuitry 220 may sample image data from a row of pixel array 105 relative to the random value used as the ADC pedestal.

FIG3 is a block diagram illustrating details of ADC circuit 220 in FIG2 according to one embodiment of the present invention. Although not illustrated in some embodiments, multiple ADC circuits 220 may be included in readout circuit 110. As shown in FIG3, ADC circuit 220 includes a comparator 304 (e.g., a fully differential operational amplifier), a latch 305, a selector circuit 306 (e.g., a multiplexer), a digital-to-analog converter (DAC) circuit 310, and a successive approximation register (SAR) 307. ADC circuit 220 also includes multiple switches, including an input switch "SHX" 301, a pair of comparator reset switches "CMP_RST" ₃₀₃₁ , ₃₀₃₂ , and a pair of digital-to-analog converter (DAC) reset switches "DAC_RST" ₃₀₉₁ , ₃₀₉₂ . The ADC circuit 220 also includes a plurality of DAC capacitors 308 ₁ through 308 _p (p>1) included in a DAC circuit 310 and a pair of comparator capacitors 302 ₁ , 302 ₂ coupled to the inputs of the comparator 304 .

In one embodiment, as shown in FIG3 , DAC circuit 310 includes a plurality of DAC capacitors 308 _{1-308 p} in parallel and one capacitor 312 located between the front plates of two parallel capacitors 308 ₄ and 308 _5. The back plates of capacitors ₃₀₈ 1-308 _p are coupled to data output lines 311 _{1-311 w} (w>1), respectively, of SAR 307. In some embodiments, SAR 307 includes twelve data output lines (e.g., w=12) coupled to twelve parallel capacitors ₃₀₈ 1-308 _p (e.g., p=12). DAC circuit 310 is coupled to DAC reset switches "DAC_RST" 309 ₁ and 309 _2. After closing DAC reset switches "DAC_RST" 309 ₁ and 309 ₂ , the front plates of DAC capacitors 308 _{1-308 p} and both plates of DAC capacitor 312 are coupled to ground, and thus DAC circuit 310 is reset. 3 , input voltage V _IN is received from scan circuit 210 and corresponds to image data or image charge from pixels in pixel array 105. After closing input switch “SHX,” input voltage V _IN is measured at node _{V DAC} such that it is received and acquired by capacitors ₃₀₈ 1-308 _p in DAC circuit 310.

In one embodiment, the inputs of comparator 304 are coupled to comparator capacitors 302 ₁ and 302 ₂ and comparator reset switches 303 ₁ and 303 ₂ , respectively. After closing comparator reset switches 303 ₁ and 303 ₂ , the inputs of comparator 304 and comparator capacitors 302 ₁ and 302 ₂ are coupled to a predetermined voltage, V _CM . As shown in FIG3 , comparator capacitor 302 ₁ is coupled to ground, while comparator capacitor 302 ₂ is coupled to node V _DAC . In one embodiment, the comparator is reset during SHR1 in FIG4 (for example, when V _IN equals the pixel reset value) and the input signal V _IN is sampled on DAC circuit 310. In other words, after each conversion of the voltage output V _IN (for example, when all samples in a row have been converted), the comparator 304 is reset by closing the comparator reset switches “CMP_RST” 303 ₁ , 303 ₂ such that the inverting input of the comparator 304 coupled to the comparator reset switch “CMP_RST” 303 ₂ is set to the predetermined comparator voltage V _CM .

The output of comparator 304 is coupled to latch 305, which receives and stores the data being output from comparator 304. The output of latch 305 is coupled to selector circuit 306, and the output of selector circuit 306 is coupled to SAR 307. In one embodiment, one of the outputs of latch 305 is inverted. Thus, SAR 307 can receive a SAR input, which is the result (or output) of comparator 304, via latch 305 and selector circuit 306.

SAR 307 is coupled to a voltage reference _VREF (e.g., 10V) and to ground, and controls the DAC circuit 310 by driving the backplates of DAC capacitors ₃₀₈₁ to _308p via data output lines ₃₁₁₁ to _311w. For example, if the first data output line ₃₁₁₁ (e.g., b0) is 0, the backplate of the DAC capacitor ₃₀₈₁ coupled thereto is connected to ground, and if the first data output line 3111 is ₁ , the backplate of the DAC capacitor ₃₀₈₁ coupled thereto is connected to the voltage reference _VREF . SAR 307 is reset before each conversion of the sampled input data (e.g., _VSHR1 , _VSHR2 , _VSHR3 , _VSHR4 , _VSHS1 , _VSHS2 , _VSHS3 , _VSHS4 ). The sampled input data is obtained by the ADC circuit sampling the image data from a given row being processed. SAR 307, in conjunction with DAC circuit 310, performs a binary search and sequentially sets each bit in data output lines 311 ₁ through 311 _w from the most significant bit (MSB) to the least significant bit (LSB). In this embodiment, comparator 304 determines whether the bit in data output lines 311 ₁ through 311 _w should remain set or reset. At the end of the conversion, SAR 307 holds the ADC conversion value (e.g., ADC output) of the sampled input data.

1 and 3 , each of the elements of the ADC circuit 220 can be controlled by the logic circuit 108. In one example, the logic circuit 108 can transmit signals to control the timing of opening and closing switches “SHX” 301, “CMP_RST” 303 ₁ , 303 ₂ , and “DAC_RST” 309 ₁ , 309 _2, respectively, as well as transmit signals to control the latch 305 and the selector circuit 306. In one example, the logic circuit 108 generates and transmits signals to control the switches (as shown in the timing diagram of FIG. 4 ).

As an example, if node V _DAC has a value of V1 and SAR 307 includes 12-bit storage and is storing a value equal to 0 (e.g., output lines 311 _{1-311 w} = B<11:0> = 0x000), node V _DAC will increase linearly from V1 to approximately V ₁ + V _REF because DAC capacitors ₃₀₈ 1-308 _p are binary coded by SAR 307 sweeping through all possible codes (from 0 to 4095).

However, sampling the input voltage (signal) V _IN on DAC circuit 310 using SAR 307 set to 0 (e.g., B<11:0>=0x000) will be negatively impacted by any noise, comparator 304 offset, or charge injection from switches 303, 303 ₁ , 303 ₂ , causing the input voltage signal V _IN to be clipped during ADC conversion. This is because the lowest output voltage of DAC circuit 310 is achieved when the input of SAR 307 is set to 0. In one embodiment, to avoid this negative effect, sampling of the input voltage signal V _IN is performed relative to a SAR 307 value above 0 (e.g., the ADC pedestal). As shown in FIG. 3 , in one embodiment, SAR 307 may also be coupled to random number generator (RNG) 230 to receive a random value used as the ADC pedestal (Nx). In some embodiments, random number generator 230 generates uncorrelated random numbers that may be uniformly distributed between 64 and 79 and transmits them to SAR 307.

In some embodiments, output _{lines 3111-311w} of SAR 307 are coupled to a multiplexer (not shown) controlled by logic circuit 108 to set the pedestal value. In this embodiment, the contents of SAR 307 (e.g., _VSHR1 ) can be transferred to a readout memory (not shown) included in readout circuit 110 during sampling of the next value (e.g., _VSHR2 , _VSHR3 , _VSHR4 , _VSHS1 , _VSHS2 , _VSHS3 , _VSHS4 ).

In this embodiment, because comparator 304 is reset during SHR1 in FIG4 (for example, when _VIN is equal to the pixel reset value) and the voltage input signal _VIN is sampled on DAC circuit 310, conversions of the V _SHR sampled input value will result in a value close to the value of the ADC pedestal. In this embodiment, the inverting input of comparator 304 is set to a predetermined voltage, _VCM , after each conversion. In one embodiment, 8-bit conversions are used for the V _SHR sampled input value, while 12-bit conversions are used for the V _SHS sampled input value.

In one embodiment, to reduce the nonlinear errors inherent in ADC circuit 220, ADC circuit 220 uses correlated multi-sampling (CMS) and uses ADC pedestals randomized within a row time. In other embodiments, the ADC pedestals can also be randomized row by row of the pixel array.

FIG4 illustrates a timing diagram of input and output signals in the ADC circuit 220 of FIG2 and 3, according to one embodiment of the present invention. As discussed above, the logic circuit 108 can transmit control signals to elements in the ADC circuit 220 (e.g., switch "SHX" 301, "CMP_RST" 303 ₁ , 303 ₂ , and "DAC_RST" 309 ₁ , 309 ₂ ) to correspond to the signals illustrated in the timing diagram of FIG4. The logic circuit 108 can also transmit control signals to the latch 305 and the selector circuit 306. In one embodiment, the correlated multi-sampling (CMS) voltage V _CMS can be calculated according to the following:

In FIG4 , the left portion of the timing diagram illustrates ADC conversion of the V _SHR value, and the right portion of the timing diagram illustrates ADC conversion of the V _SHS value. In the example of FIG4 , the DAC circuit 310 is reset (e.g., DAC_RST=1) before the next conversion (e.g., SHX=1), and the comparator 304 is reset (e.g., CMP_RST=1) during SHR1 (e.g., SHX=1). In the example of FIG4 , there are four CMS samples (i.e., M=4; 4×CMS), so four values of the ADC pedestal are used ( _N1 to _N4 ). The ADC pedestal values of _N1 to _N4 are uncorrelated random numbers. In one embodiment, the values of _N1 to _N4 may be uniformly distributed between 64 and 79. As shown in FIG4 , sampling within a row (e.g., V _SHR1 , V _SHR2 , V _SHR3 , V _SHR4 and V _SHS1 , V _SHS2 , V _SHS3 , V _SHS4 ) is performed relative to SAR 307, where ADC pedestal values are N ₁ through N ₄ . By randomizing the ADC pedestal values N ₁ through N ₄ and performing multiple sampling (e.g., 4x CMS as in FIG4 ), ADC circuit 220 can average the linearity error from each sampling, resulting in improved ADC DNL and INL. Furthermore, by improving the ADC linearity of ADC circuit 220 , ADC-induced structured noise is reduced. In some embodiments, the ADC pedestal values (e.g., N ₁ through N ₄ ) are further randomized row by row across pixel array 105 to reduce vertical fixed pattern noise (VFPN).

Furthermore, the following embodiments of the present invention may be described as a process, which is often depicted as a flowchart, flow diagram, structure diagram, or block diagram. Although a flowchart may describe operations as a sequential process, many operations may be performed in parallel or simultaneously. In addition, the order of the operations may be rearranged. A process terminates when its operations are completed. A process may correspond to a method, procedure, or the like.

FIG5 is a flow chart illustrating a method 500 for implementing correlated multi-sampling with improved analog-to-digital converter linearity according to one embodiment of the present invention. The method or process 500 begins with a readout circuit acquiring image data from a given row n in a color pixel array (block 501), where n ≥ 1. In one embodiment, the readout circuit includes a scanning circuit that selects and amplifies the image data from the given row n. The scanning circuit may include at least one multiplexer for selecting an image and at least one amplifier for amplifying the image data. The scanning circuit may also transmit the selected and amplified image data to the ADC circuit for further processing.

At block 502, an ADC circuit included in the readout circuit generates multiple uncorrelated random numbers that serve as ADC pedestals for a given row n. Thus, the values used as ADC pedestals are randomized for the same row, rather than having a single number repeatedly used as the ADC pedestal for the same row. In some embodiments, the uncorrelated random numbers are uniformly distributed between 64 and 79. At block 503, a SAR included in the ADC circuit stores one of the uncorrelated random numbers as the ADC pedestal, and in block 504, the ADC circuit samples image data from row n to obtain sampled input data. In this embodiment, the ADC circuit samples relative to the value stored in the SAR (for example, a random number greater than 0x000). Referring back to FIG. 4 , the uncorrelated random numbers used as ADC pedestals are: _N1 , _N2 , _N3 , and _N4 . In the example in FIG. 4 , _N1 is 0x41 (or 65) and _N2 is 0x45 (or 69). In this example, the readout circuitry implements CMS using four samples (M=4).In one embodiment, the ADC circuit samples the image data from the given row on a digital-to-analog (DAC) circuit included in the ADC circuitry to obtain the sampled input data.

At block 505 in FIG. 5 , the ADC circuit converts the sampled input data from analog to digital to obtain an ADC output value. Thus, the ADC output value is a digitized value corresponding to the sampled input data. In some embodiments, converting the sampled input data from analog to digital includes performing a binary search using a DAC circuit and a SAR, both included in the ADC circuit. The ADC circuit may also include a comparator. In this embodiment, to perform the analog-to-digital conversion of the sampled input data, the comparator determines whether multiple bits stored in the SAR are continuously set or reset from the MSB to the LSB, and the SAR sets or resets each of the multiple bits stored therein based on the determination made by the comparator. Once the LSB stored in the SAR is set or reset by the SAR, the value stored in the SAR becomes the ADC output value, which is the digitally converted value of the sampled input data. The ADC output value may then be output to functional logic or stored in a memory included in the readout circuit. In one embodiment, the analog-to-digital conversion of the sampled input data by the ADC circuit further includes resetting the inverting input of the comparator to a predetermined value (e.g., V _CM ) on the DAC circuit during sampling of the image data to obtain the sampled input data. In this embodiment, the ADC circuit further includes a latch coupled to the output of the comparator and a selector circuit (e.g., a multiplexer) coupled to the output of the latch. The latch receives and stores the comparator output value, and the selector circuit selects the value output from the latch to be transmitted to the SAR.

At block 506, the ADC circuit determines whether additional input data samples are pending for a given row n. For example, in the example of FIG. 4 , the pairs of samples to be processed include: _VSHR1 , _VSHR2 , _VSHR3 , _{VSHR4, VSHS1 , VSHS2} , _VSHS3 , and _VSHS4 . In FIG. 4 , once sample _VSHR1 is converted from analog to digital to obtain an ADC output value and the SAR contains the ADC output value, the ADC circuit can determine that additional samples (e.g., _VSHR2 , _VSHR3 , _VSHR4 , _VSHS1 , _VSHS2 , _VSHS3 , and _VSHS4 ) are pending for processing for row n. At block 506, if the ADC circuit determines that the current sample being converted is not the last sample in row n, process 500 returns to block 503, where the SAR updates its contents and stores a different one of the uncorrelated random numbers as the ADC pedestal, and at block 504, the ADC circuit samples image data from row n relative to the updated value stored in the SAR. For example, in FIG4 , the SAR stores _N2 instead of _N1 . Process 500 then continues to block 505, where the sampled input data is converted from analog to digital to produce another ADC output.

At block 506, if the ADC circuit determines that no further input data samples are to be processed for a given row n, process 500 continues to block 507 where the ACD circuit calculates the nonlinearity error and outputs the final ADC output for row n. In some embodiments, the ADC circuit stores the ADC output values in a memory (not shown) included in the readout circuit. To calculate the nonlinearity error, the ACD circuit may determine the INL and DNL for each of the ACD outputs (e.g., for each digitized converted sampled input data for a given row n) and calculate the average of the INL and DNL errors for row n. To output the final ADC output for row n, the ADC circuit may calculate the CMS voltage V _CMS using the following equation:

In other embodiments, the ADC circuit outputs the ADC output value to function logic to perform row n calculations for nonlinear errors and final ADC outputs. By randomizing the ADC pedestal within the row time and implementing CMS, ADC nonlinearities, including INL and DNL, are reduced because nonlinear errors are averaged. Process 500 can be repeated for each row in the color pixel array.

The processes explained above are described in terms of computer software and hardware. The techniques described may constitute machine-executable instructions embodied in a machine (e.g., a computer) readable storage medium that, when executed by a machine, causes the machine to perform the described operations. Alternatively, the processes may be embodied in hardware, such as an application-specific integrated circuit ("ASIC") or the like.

The above description of the illustrated embodiments of the present invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Although specific embodiments and examples of the invention are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the invention.

These modifications may be made to examples of the present invention in light of the above detailed description. The terms used in the appended claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and claims. Rather, the scope is to be determined entirely by the appended claims, which are to be construed in accordance with established principles of claim interpretation. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive.

Claims (22)

1. A method for implementing correlated multi-sampling (CMS) with improved analog-to-digital converter (ADC) linearity in an image sensor, comprising: The readout circuit acquires image data from a first row in the color pixel array; generating, by an ADC circuit included in the readout circuit, a plurality of uncorrelated random numbers for a plurality of ADC pedestals used as the first row, the ADC pedestals including a first ADC pedestal and a second ADC pedestal; The first ADC pedestal is stored by a successive approximation register SAR included in the ADC circuit; sampling, by the ADC circuit, the image data from the first row relative to the first ADC pedestal stored in the SAR to obtain first sampled input data; and converting, by the ADC circuit, the first sampled input data from analog to digital to obtain a first ADC output value; Once the first ADC output value is obtained, storing the second ADC base by the SAR, sampling, by the ADC circuit, the image data from the first row relative to the second ADC pedestal stored in the SAR to obtain second sampled input data, and The second sampled input data is converted from analog to digital by the ADC circuit to obtain a second ADC output value. 2. The method of claim 1, wherein the uncorrelated random numbers are uniformly distributed between 64 and 79. 3. The method of claim 1 , wherein acquiring, by the readout circuitry, the image data from the first row further comprises: selecting and amplifying the image data from the first row by a scanning circuit included in the readout circuit; and The image data is transmitted from the first row to the ADC circuit. 4. The method of claim 1 , wherein sampling, by the ADC circuit, the image data from the first row to obtain the first and second sampled input data further comprises: The image data is sampled on a digital-to-analog DAC circuit included in the ADC circuit to obtain the first and the second sampled input data, respectively. 5. The method of claim 4, wherein converting, by the ADC circuit, the first and second sampled input data from analog to digital to obtain the first and second ADC output values, respectively, further comprises: A binary search is performed using the DAC circuit and the SAR. 6. The method of claim 5 , wherein converting, by the ADC circuit, the first and second sampled input data from analog to digital to obtain the first and second ADC output values, respectively, further comprises: The plurality of bits stored in the SAR are successively set or reset from the most significant bit (MSB) to the least significant bit (LSB) as determined by a comparator included in the ADC circuit, Based on the determination of the comparator, setting or resetting, by the SAR, each of the plurality of bits stored in the SAR to obtain the first and second ADC output values, respectively, and The first and second ADC output values are output from the SAR to function logic, respectively. 7. The method of claim 6 , wherein converting, by the ADC circuit, the first and second sampled input data from analog to digital to obtain the first and second ADC output values, respectively, further comprises: The inverting input of the comparator is reset to a predetermined value on the DAC circuit during the sampling of the image data to obtain the first and the second sampled input data, respectively. 8. The method of claim 7 , wherein converting, by the ADC circuit, the first and second sampled input data from analog to digital to obtain the first and second ADC output values, respectively, further comprises: The comparator output value is received and stored by the latch, and The value output from the latch to be transmitted to the SAR is selected by a selector circuit. 9. The method according to claim 8, further comprising: A control signal is received by the readout circuit from a logic circuit, wherein the control signal controls at least one of: the latch, the selector circuit, a switch for receiving the image data, a switch for resetting the comparator, and a switch for resetting the DAC circuit. 10. The method according to claim 9, further comprising: generating, by the readout circuit, a nonlinear error for each of the ADC output values corresponding to the first and the second sampled input data, respectively, and generating an average value of the nonlinear errors; and A final ADC output is generated by the readout circuit based on the first ADC output value and the second ADC output value. 11. A method for implementing correlated multi-sampling (CMS) with improved analog-to-digital converter (ADC) linearity in an image sensor, the method comprising: generating, by the ADC circuit, a plurality of uncorrelated random numbers serving as a plurality of ADC pedestals for sampling from the first row; storing a different ADC pedestal among the plurality of ADC pedestals by a successive approximation register SAR included in the ADC circuit before each sampling of the image data; sampling, by an ADC circuit included in a readout circuit, image data from a first row a plurality of times with respect to the plurality of ADC pedestals stored in the SAR to obtain a plurality of sampled input data; and Each of the plurality of sampled input data is converted from analog to digital by the ADC circuit, wherein converting by the ADC circuit includes performing a binary search using the SAR. 12. The method of claim 11, wherein the uncorrelated random numbers are uniformly distributed between 64 and 79. 13. The method of claim 11 , wherein sampling by the ADC circuit further comprises: The image data is sampled on a digital-to-analog DAC circuit included in the ADC circuit to obtain the plurality of sampled input data. 14. The method of claim 13, wherein converting by the ADC circuit comprises: The binary search is performed using the DAC circuit. 15. The method of claim 14, wherein converting by the ADC circuit comprises: The plurality of bits stored in the SAR are successively set or reset from the most significant bit (MSB) to the least significant bit (LSB) as determined by a comparator included in the ADC circuit, Based on the determination of the comparator, each of the plurality of bits stored in the SAR is set or reset by the SAR to obtain an ADC output value, and The ADC output value is output from the SAR to function logic. 16. The method of claim 15, wherein converting by the ADC circuit comprises: An inverting input of the comparator is reset to a predetermined value on the DAC circuit during the sampling of the image data to obtain the plurality of sampled input data. 17. The method according to claim 16, further comprising: A non-linear error is determined by the readout circuit for each of the ADC output values and an average of the non-linear errors is generated. 18. An imaging system comprising: A color pixel array for acquiring image data, wherein the pixel array comprises a plurality of rows and columns; a readout circuit coupled to the color pixel array to acquire image data from a first row in the color pixel array, wherein the readout circuit includes an analog-to-digital conversion (ADC) circuit to: generating a plurality of uncorrelated random numbers that serve as a basis for a plurality of ADCs for sampling from the first row; storing a different one of the plurality of ADC pedestals in a successive approximation register SAR included in the ADC circuit before each sampling of the image data; sampling the image data from the first row multiple times relative to the multiple ADC pedestals stored in the SAR to obtain a plurality of sampled input data, wherein the image data is sampled on a digital-to-analog DAC circuit included in the ADC circuit, and Each of the plurality of sampled input data is converted from analog to digital, wherein converting by the ADC circuit includes performing a binary search using the SAR and the DAC circuit. 19. The imaging system of claim 18, wherein the uncorrelated random numbers are uniformly distributed between 64 and 79. 20. The imaging system of claim 18, wherein the ADC circuit further comprises: A comparator is used to determine whether to successively set or reset a plurality of bits stored in the SAR from a most significant bit (MSB) to a least significant bit (LSB), wherein the SAR sets or resets each of the plurality of bits stored in the SAR based on the determination of the comparator to obtain an ADC output value. 21. The imaging system of claim 20, wherein converting by the ADC circuit comprises: An inverting input of the comparator is reset to a predetermined value on the DAC circuit during the sampling of the image data to obtain the plurality of sampled input data. 22. The imaging system of claim 21, wherein the readout circuitry further determines a nonlinear error for each of the ADC output values and generates an average of the nonlinear errors.