HK40062797A - Chip system - Google Patents

Description

Chip system

Technical Field

The present disclosure relates to the field of chip technology, and more particularly, to a chip system.

Background

In a chip system, the design structure of a clock and reset is related to the stability of the initial state of the system, the starting efficiency, and the performance of time sequence and energy consumption. In a System on Chip (SoC), different IP (Intellectual Property) checks are applied to different clock signals and reset signals. The working state of the corresponding IP core is controlled by controlling the clock signal and/or the reset signal of each IP core. In a conventional method, a clock signal and a reset signal are generally controlled by a Central Processing Unit (CPU), and it takes a lot of time to send a control instruction, which is inefficient.

Disclosure of Invention

The present disclosure provides a chip system.

According to a first aspect of embodiments of the present disclosure, there is provided a chip system, the chip system comprising: the device comprises a plurality of IP cores and a control unit, wherein the control unit is used for controlling a target signal of at least one IP core in the plurality of IP cores through a control circuit, and the target signal comprises a clock signal or a reset signal.

In some embodiments, the control unit is configured to concurrently control turning on and/or turning off of target signals of at least two IP cores of the plurality of IP cores based on the read first configuration information, where the first configuration information is used to indicate the at least two IP cores.

In some embodiments, the first configuration information occupies at least one specific storage bit of the register, and the control unit is configured to determine the at least two IP cores based on a mapping relationship between a plurality of preset control modes and preset coding information and current coding information of the at least one specific storage bit, where the plurality of preset control modes correspond to different IP core combinations.

In some embodiments, the control unit is further configured to: and on and/or off of target signals of the at least two IP cores are controlled concurrently based on the configured sequence and/or interval of the read second configuration information.

In some embodiments, where the target signal comprises a clock signal, the first configuration information and the second configuration information are stored in the same register; and/or the first configuration information and the second configuration information are stored in different registers in case the target signal comprises a reset signal.

In some embodiments, the chip system further comprises a central processing unit for: writing the first configuration information and the second configuration information into a register in one instruction cycle; and/or writing the first configuration information into a first register in a first instruction cycle, and writing the second configuration information into a second register in a second instruction cycle.

In some embodiments, the control circuit comprises: the enabling end of each switch unit in the switch units is respectively and electrically connected with the control unit and one IP core in the IP cores; the control unit is used for: and controlling the switching state of at least one switching unit in the plurality of switching units so as to control the on and/or off of the clock signal of the corresponding IP core.

In some embodiments, the control unit is coupled to at least one of the plurality of IP cores and configured to transmit a reset signal to the at least one IP core; and/or the control unit is electrically connected with the clock switch unit of at least one of the plurality of IP cores and is used for sending a clock enabling signal to the clock switch unit of the at least one IP core so as to control the conduction of the transmission circuit of the clock signal of the at least one IP core.

In some embodiments, the control unit is to: and taking the state control signal of the first IP core in the plurality of IP cores as a clock enabling signal of the first IP core.

In some embodiments, the control unit is to: controlling a clock signal of a third IP core based on a clock state of a second IP core of the plurality of IP cores, wherein the second IP core and the third IP core have a master-slave relationship therebetween.

In some embodiments, the control unit is to: and controlling a clock signal of a fifth IP core based on voting information of each of at least two fourth IP cores in the plurality of IP cores, wherein the at least two fourth IP cores are users of the fifth IP core, and the voting information is used for indicating the clock signal of the fifth IP core to be turned on or off.

In some embodiments, the control unit is to: turning off a clock signal of a fifth IP core in the case that the clock signal of each of a plurality of fourth IP cores which are clock users of the fifth IP core is turned off; and/or in the case that the clock signal of any one of the plurality of fourth IP cores is turned on, causing the clock signal of the fifth IP core to be in an on state.

Compared with the traditional software control mode, the control unit controls the clock signal or the reset signal through hardware, and the control efficiency of the clock signal or the reset signal is improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure.

Fig. 1 is a schematic diagram of a control clock signal in the related art.

Fig. 2 and 3 are schematic diagrams of a chip system according to an embodiment of the disclosure.

Fig. 4A is a schematic diagram of a conventional clock signal control method.

Fig. 4B is a schematic diagram of a clock signal control manner according to an embodiment of the disclosure.

Fig. 4C is a schematic diagram of a reset signal control manner according to an embodiment of the disclosure.

Fig. 5 is a schematic diagram of a master-slave design mechanism of an embodiment of the disclosure.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used in this disclosure and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality.

It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present disclosure. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.

In order to make the technical solutions in the embodiments of the present disclosure better understood and make the above objects, features and advantages of the embodiments of the present disclosure more comprehensible, the technical solutions in the embodiments of the present disclosure are described in further detail below with reference to the accompanying drawings.

The control manner of the clock signal (clock) and the reset signal (reset) in the related art is implemented based on the manner of the instruction. The following describes a command control method by taking control of a clock signal as an example. In a multi-core CPU, there is a competing relationship between instructions of different CPU cores. As shown in fig. 1, a case including two CPU cores is shown. Assume that the clock signal of one IP core currently needs to be controlled by the first CPU core 101. The instructions sent by the first CPU core 101 and the second CPU core 102 are first transmitted to an arbitration unit 103, the arbitration unit 103 determines the sending priority of the instructions of the two CPU cores, and then the corresponding instructions are sequentially output to the bus 104. After the instructions of the first CPU core 101 are output to the bus, since the priorities of different instructions on the bus 104 are also different, the bus 104 needs to sequentially send each instruction according to the priority of the instruction of the first CPU core 101 and the priorities of other instructions. In the above process, because there is contention between instructions, a control instruction sent by the CPU may take a long time to be written into the register 105 for controlling one clock signal, resulting in low control efficiency.

Based on this, the present disclosure provides a chip system, as shown in fig. 2 and fig. 3, the chip system may include a plurality of IP cores 201, and a control unit 202 for controlling a target signal of at least one IP core of the plurality of IP cores 201 through a control circuit 203, where the target signal includes a clock signal or a reset signal.

The control unit 202 controls the target signal through the control circuit 203, instead of controlling the target signal through a software manner, the control circuit 203 may directly read the control information generated by the control unit 202 through a wire connected with the control unit 202, and after the control circuit 203 reads the control information, the control circuit 203 may directly change its own circuit state (for example, on state or off state) in response to the control information, thereby controlling the target signal. The process has no competition among instructions, and the time delay can be ignored when information is read through the conducting wire, so that the control time of the target signal is effectively saved, and the control efficiency of the target signal is improved.

The IP core in the embodiments of the present disclosure may be any hardware Unit in the Chip system, for example, a watchdog Timer (WDT), a Power Management Unit (PMU), a NOC (Network On Chip) bus, a Direct Memory Access (DMA) controller, a Double Data Synchronous Dynamic Random Access Memory (DDR SDRAM), a security control Unit (security control), a debug Unit (debug), and the like.

The control unit 202 may be electrically connected to the control circuit 203 to control the target signal of at least one of the plurality of IP cores 201 through the control circuit. The controlling of the target signal may include at least one of turning the target signal on and off. In some embodiments, the target signal may include a clock signal or a reset signal. Since the Control unit 202 can Control the Clock signal and the Reset signal of the system-on-chip, the Control unit 202 can be called a Global Control module (GRCC) for the Clock signal and the Reset signal.

In the case that the target signal includes a clock signal, the control unit 202 may be electrically connected to the clock switching unit of at least one of the plurality of IP cores 201, and configured to send a clock enable signal to the clock switching unit of the at least one IP core to control conduction of the transmission circuit of the clock signal of the at least one IP core, so as to correspondingly control a state of the clock signal of each IP core. The transmission circuit of the clock signal of one IP core is used for connecting the IP core and a signal source for generating the clock signal of the IP core, and under the condition that the transmission circuit of the clock signal is conducted, the signal source of the clock signal can output the clock signal to the corresponding IP core, namely the clock signal of the IP core is in an open state; when the transmission circuit of the clock signal is disconnected, the signal source of the clock signal is not output to the corresponding IP core, that is, the clock signal of the IP core is in an off state. By electrically connecting the control unit 202 with the clock switch unit, the clock enable signal output by the control unit 202 can be directly read by the clock switch unit, thereby improving the control efficiency of controlling the clock signal of the IP core.

The control unit 202 may be connected to at least one IP core of the plurality of IP cores 201 in a case where the target signal includes a reset signal, and configured to transmit the reset signal to the at least one IP core. The reset signal is asserted (also referred to as an on reset signal) at a first level and released (also referred to as an off reset signal) at a second level. The first and second levels may be high and low levels, respectively, or low and high levels, respectively. By connecting the control unit 202 with the IP core, the reset enable signal output by the control unit 202 can be directly read by the IP core, thereby improving the control efficiency of controlling the reset signal of the IP core.

In some embodiments, the control unit 202 may concurrently control the target signals of at least two IP cores of the plurality of IP cores 201. For example, in a certain boot mode, if it is necessary to boot the IP cores 1,2, and 3, it is necessary to concurrently control clock signals of the IP cores 1,2, and 3. For example, in a certain operation mode, if it is necessary to reset each IP core necessary for the function 1 and the function 2, it is necessary to concurrently control the reset signals of each IP core necessary for the function 1 and the function 2. It should be noted that the concurrent control does not require that the control on the target signals of the at least two IP cores occurs simultaneously, and may also control the target signals of the at least two IP cores sequentially according to a certain sequence.

The control unit 202 may control the target signal based on a plurality of control manners. In some embodiments, the control unit 202 may control the target signal based on the read first configuration information. For example, the control unit 202 may individually control the target signal of a certain IP core based on the read first configuration information for the IP core. Alternatively, the control unit 202 may also concurrently control the target signals of at least two of the plurality of IP cores based on the read first configuration information for the at least two of the plurality of IP cores. In this case, the first configuration information is used to indicate the at least two IP cores.

The first configuration information may be stored in a first register. The first register may be integrated inside the control unit 202, or may be physically separated from the control unit 202 and electrically connected to the control unit 202. In this way, the control unit 202 can directly read the first configuration information in the first register, and the time delay of the process is negligible, so that the control efficiency of the target signal is improved. In some embodiments, to facilitate reading the first configuration information, the first configuration information may be stored to at least one particular bit in the first register. The position information of the specific bit (i.e., which bit or bits in the first register the specific bit is) may be stored in the control unit 202.

Optionally, the control unit 202 may determine the at least two IP cores based on a mapping relationship between a plurality of preset control modes and preset coding information and the current coding information of the at least one specific storage bit, where the plurality of preset control modes correspond to different combinations of IP cores. For example, the preset encoding mode corresponding to the preset encoding information 0001 represents that the target signal of the IP core1 is individually controlled, the preset encoding mode corresponding to the preset encoding information 0010 represents that the target signal of the IP core 2 is individually controlled, and the preset encoding mode corresponding to the preset encoding information 0011 represents that the target signal of the IP core1 and the target signal of the IP core 2 are concurrently controlled. It will be appreciated by those skilled in the art that the encoded information described above may be other types of numerically encoded information, non-numerically encoded information, or a combination of numerically encoded information and non-numerically encoded information, in addition to the binary-valued encoded information described above.

Or alternatively, the control unit 202 may determine the at least two IP cores based on the location information of the specific bit, where each location information corresponds to a different combination of IP cores. For example, the specific bit being the 1 st bit in the first register represents that the target signal of the IP core1 is controlled separately, and the specific bit being the 2 nd bit in the first register represents that the target signal of the IP core1 and the target signal of the IP core 2 are controlled concurrently.

Or alternatively, the control unit 202 may determine the at least two IP cores based on bit number information of a significant bit in the specific bits, where the significant bit may be a bit taking a specific value, for example, a bit taking a value of 1. Wherein, each bit information corresponds to different IP core combinations. For example, the number of significant bits of the specific bits being 1 bit represents that the target signal of the IP core1 is controlled individually, and the number of significant bits of the specific bits being 2 bits represents that the target signal of the IP core1 and the target signal of the IP core 2 are controlled concurrently.

Or optionally, the number of the first registers is multiple, and different first registers or combinations of different first registers correspond to different IP core combinations. For example, the control unit 202 individually controls the target signal of the IP core1 when only a specific bit in the first register 1 is detected, and the control unit 202 concurrently controls the target signal of the IP core1 and the target signal of the IP core 2 when specific bits in the first register 1 and the first register 2 are detected.

In addition to the various manners described above, the control unit 202 may determine the at least two IP cores based on other manners, which are not described herein again.

In the case that the control unit 202 concurrently controls the target signals of the at least two IP cores, the control unit 202 may also concurrently control the target signals of the at least two IP cores based on the sequence and/or interval configured by the read second configuration information.

The interval may be based on a period of a clock signal (referred to as a first clock signal) of the control unit 202. One cycle of the target signal is called one beat, and the control unit 202 may control the target signal of a subsequent IP core of the at least two IP cores through n (n is a positive integer) beats when the target signal control of a previous IP core of the at least two IP cores is completed.

The second configuration information may be stored in a second register. The second register may be integrated inside the control unit 202, or may be physically separated from the control unit 202 and electrically connected to the control unit 202. In this way, the control unit 202 can directly read the second configuration information in the second register, and the time delay of the process can be ignored, so that the control efficiency of the target signal is improved. In some embodiments, to facilitate reading the second configuration information, the second configuration information may be stored to at least one particular bit in the second register. The position information of the specific bit in the second register may be stored in the control unit 202.

The control unit 202 may determine an order and/or an interval for controlling the target signals of the at least two IP cores based on a mapping relationship between a plurality of preset control modes and preset coding information and current coding information of the at least one specific storage bit. Wherein the plurality of preset control modes correspond to different sequences and/or combinations of intervals. For example, the preset control mode corresponding to the preset encoding information 0001 indicates that the control signals of the IP core1, the IP core 2, and the IP core 3 are sequentially controlled. For another example, the preset control pattern corresponding to the preset encoding information 0010 indicates that a control interval between the control signal of the first IP core and the control signal of the second IP core is 2 beats, and a control interval between the control signal of the second IP core and the control signal of the third IP core is 3 beats. For another example, the preset control mode corresponding to the preset encoding information 0011 indicates that the control signals of the IP core1, the IP core 2 and the IP core 3 are sequentially controlled, and the control interval between the control signal of the IP core1 and the control signal of the IP core 2 is 2 beats, and the control interval between the control signal of the IP core 2 and the control signal of the IP core 3 is 3 beats.

In addition to the above-described manners, the control unit 202 may determine the order and/or interval for controlling the target signals of the at least two IP cores based on other manners, for example, the order and/or interval for controlling the target signals of the at least two IP cores is determined based on the position information of the specific bit or the bit number information of the significant bit in the specific bit, or, in a case that the number of the second registers is multiple, the order and/or interval for controlling the target signals of the at least two IP cores may be determined based on different second registers or a combination of different second registers, and the manner for determining the at least two IP cores based on the first configuration information may be specifically referred to, and is not described herein again.

In some embodiments, the second configuration information may be carried in the first configuration information. That is, the first configuration information may indicate not only which IP core's target signals are concurrently controlled, but also in what order and/or interval the IP core's target signals are controlled. For example, the encoding information corresponding to the first configuration information is 0111, and the indicated IP cores and their sequence and interval are, in order: beat 1,2 of IP core, beat 2,3 of IP core and 3 of IP core. In other embodiments, the second configuration information may also be two pieces of configuration information that are independent from the first configuration information.

Alternatively, in a case where the target signal includes a clock signal, the first configuration information and the second configuration information may be stored in the same register. Optionally, in a case where the target signal includes a reset signal, the first configuration information and the second configuration information are stored in different registers. By storing the first configuration information and the second configuration information in different registers, the flexibility of control of the reset signal can be improved.

In some embodiments, the chip system further comprises a central processing unit 204, configured to write the first configuration information and the second configuration information into a register in one instruction cycle; and/or writing the first configuration information into a first register in a first instruction cycle, and writing the second configuration information into a second register in a second instruction cycle. The central processor 204 may be a single core processor or a multi-core processor, or may be a processor cluster including a plurality of processors, and each processor in the cluster may be a single core processor or a multi-core processor.

For example, in a case where the control signal includes a clock signal, the central processing unit 204 may write the first configuration information and the second configuration information corresponding to the clock signal into the same register in one instruction cycle. For another example, in a case where the control signal includes a reset signal, the central processing unit 204 may write first configuration information corresponding to the reset signal into the first register in the first instruction cycle, and write second configuration information corresponding to the reset signal into the second register in the second instruction cycle.

After writing the first configuration information and the second configuration information into the corresponding registers, the control unit 202 may directly read the first configuration information and the second configuration information in the corresponding registers, and control the clock signal or the reset signal of each IP core based on the read first configuration information and the read second configuration information.

In some embodiments, the control circuit 203 includes a plurality of switch units 205, and an enable terminal of each of the plurality of switch units 205 is electrically connected to the control unit 202 and one of the plurality of IP cores 201, respectively. The control unit 202 is configured to control a switching state of at least one switching unit in the plurality of switching units 205, so as to control on and/or off of a clock signal of a corresponding IP core. Each of the plurality of switch units 205 may be implemented using clock gating. The control unit 202 controls the on of the target signal of the corresponding IP core by controlling the on of the clock gating, and controls the off of the clock signal of the corresponding IP core by controlling the off of the clock gating.

The traditional control mode is a software control mode, and a competitive relationship exists between a signal carried out on a target signal and other signals sent by a CPU (central processing unit), so that the traditional control mode has low control efficiency, cannot accurately control the control time of the target signal of each IP core, and can only control the sequence of the target signal of each IP core. In the embodiment of the present disclosure, since the hardware control mode is adopted, the control unit 202 directly controls the clock signal and the reset signal based on the hardware connection, thereby improving the control efficiency. In addition, the control sequence can be accurately positioned to a certain beat of the first clock signal in a hardware mode, and the control accuracy is improved.

In order to distinguish the difference between the conventional signal configuration and the signal configuration of the embodiment of the present disclosure more clearly, two different signal configurations will be described with reference to fig. 4A, 4B and 4C. Suppose that the IP core1, the IP core 2, and the IP core 3 need to cooperatively work in a certain working scenario, and suppose that the states of the clock signals of the IP core1, the IP core 2, and the IP core 3 are off states in a default state.

As shown in fig. 4A, in the conventional clock signal configuration manner, a first register 1, a first register 2, and a first register 3 are respectively used for storing first configuration information corresponding to clock signals of an IP core1, an IP core 2, and an IP core 3, a CPU configures the first configuration information in the first register 1 in a first instruction cycle to control the clock signal of the IP core1, configures the first configuration information in the first register 2 in a second instruction cycle to control the clock signal of the IP core 2, and configures the first configuration information in the first register 3 in a third instruction cycle to control the clock signal of the IP core 3.

As shown in fig. 4B, in the clock signal configuration manner according to the embodiment of the present disclosure, first configuration information corresponding to the clock signals of the IP core1, the IP core 2, and the IP core 3 is stored by one register. The control of the clock signals of the IP core1, the IP core 2 and the IP core 3 can be finished at the same time only by configuring the first configuration information in one register. For example, in one instruction cycle, the first configuration information in the register is switched from "0" to "1", thereby controlling the clock signals of the IP core1, the IP core 2, and the IP core 3 from the off state to the on state. This way of controlling the clock signal becomes the fastboot control mechanism.

It can be seen that in the conventional configuration mode, software needs to configure multiple instruction cycles to complete control of clock signals of multiple IP cores; the fastboot mechanism can control the clock signals of the multiple IP cores only by one instruction cycle, so that the control time is saved, and the control efficiency is improved. In the embodiment of the present disclosure, from the working scenes of the chip system, the concurrent requirements of the clocks in each scene are distinguished, and the control information output by the control unit 202 is simultaneously connected to the clock paths of the multiple IP cores on the hardware by using the fastboot design and one software configuration, so as to turn on the required clock paths. For example, in a PCIE (peripheral component interconnect express) usage scenario, a bus clock required by the PCIE and a clock path of an internal state machine clock signal can be conducted together through the fastboot.

As shown in fig. 4C, rst1 to rst5 each indicate a reset signal corresponding to one function, and the reset signals of one or more IP cores required for each function need to be concurrently turned on or off. For example, the function corresponding to rst1 needs to concurrently turn on or off the reset signals of IP core1 and IP core 3, the function corresponding to rst4 needs to turn on or off the reset signal of IP core 3, and the function corresponding to rst5 needs to turn on or off the reset signal of IP core 4. In a certain scenario, reset signals of IP cores required by multiple functions need to be concurrently turned on or off, for example, reset signals of IP core 3 required by a function corresponding to rst4 and IP core 4 required by a function corresponding to rst5 need to be concurrently turned on or off. In addition to the software and hardware reset required by the functions of the IP core 3 and the IP core 4, a common reset control may be provided for the two in the design, for example, the common reset signal misc _ rstn of the IP core 3 and the IP core 4 in fig. 4C; this signal may be controlled by a single software address, one software instruction operating misc _ rst to assert and de-assert, will concurrently assert and de-assert the reset signals of IP core 3 and IP core 4. In this way, reset signals of the IP cores required for various functions can be concurrently asserted and released. This approach is referred to as a one-click reset control mechanism. The common reset signal may be configured based on the first configuration information described above, which may be stored in a register and configured by a piece of software. In addition, each IP core can also have a dedicated reset signal for controlling the reset signal of the IP core to be effective and released independently. In some embodiments, the reset signal is asserted high. The grey blocks in the figure represent or gates, and the reset signal of an IP core is asserted whenever one of the common reset signal and the dedicated reset signal of the IP core is asserted. The finally output reset signal of each IP core is IPi _ rst, i is 1,2,3 or 4.

In the embodiment of the disclosure, from the SoC scene, the IP cores working cooperatively are induced, the first configuration information result in the register is directly connected to the control end of the reset through one software configuration, the reset signals of the multiple IP cores are simultaneously effective and released, and the control efficiency of the reset signals is improved.

In some embodiments, the control unit 202 is further configured to control a clock signal of a third IP core based on a clock state (including an on state and an off state of the clock signal) of a second IP core of the plurality of IP cores, where the second IP core and the third IP core have a master-slave relationship therebetween. Specifically, the second IP core may be a master IP core, and the third IP core may be a slave IP core. The master IP core may be a user of the slave IP core. The above approach is referred to as a master-slave design mechanism.

The following describes the master-slave design mechanism by taking a specific application scenario as an example. FIG. 5 is a schematic diagram of a system-on-chip of some embodiments, including PMU, debug unit, DMA, DDR, CPU core0, CPU core1, WDT, NOC, and security control units. Cxo _ clk, rtc _ clk and jtag _ clk in the figure are all clock signals of GRCC, wherein cxo _ clk is a clock signal of GRCC in normal operation state and is also a clock signal of DDR. rtc _ clk is the clock signal of GRCC in bootup phase, and jtag _ clk is the clock signal of GRCC in debug phase. jtag _ rst and rtc _ rst are reset signals of the GRCC for resetting the state of the GRCC. The GRCC may output a reset signal, e.g., a reset signal rst for PMU.

In the process of data transportation from a DMA controller to a NOC bus in the SoC, a safety control unit is often needed to cooperate with the judgment whether the data conforms to the data allowed to be transported under the current safety mechanism. The data transfer path from the DMA to the NOC bus can be opened for data transfer with the transport allowed by the security control unit. In the conventional working mode, the CPU is required to frequently switch clock signals corresponding to the safety control unit and the NOC bus according to a control status register of a DMA internal state machine. This process increases the scheduling requirements of the CPU and the duration of the on clock signal.

In the disclosed embodiment, the control unit 202 may set the DMA and the security control unit, NOC bus as the same master-slave working family, and use the DMA as the master IP core of that family. When data is desired to be transferred from the DMA, the software need only configure the clock signals of the DMA to be on, and the security control unit and NOC bus will then automatically turn on the clock signals as a slave IP core without the CPU having to reconfigure the clock signals corresponding to the security control unit and NOC bus. The process reduces the dispatching of the CPU, shortens the clock conversion time and reduces the power consumption waste of the invalid time period.

In some embodiments, the control unit 202 may further control a clock signal of a fifth IP core based on voting information of each of at least two fourth IP cores of the plurality of IP cores 201, wherein the at least two fourth IP cores are users of the fifth IP core, and the voting information is used for indicating the clock signal of the fifth IP core to be turned on or off. This approach is referred to as a multi-user voting mechanism.

Alternatively, in a case where the clock signal of each of the plurality of fourth IP cores that are clock users of the fifth IP core is turned off, the control unit 202 turns off the clock signal of the fifth IP core. Optionally, in a case where a clock signal of any one of the plurality of fourth IP cores is turned on, the control unit 202 makes the clock signal of the fifth IP core in an on state. The plurality of fourth IP cores using the same fifth IP core is referred to as a vote group (vote group), and one fifth IP core is also referred to as a vote user (vote user).

In the slave SoC scene, the clock enabling signals of each master IP core of the slave IP cores are induced, and a multi-user voting mechanism is used to ensure that the states of the clock signals of the slave IP cores can be controlled based on a plurality of master IP cores at the same time; the state of the clock signal of the slave IP core may be turned off only when all master IP cores wish to control the state of the clock signal of the slave IP core to an off state. In practice, therefore, a plurality of voting users in a voting group can vote and send the voting result to the control unit 202. The state of the clock signals of the slave IP cores in the voting group will be controlled to the off state only if all voting users vote to control the state of the clock signals of the slave IP cores to the off state.

In the SoC application of the conventional multi-core CPU (i.e. the target first IP core), each CPU may use DDR, and the following scenario often occurs:

1) when the CPU core0 is used, the DDR needs to be read, so that the clock signal of the DDR is started by software configuration, and data transmission is performed after the clock status register is polled to be in the starting state; 2) DDR is also expected to be used during this time at the CPU core1, but because core0 is in use, polling waits for core0 to complete; 3) after the core0 is completed, the clock signal of the DDR is closed, and the core0 operation is completed; 4) after the core1 finds that the core0 is completed, the DDR clock is turned back on to match the core 1.

In this process, the clock of the DDR needs to be configured by software three times: 1) clock signal to turn on DDR for core0 process; 2) after the core0 is completed, the clock signal of the DDR is closed; 3) the DDR clock signal is turned on again for the core1 process. The DDR clock signal switch is operated frequently, the switching time length between the core0 and the core1 is prolonged, and software scheduling is increased.

In the embodiment of the disclosure, the CPU core0 and the CPU core1 may both be used as voting users of the DDR, and when one of the CPU core0 and the CPU core1 needs the clock signal of the DDR to be turned on, the clock signal of the DDR will be in an on state. Therefore, when the core1 does not occupy the DDR and the core0 is occupying the DDR, the clock signal of the DDR is still indicated to be turned on, and after the DDR responds to the completion of the clock turn-on requirement of the core0, the clock signal of the DDR can be directly responded to the requirement of the core1 without turning off the clock signal of the DDR, and the clock signal of the DDR is continuously kept in the turn-on state.

In some embodiments, the control unit 202 is further configured to use a status control signal of a first IP core of the plurality of IP cores 201 as a clock enable signal of the first IP core. For example, the first IP core may be an interface unit (e.g., a USB interface, etc.). The state control signal of the first IP core is used to indicate whether the first IP core is currently occupied, so that the control unit 202 determines whether the clock enable signal of the first IP core needs to be output currently to turn on the clock signal of the first IP core. For example, in a case that the state control signal of the first IP core indicates that the first IP core is currently occupied, the control unit 202 turns on a clock signal of the first IP core. For another example, the control unit 202 turns off the clock signal of the first IP core in a case where the status control signal of the first IP core indicates that the first IP core is currently unoccupied. In this way, the CPU is not required to control the state of the clock signal of the first IP core, and the burden of the CPU is reduced.

Compared with a traditional signal control mode, the embodiment of the disclosure realizes software and hardware cooperation, light CPU/software scheduling among multi-module cooperation (namely, the CPU is not required to realize the control of a target signal through multi-pen configuration), hardware quick response, further improvement of an effective clock power consumption use window and the like. From the perspective of scene use, designers can substitute frequent interactive scheduling between software and hardware through fastboot/master-slave mode/multi-user voting design/one-click reset control mechanism.

The design realization based on the method can support the clock control requirement under multiple scenes, reduce the participation of CPU/software, reduce the delay of scene switching caused by clock switching and improve the clock use efficiency under an effective scene window.

The foregoing is only a specific embodiment of the embodiments of the present disclosure, and it should be noted that, for those skilled in the art, a plurality of modifications and decorations can be made without departing from the principle of the embodiments of the present disclosure, and these modifications and decorations should also be regarded as the protection scope of the embodiments of the present disclosure.

Claims (12)

1. A chip system, comprising:

a plurality of IP cores, and

and the control unit is used for controlling a target signal of at least one IP core in the plurality of IP cores through a control circuit, wherein the target signal comprises a clock signal or a reset signal.

2. The chip system according to claim 1, wherein the control unit is configured to concurrently control on and/or off of target signals of at least two IP cores of the plurality of IP cores based on the read first configuration information, wherein the first configuration information is used to indicate the at least two IP cores.

3. The chipset system of claim 2, wherein the first configuration information occupies at least one specific storage bit of the register, and the control unit is configured to determine the at least two IP cores based on a mapping relationship between a plurality of preset control modes and preset coding information and current coding information of the at least one specific storage bit, wherein the plurality of preset control modes correspond to different combinations of IP cores.

4. The chip system according to claim 2 or 3, wherein the control unit is further configured to:

and on and/or off of target signals of the at least two IP cores are controlled concurrently based on the configured sequence and/or interval of the read second configuration information.

5. The system on a chip of claim 4, wherein the first configuration information and the second configuration information are stored in a same register if the target signal comprises a clock signal; and/or

In a case where the target signal includes a reset signal, the first configuration information and the second configuration information are stored in different registers.

6. The chip system according to claim 4 or 5, wherein the chip system further comprises a central processing unit for:

writing the first configuration information and the second configuration information into a register in one instruction cycle; and/or

The first configuration information is written into a first register in a first instruction cycle, and the second configuration information is written into a second register in a second instruction cycle.

7. The chip system according to any of the claims 1 to 6, wherein the control circuit comprises:

the enabling end of each switch unit in the switch units is respectively and electrically connected with the control unit and one IP core in the IP cores;

the control unit is used for: and controlling the switching state of at least one switching unit in the plurality of switching units so as to control the on and/or off of the clock signal of the corresponding IP core.

8. The chip system according to any one of claims 1 to 7, wherein the control unit is connected to at least one of the plurality of IP cores and configured to transmit a reset signal to the at least one IP core; and/or

The control unit is electrically connected with the clock switch unit of at least one of the plurality of IP cores and is used for sending a clock enable signal to the clock switch unit of the at least one IP core so as to control the conduction of the transmission circuit of the clock signal of the at least one IP core.

9. The chip system according to any of the claims 1 to 8, wherein the control unit is configured to:

and taking the state control signal of the first IP core in the plurality of IP cores as a clock enabling signal of the first IP core.

10. The chip system according to any of the claims 1 to 9, wherein the control unit is configured to:

controlling a clock signal of a third IP core based on a clock state of a second IP core of the plurality of IP cores, wherein the second IP core and the third IP core have a master-slave relationship therebetween.

11. The chip system according to any of the claims 1 to 10, wherein the control unit is configured to:

and controlling a clock signal of a fifth IP core based on voting information of each of at least two fourth IP cores in the plurality of IP cores, wherein the at least two fourth IP cores are users of the fifth IP core, and the voting information is used for indicating the clock signal of the fifth IP core to be turned on or off.

12. The chip system according to any of the claims 1 to 11, wherein the control unit is configured to:

turning off a clock signal of a fifth IP core in the case that the clock signal of each of a plurality of fourth IP cores which are clock users of the fifth IP core is turned off; and/or

Causing a clock signal of the fifth IP core to be in an ON state if a clock signal of any of the plurality of fourth IP cores is ON.