JP2000040376A - Semiconductor storage device - Google Patents

Abstract

(57) [PROBLEMS] To provide an FeRAM that operates stably with a wide operation margin and obtains high reliability by eliminating a ferroelectric capacitor for a reference cell. SOLUTION: A potential supply circuit 33 for supplying a potential between a low level and a high level of a cell plate 4 to a pair of bit lines 5 and 7 as a precharge potential, and the potential supply circuit 33 and each bit Conduction with lines 5 and 7
Transfer gates 31 and 32 for shutting off are provided, and after the end of precharge, the potential supply circuit 33 and the bit lines 5 and 7
When reading data from the ferroelectric capacitor 1 to the bit line 5, the differential amplifier 16 amplifies the precharge potential held on the bit line 7 as a reference potential.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device using a ferroelectric for a capacitance insulating film of a charge storage capacitor of a memory cell.

[0002]

2. Description of the Related Art At present, a typical semiconductor memory device is a dynamic random access memory (DRAM), but recently, a ferroelectric material using a ferroelectric material as an insulating film of a charge storage capacitor of the DRAM memory cell. A memory device (FeRAM) was developed. This memory device can be used as a non-volatile memory due to a characteristic of a ferroelectric material in which a DRAM remains volatile even when an external electric field is removed, while a DRAM is a volatile memory. In addition, existing rewritable nonvolatile memory devices have excellent characteristics such as low power consumption and high rewrite speed. For this reason, interest is increasing as a next-generation main memory device.

FIG. 8A is a voltage-charge amount characteristic diagram of a memory cell capacitor of a DRAM and a FeRAM. The horizontal axis represents the voltage V between both electrodes of the capacitor, and the vertical axis represents the charge amount Q stored in the electrode of the capacitor. There is. As shown in FIG. 8B, the direction of the voltage and the direction of the polarization are positive from the top to the bottom. The amount of charge Q stored in the capacitor is obtained by the product of the capacitor capacitance C and the voltage V between the capacitor electrodes. In a DRAM memory cell capacitor (paraelectric capacitor) using a paraelectric as an insulating film, the capacitance C Is specific to the capacitor and takes a constant value. When the voltage V is 0 volt, the charge amount Q is also 0.
Coulomb. The characteristic shown by the straight line in FIG. 8A is an example. On the other hand, Fe using a ferroelectric as an insulating film
RAM memory cell capacitor (ferroelectric capacitor)
Then, the capacitance C changes depending on the value and the history of the voltage V,
The charge amount Q when the voltage V is 0 volt also changes according to the history of the voltage V. The characteristic shown by the curve in FIG. 8A is an example.

Hereinafter, the voltage-charge amount characteristic of the ferroelectric capacitor represented by the curve in FIG. 8A will be described in detail. In the initial state, the ferroelectric capacitor has not been subjected to an electric field even once, and O
It is assumed that the state is indicated by a dot. As the voltage V between the two plates of the capacitor increases, the amount of charge Q generated at the electrodes increases along the path of the curve OA, and changes to the state at point A. At point A, a voltage is applied between both electrode plates of the capacitor, and the voltage causes electric charges to be generated in the electrode plates and polarization occurs in the ferroelectric material. Next, when the voltage V is reduced to 0, the state of the capacitor follows the path of the curve AB, and
Change to a point state. At point B, the voltage V between the two plates of the capacitor is 0, but since the polarization generated at point A remains in the ferroelectric material (residual polarization), charges are generated on the plates by the polarization. ing. Further, when the voltage V is applied in the negative direction, the state of the capacitor changes to the state at the point C following the path of the curve BC. At point C, a voltage in the opposite direction to that of point A is applied between the electrode plates, and a charge having a polarity opposite to that of A is generated in the electrode plate, and a polarization in the opposite direction is generated in the ferroelectric material. Further, when the voltage V is returned to 0, the state changes to the state of the point D by following the path of the curve CD. At the point D, the polarization generated at the point C remains in the ferroelectric material. A charge having a polarity opposite to that of the point B is generated on the plate. Further, when a positive voltage is applied again, the state changes to the state at the point A by following the path of the curve DA.

FIG. 9 shows one method of applying a ferroelectric capacitor having the above characteristics as a semiconductor memory device of FeRAM. FIG. 9A is a voltage-charge amount characteristic diagram of the ferroelectric capacitor similarly to FIG.
FIG. 9 shows a change in the state of a capacitor that occurs when data is read out to a bit line when applied to the memory cells shown in FIGS. Here, different data is written in the memory cell of FIG. 9B and the memory cell of FIG. 9C. 9 (b) and 9 (c).
1 is a ferroelectric capacitor for a memory cell, 2 is an NMOS
An access transistor composed of a transistor, 3 is a word line, 4 is a cell plate, 5 is a bit line, 6 is a stray capacitance of the bit line 5, and the direction of polarization in the ferroelectric capacitor 1 is shown in FIG. There is for the same as. Less than,
Regarding the principle of FeRAM data storage, FIG.
This will be described with reference to (b) and (c).

In the ferroelectric capacitor 1 of the memory cell shown in FIG. 9B, remanent polarization occurs when a voltage is applied in the positive direction, and the state is represented by a point B in FIG. 9A. You. Also, remanent polarization occurs when a voltage is applied in the negative direction to the ferroelectric capacitor 1 of the memory cell in FIG. 9C, and the state is represented by a point D in FIG. 9A. . FIG.
To read data from the memory cells shown in (b) and (c), first, the potential BL of the bit line 5 is precharged to the ground level, and then the potential WL of the word line 3 is
To turn on the access transistor 2 and raise the potential CP of the cell plate 4 to V _BC . Then, a negative voltage is applied to the ferroelectric capacitor 1, and FIG.
To the state of point C. However, since the voltage applied to the ferroelectric capacitor 1 is determined by dividing V _BC by the stray capacitance 6 of the bit line 5 and the ferroelectric capacitor 1, the voltage differs from the description in FIG. The state change of the ferroelectric capacitor 1 stops halfway to the point C.
That is, when in the state of point B in FIG. 9 (a), changes to point E on the curve B-C, the potential generated in the bit line 5 at that time is V _1. On the other hand, when it is in the state of the point D, it changes to the point F on the curve DC, and the potential of the bit line 5 at that time is V ₀ . At this time, the relationship between the bit line potentials is V ₁ > V ₀ . That is, if the state of the ferroelectric capacitor 1 in FIG. 9B is data “1”, the potential of the bit line 5 becomes H (high) level, and the state of the ferroelectric capacitor 1 in FIG. Is data "0", the potential of the bit line 5 becomes L (low) level.

As described above, data is stored in association with the direction of polarization of the ferroelectric capacitor 1, and when data is read from the memory cell to the bit line 5, the data is generated on the bit line 5 depending on the direction of polarization. It is the data storage principle of FeRAM to discriminate between data "1" and "0" using the difference in potential. FIG. 10 shows the F
Conventional 1 that stores data using the operating principle of eRAM
FIG. 2 is a circuit diagram of a memory cell column showing an example of a Tr-1C (1-Transistor 1-Capacitance) type semiconductor memory device. FIG.
At 0, 1 is a ferroelectric capacitor for a memory cell,
Reference numeral 2 denotes an access transistor formed of an NMOS transistor for accessing a memory cell, 3 denotes a word line, 4 denotes a cell plate, 5 and 7 denote bit lines, 9 denotes a ferroelectric capacitor for a reference cell, and 9 denotes a ferroelectric capacitor.
Is larger in area than the ferroelectric capacitor 1. Reference numeral 10 denotes an access transistor including an NMOS transistor for accessing a reference cell, 11 denotes a reference word line, 12 denotes a reference cell plate, and 13 and 14 denote NMOS transistors for precharging the bit lines 5 and 7 to ground potential. in charging transistor, 15 denotes a control signal line for supplying the control signal phi _b. 16 is a differential amplifier for amplifying a potential difference between the bit lines 5 and 7, here is composed of two clocked CMOS inverter capable of controlling the activity and non-activity by the control signal phi _s. 17 data lines, 19 a transfer gate for connecting the bit lines 5 and the lines 17, & their electrical conduction by the control signal phi _t
The interruption can be controlled.

FIG. 11 is a timing chart of a data read operation of the semiconductor memory device of FIG. In Figure 11, WL, CP, RWL, RCP, BL, / BL each word line 3, the cell plate 4, reference word line 11, the reference cell plate 12, the bit line 5, the potential of the bit line 7, phi _s , phi _b each differential amplifier 16, precharge transistors 13, 14
Is the level of the control signal.

A data read operation in the conventional semiconductor memory device will be described with reference to FIGS. In the initial state, all the nodes in FIG. 10 are at the ground potential, and it is assumed that data “0” is written in the ferroelectric capacitor 9 for the reference cell.
First, the potential W of the word line 3 and the reference word line 11
The access transistors 2 and 10 are turned on by increasing L and RWL, and the potentials CP and RCP of the cell plate 4 and the reference cell plate 12 are increased. Then, the bit line 5
The potential BL varies depending on the direction of spontaneous polarization of the ferroelectric capacitor 1 for the memory cell, and the potential / BL of the bit line 7 is the potential of the potential at the time of reading data "1" and data "0". A certain potential between them appears.
Then, the differential amplifier 16 to enable the control signal phi _s
Is activated, and the potential BL of the bit line 5 is amplified using the potential / BL of the bit line 7 as a reference. After amplification was completed, sends a control signal phi _t is turned on transfer gate 19 is enabled, the potential BL of the bit line 5 to the data line 17. The above is the reading operation in this device.

[0010]

In the conventional semiconductor memory device described above, it is necessary to determine whether the potential read from the memory cell to the bit line 5 is at the H (high) level or the L (low) level. As a reference potential, a capacitor having a larger area than the ferroelectric capacitor 1 for the memory cell is used as the ferroelectric capacitor 9 for the reference cell, and data “0” is written to the ferroelectric capacitor 9 and the data is written to the ferroelectric capacitor 9. Although it is generated by reading to the bit line 7, a capacitor having a smaller area than the ferroelectric capacitor 1 for the memory cell is used for the ferroelectric capacitor 9 for the reference cell, and the ferroelectric capacitor 9 is used for the ferroelectric capacitor 9. It may be generated by writing data “1” and reading it out to the bit line 7.

However, in any case, just H
It is not possible to design the area of the ferroelectric capacitor 9 for the reference cell that generates an intermediate potential between the L level and the L level, and to manufacture the ferroelectric capacitor 9 for the reference cell having certain characteristics as designed. Difficult due to manufacturing variability. There are also variations in the characteristics and bit line capacitance of the ferroelectric capacitor 1 for a memory cell, and these factors narrow the 1Tr-1C operation margin and realize a 1Tr-1C FeRAM device that operates stably. It is difficult to achieve high yields.

Since the characteristics of the ferroelectric capacitors 1 and 9 change due to stress during use of the device, the H-level and L-level potentials from the memory cell and the reference potential from the reference cell fluctuate during use. And the operation margin is narrowed, which is a major problem in reliability. SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the need for a ferroelectric capacitor for a reference cell, to operate stably with a wide operation margin, and to obtain a highly reliable FeR
An object of the present invention is to provide a semiconductor memory device which is an AM.

[0013]

According to a first aspect of the present invention, there is provided a semiconductor memory device comprising: a memory cell using a ferroelectric capacitor having a capacitive insulating film made of a ferroelectric; and data read from the memory cell when data is read from the memory cell. A first bit line, a second bit line paired with the first bit line, and a cell connected to one electrode of a ferroelectric capacitor of the memory cell for supplying a low-level potential and a high-level potential A plate, a potential supply circuit for supplying a potential between a high level and a low level of the cell plate as a precharge potential to the first bit line and the second bit line, a potential supply circuit, the first bit line, The first bit line is electrically connected to the second bit line during the precharge period and cut off during data reading.
And a second transfer gate, and a differential amplifier for amplifying a potential difference between the first bit line and the second bit line by using a precharge potential held on the second bit line as a reference potential when reading data. At the time of data reading, a period in which the cell plate supplies a low-level potential and a period in which the cell plate supplies a high-level potential are both present.

According to this configuration, the precharge potential of the bit line is set to a potential between the high level and the low level of the cell plate, and the second bit is read when data is read from the memory cell to the first bit line. Since the precharge potential held on the line is amplified as the reference potential, the ferroelectric capacitor for the reference cell, which was conventionally required to generate the reference potential, is eliminated, and its design and manufacturing Problems can be avoided. In addition, since the precharge potential is used as a reference potential and data is determined based on whether the potential of a bit line from which data is read is higher or lower than the precharge potential, the characteristics of a ferroelectric capacitor for a memory cell and the bit line The effect of the variation in capacitance is greatly reduced, and the same holds true for fluctuations in the characteristics of the ferroelectric capacitor during use. Therefore, an FeRAM that operates stably with a wide operation margin and has high reliability can be realized.

According to a second aspect of the present invention, there is provided a semiconductor memory device, wherein first and second memory cells using a ferroelectric capacitor having a capacitor insulating film made of a ferroelectric, and when data is read from the first memory cell. A first bit line from which data is read, a second bit line paired with the first bit line, and from which data is read from the second memory cell, and one electrode of a ferroelectric capacitor of the memory cell. A cell plate connected to supply a low-level potential and a high-level potential, and a potential between a high level and a low level of the cell plate as a precharge potential.
Potential supply circuit for supplying the bit line and the second bit line, and a first and a second circuit for conducting the potential supply circuit and the first bit line and the second bit line during the precharge period and cutting off the data read operation. 2 transfer gates,
Amplifying the potential difference between the first bit line and the second bit line using the precharge potential held on the second bit line as a reference potential when reading data from the first memory cell, And a differential amplifier for amplifying a potential difference between the first bit line and the second bit line by using the precharge potential held on the first bit line as a reference potential at the time of data reading. And a period in which the cell plate supplies a low-level potential and a period in which the cell plate supplies a high-level potential.

According to this configuration, in addition to the same effect as the first aspect, the data of the first memory cell is read out to the first bit line, and the data of the second memory cell is read out of the second bit line. Therefore, by alternately replacing the bit line for reading data and the bit line for maintaining the reference potential, the bit line can be effectively used and the area of the memory cell block can be reduced.

According to a third aspect of the present invention, in the semiconductor memory device according to the first or second aspect, a plurality of selectable potential supply circuits are provided, and the plurality of potential supply circuits supply different precharge potentials. It is made possible. With this configuration, it is possible to select a potential supply circuit that supplies different precharge potentials. Therefore, the ferroelectric capacitor characteristics for a memory cell at the time of P detection (during device inspection in a wafer state immediately after the completion of diffusion) and the time of device use It is possible to select an optimal precharge potential in accordance with the characteristic fluctuation of the above, and it is possible to optimize the operating conditions to operate more stably.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 is a circuit diagram of a memory cell column of a semiconductor memory device according to a first embodiment of the present invention.
1 shows an r-1C type FeRAM. In FIG. 1, 1 is a ferroelectric capacitor for a memory cell, 2 is an access transistor comprising an NMOS transistor for accessing the memory cell, 3 is a word line, 4 is a cell plate, 5 and 7 are bit lines (5 is a first bit line, the second bit line 7), 16 is a differential amplifier for amplifying a potential difference between the bit lines 5 and 7, wherein it controls the active and non-active by the control signal phi _s clocked CMOS inverter 2 It is composed of individual pieces. 17 is a data line, 19 is a transfer gate connecting the bit line 5 and the data line 17, and a control signal φ
The electrical conduction / interruption can be controlled by _t . 31 and 32 respectively transfer gates connecting the bit lines 5 and 7 and the potential supply circuit 33, it is possible to control the electrical conduction and interruption thereof by a control signal phi _m. The potential supply circuit 33 can supply an arbitrary potential.

The semiconductor memory device of this embodiment is similar to that of FIG.
0 and the access transistor 1 for the ferroelectric capacitor 9 for the reference cell in the conventional example shown in FIG.
A potential supply circuit 33 for eliminating a 0 or the like and supplying a precharge potential to a pair of bit lines 5 and 7, and a transfer gate 31 for conducting / cutting off the potential supply circuit 33 and the respective bit lines 5 and 7. , 32 are provided.
The potential supply circuit 33 supplies a potential between the L level and the H level of the cell plate 4 to the bit lines 5 and 7 as a precharge potential.

FIG. 2 is a timing chart of a first data read operation in the semiconductor memory device of FIG.
CP, BL and / BL are the potentials of the word line 3, cell plate 4, bit line 5 and bit line 7, respectively, and φ _s and φ
_m is the differential amplifier 16 and the transfer gate 31
32 control signal levels. A data read operation in this device will be described with reference to FIGS. Here, the description will be made with the L level of the cell plate 4 as the ground and the H level as the power supply voltage.

As an initial state, the transfer gates 31 and 32 in FIG. 1 are in an on state, and the bit lines 5 and 7 are precharged by the potential supply circuit 33 to a potential intermediate between the ground level and the power supply voltage level. All other nodes are at ground potential. First, after completion of the precharge control signal φ transfer gates 31 and 32 are turned off by _m, to turn on the access transistor 2 by raising the potential WL of word line 3. Then, charges move from the bit line 5 to the ferroelectric capacitor 1 in accordance with the data written in the ferroelectric capacitor 1, and the potential BL of the bit line 5 decreases.

Next, when the potential CP of the cell plate 4 is raised, the electric charge moves from the ferroelectric capacitor 1 to the bit line 5 in accordance with the data written in the ferroelectric capacitor 1, and the bit line 5 Potential BL rises. Eventually, the potential BL of the bit line 5 becomes higher than the bit line precharge potential when data “1” is written in the ferroelectric capacitor 1, and when the data “0” is written, It becomes lower than the bit line precharge potential.
The variation of the potential is amplified to activate the differential amplifier 16 to enable the control signal phi _s, precharge potential was kept at the bit line 7 (/ BL) as the reference potential. After amplification was completed, the control signal phi _t to enable to turn on the transfer gate 19, the read operation is completed by sending the potential BL of the bit line 5 to the data line 17.

The principle of the data reading operation will be described with reference to FIGS. FIG. 3 is a diagram for explaining the principle of the data read operation. 3A, 3B, and 3C, reference numeral 6 denotes a stray capacitance of the bit line 5, and the directions of voltages of the ferroelectric capacitor 1 and the bit line stray capacitance 6 are the same as those in FIG. 8B. The direction from the top to the bottom is positive. FIG. 4 is a voltage-charge amount characteristic diagram of the ferroelectric capacitor 1 for a memory cell.
The horizontal axis indicates the voltage V between the two electrodes of the capacitor, and the vertical axis indicates the amount of charge Q stored in the electrodes of the capacitor. FIG. 4 shows a state change of the ferroelectric capacitor 1 that occurs when the read operation shown in FIGS. 3A, 3B, and 3C is performed.

FIG. 3A shows a state immediately before data is read out. The bit line stray capacitance 6 is precharged at the potential V _B0 , and the voltage generates a charge Q _{B0 on the} electrode plate. The ferroelectric capacitor 1 is in a state shown by a point B in FIG. 4 and the voltage V between the plates is 0, but the charge Q _S0 is generated due to the residual polarization of the ferroelectric. Bit line stray capacitance 6
Value C _B of when placed a capacitance value of the ferroelectric capacitor 1 and C _S, although C _B takes a constant value, C _S is the voltage of FIG. 4 - depending on the position on the curve showing the charge quantity characteristics With different values. One electrode plate of the bit line stray capacitance 6 is connected to the ground, and the other electrode plate is in a high impedance state. One electrode plate of the ferroelectric capacitor 1 is connected to the cell plate 4 maintained at the ground level, and the other electrode plate is in a high impedance state.

From this state, the potential of the word line 3 is raised, the access transistor 2 is turned on, and the bit line floating capacitor 6 and the ferroelectric capacitor 1 are in a high impedance state as shown in FIG. When the plates are electrically connected, charges move from the bit line floating capacitance 6 to the ferroelectric capacitor 1 until the voltage of the two capacitors (1, 6) becomes equal to the voltage between the plates. The voltage V _B1 and the charge Q _B1 are applied to the stray capacitance 6, and the voltage V _B1 is applied to the ferroelectric capacitor 1.
_S1 and charge _QS1 are generated and stabilized. Further, the state of the ferroelectric capacitor 1 changes to the state at the point G following the curve BG in FIG. When the bit line potential V _B1 in this stable state is obtained, Q _B0 + Q _S0 = Q _B1 + Q _S1 (1) In addition, since the voltages of both capacitors are equal, V _B1 = V _S1 (2) Since the amount of charge stored in the capacitor is the product of the capacitance value and the voltage between the plates, the amount of charge in the bit line stray capacitance 6 is Q _B0 = C _B · V _B0 Q _B1 = C _B · V _B1 .

Ferroelectric substance from point B to point G in FIG.
The state change of the capacitor 1 is approximated by a straight line connecting two points, and
The slope of C_S1, The charge of the ferroelectric capacitor 1
Quantity Q _S1Is Q_S1= C_S1・ V_S1+ Q_S0 (3) Substituting these into equation (1) gives C_B・ V_B0+ Q_S0= C_B・ V_B1+ C_S1・ V_S1+ Q_S0 Further, when rearranging by substituting equation (2), C_B・ V_B0= (C_B+ C_S1) ・ V_B1 Therefore, the bit line potential V_B1Is V_B1= ｛C_B/ (C_B+ C_S1)｝ ・ V_B0 (4)

[0027] Then raised to a power supply potential V _D potential CP cell plate 4 as shown in FIG. 3 (c), the now FIG 3 (b)
If the charge moves from the ferroelectric capacitor 1 to the contrary to the bit line stray capacitance 6, the bit line stray capacitance of the voltage V _D 6
And the voltage V _B2 divided by the capacitance of the ferroelectric capacitor 1
And V _S2 are generated and stabilized. At this time, the charges Q _B2 and Q _S2 are stored in the bit line stray capacitance 6 and the ferroelectric capacitor 1, respectively.
Has occurred. Further, the state of the ferroelectric capacitor 1 changes to the state at the point H following the curve GH in FIG. When the bit line potential V _B2 in this stable state is obtained, from the law of conservation of electric charge, Q _B0 + Q _S0 = Q _B2 + Q _S2 (5) Also, the sum of the bit line floating capacitance 6 and the voltage of the ferroelectric capacitor 1 since but it becomes the voltage V _D, the charge amount of _{V B2 -V S2 = V D (} 6) bit line stray capacitance 6 becomes _{Q B0 = C B · V B0} Q B2 = C B · V B2.

When the state change of the ferroelectric capacitor 1 from the point G to the point H in FIG. 4 is approximated by a straight line connecting two points, the slope is C _S2 , and the Q contact piece is Q ₂ , the approximate straight line _{is, Q = C S2 · V +} Q 2 the approximate line from passing through the point G and substituting obtain the relation of the charge amount Q and the voltage V of the G point from equation _{(3), C S1 · V} S1 + Q S0 = C _{When S2} · V _S1 + Q _{2 is} transformed, (C _S1 −C _S2 ) · V _S1 + Q _S0 = Q ₂ Therefore, the charge amount of the ferroelectric capacitor 1 becomes Q _S2 = C _S2 · V _S2 + (C _S1 −C _{S2 ) · V S1 + Q S0 (} 7) When these are substituted into equation _{(5), C B · V} B0 + Q S0 = C B · V B2 + C S2 · V S2 + (C S1 -
When _{C S2) · V S1 + Q} S0 organized by substituting equation to _{(6), C B · V} B0 = (C B + C S2) · V B2 -C S2 · V D + (C
_S1 -C _S2) · V _S1 further equations (2) from equation (4), and substituting the value of _{V S1, C B · V B0} = (C B + C S2) · V B2 -C S2 · V D + _{(C S1 -C S2) · {} C B / (C B + C S1)} · V B0 C B · V B0 · {1- (C S1 -C S2) / (C B + C S1)} + C S2 · V _D = (C _B + C _S2 ) · V _B2 C _B · V _B0 · {(C _B + C _S2 ) / (C _B + C _S1 )} + C _S2 · V _D = (C _B + C _S2 ) · V _B2 V _B2 = _{C B · V B0 / (C} B + C S1) + C S2 · V D / (C B + C S2) become (8).

As shown in the equation (8), the bit line potential V _{B2 in} FIG. 3C is the precharge potential V _B0 , the cell plate potential V _D , the bit line stray capacitance C _B , and the ferroelectric capacitor 1 It is determined by the relationship between the approximate capacitances C _S1 and C _S2 , but generally tends to be higher than the precharge potential V _B0 when C _S1 is smaller than C _S2 . The ferroelectric capacitor 1 corresponds to B in FIG.
If at point because C _S1 <C _S2, the bit line potential V _B2 by adjusting the C _B and V _B0 or V _D is higher than the precharge potential V _B0. In short, when electric charges move from the bit line stray capacitance 6 to the ferroelectric capacitor 1, a positive voltage is applied to the ferroelectric capacitor 1 and the change in polarization is small, so that the amount of movement is small. When electric charges move from the dielectric capacitor 1 to the bit line floating capacitance 6, a negative voltage is applied to the ferroelectric capacitor 1, and the amount of movement is increased due to a large change in polarization. 5 has been transferred, and the potential of the bit line 5 rises.

Also, when the ferroelectric capacitor 1 before reading data is in the state of the point D in FIG. 4, the bit line potential V _B2 can be obtained in the same manner. In that case, C _S1 > C
_{Since it is S2} , the bit line potential V _B2 is lower than the precharge potential V _B0 . That is, when electric charges move from the bit line stray capacitance 6 to the ferroelectric capacitor 1, a positive voltage is applied to the ferroelectric capacitor 1 and a large change in polarization causes a large amount of movement. When the electric charge moves to the bit line stray capacitance 6, a negative voltage is applied to the ferroelectric capacitor 1 and the amount of movement is small due to a small change in polarization. As a result, the electric charge is transferred to the ferroelectric capacitor 1. Has moved, and the potential of the bit line 5 drops.

According to the above-described principle, the potential of the bit line 5 after reading data is higher or lower than the precharge potential depending on the type of data, so that it is possible to determine data using the precharge potential as a reference. It becomes. According to this embodiment, bit line 5
And 7 are set to potentials between the H level and the L level of the cell plate 4, and when reading data from the ferroelectric capacitor 1 to the bit line 5, the precharge potential held on the bit line 7 Is amplified as a reference potential, so that a ferroelectric capacitor for a reference cell, which is conventionally required for generating a reference potential, can be eliminated, and problems in design and manufacture can be avoided. Also, since the precharge potential is used as a reference potential and data is determined based on whether the potential of the bit line 5 from which data is read is higher or lower than the precharge potential, the characteristics and bit of the ferroelectric capacitor for a memory cell are determined. The effect of the variation in line capacitance is greatly reduced, and the same holds true for fluctuations in ferroelectric capacitor characteristics during use. Therefore, 1Tr-1 which operates stably with a wide operation margin and has high reliability
A C-type FeRAM can be realized.

In the present embodiment, the L level of the cell plate 4 has been described as ground and the H level has been described as the power supply voltage. However, the operation can be performed with the L level of the cell plate 4 being lower than the ground level. If
The precharge potentials of the bit lines 5 and 7 can be set to the ground level, and the potential supply circuit 33 can be simplified.

When the level of the word line 3 is raised,
When the potential of the cell plate 4 is raised, the charge moves between the ferroelectric capacitor 1 and the bit line 5, but before the movement of the charge stops and the state is stabilized, the potential of the cell plate 4 is raised. Also, an operation of activating the differential amplifier 16 is possible, and the access time can be reduced.

FIG. 5 is a timing chart of the second data reading operation in the semiconductor memory device of FIG. In the second data reading operation, the potential C of the cell plate 4 is changed with respect to the first data reading operation timing shown in FIG.
The details are the same except that after raising P to the H level, once returning to the L level and then raising to the H level again, detailed description is omitted, but the potential CP of the cell plate 4 is repeatedly raised and lowered twice or more as described above. Therefore, an operation of activating the differential amplifier 16 is also possible.

[Second Embodiment] FIG. 6 shows a second embodiment of the present invention.
FIG. 3 is a circuit diagram of a memory cell column of the semiconductor memory device according to the embodiment, showing a 1Tr-1C type FeRAM. In FIG. 6, reference numeral 21 denotes a ferroelectric capacitor for a memory cell, 22 denotes an access transistor including an NMOS transistor for accessing the memory cell, 23 denotes a word line, 24 denotes a cell plate, 18 denotes a data line, and 20 denotes a bit line 7. And the data line 18 can control their electrical conduction / interruption by the control signal φ _t2 . Note that the transfer gate 19 connecting the bit line 5 and the data line 17 is controlled here by a control signal φ _t1 . Other components are the same as those in FIG.

In the above-described first embodiment, in all the memory cells, the ferroelectric capacitors 1 for the memory cells are used.
Is read out to the bit line 5 via the access transistor 2. However, in the second embodiment, the bit line 7 paired with the bit line 5 is also connected to the ferroelectric capacitor 21. Access transistor 2
The data line 18 is connected to the bit line 7 via a transfer gate 20. When the ferroelectric capacitor 1 from which data is read to the bit line 5 in FIG. 6 is a first memory cell and the ferroelectric capacitor 21 from which data is read to the bit line 7 is a second memory cell, a memory cell array is formed. If the first memory cell and the second memory cell are provided in each memory cell column,
There is no particular limitation on the arrangement of the memory cell and the second memory cell.

In this configuration, the operation of the word lines 3 and 23, the cell plates 4 and 24, and the transfer gates 19 and 20 is the same as that of the first embodiment except that the operation side is selected. In addition, since the transfer gates 19 and 20 are controlled by different signals φ _t1 and φ _t2 , it is possible to connect only the bit line from which data is read to the data line. There is no problem if both are turned on and the two bit lines 5 and 7 are connected to the data lines 17 and 18, respectively.

According to this embodiment, access transistors 2.22 are connected to bit lines 5 and 7 forming a pair, respectively.
By connecting the ferroelectric capacitors 1 and 21 of the memory cell via the memory cell and alternately switching the bit line for reading data and the bit line for keeping the reference potential, the bit line is effectively used, and the first embodiment is used. Can reduce the area of the memory cell block. That is, the first
In the second embodiment, one bit line 7 for reference potential which is paired with the bit line 5 from which data is read is required. In the second embodiment, the bit line on which data is not read is connected to the reference potential. By using it for
Since there is no bit line used only for the reference potential, the number of bit lines required to read the same number of bits is the first
Of the embodiment of the present invention.

The cell plate 4 and the cell plate 24
Can be shared, so that the area of the memory cell block can be further reduced. [Third Embodiment] FIG. 7 is a circuit diagram of a memory cell column of a semiconductor memory device according to a third embodiment of the present invention.
1 shows an r-1C type FeRAM. In FIG. 7, 41, 4
,..., 43 are potential supply circuits, the potentials of which are different for each circuit. Reference numerals 44, 45,..., 46 denote switch elements, and other components are the same as those in FIG.

In this embodiment, instead of the potential supply circuit 33 of FIG. 6, a plurality of potential supply circuits 41, 42,... , 42,..., 43 are provided. With this configuration, one of the potential supply circuits 41, 42,..., 43 is selected by the switch elements 44, 45,. The potential can be selected. Other configurations and operations are shown in FIG.
Is the same as the second embodiment shown in FIG. According to this embodiment, the same effects as those of the second embodiment can be obtained, and the potential supply circuits 41, 42,..., Which supply different bit line precharge potentials, respectively.
43 can be selected by the switch elements 44, 45,..., 46, so that the memory cell capacitor characteristics at the time of P inspection (at the time of device inspection in a wafer state immediately after the end of diffusion) and the characteristic fluctuation at the time of device use In this case, an optimum bit line precharge potential can be selected according to the operating conditions, and the operation conditions can be optimized to operate more stably.

Also in the first embodiment, FIG.
A plurality of potential supply circuits 4 in place of
, 43, and switch elements 44, 45,.
, 46, the same effect can be obtained. Note that instead of the switch elements 44 to 46,
A plurality of potential supply circuits 41, 42,..., 43 may be provided with a switching circuit that can be selectively connected.

[0042]

According to the present invention, when the precharge potential of a bit line is set to a potential between a high level and a low level of a cell plate and data is read from a memory cell to one of the paired bit lines, Since the precharge potential held on the other bit line is amplified as the reference potential, the ferroelectric capacitor for the reference cell, which was conventionally required to generate the reference potential, is eliminated and its design and Manufacturing problems can be avoided. In addition, since the precharge potential is used as a reference potential and data is determined based on whether the potential of a bit line from which data is read is higher or lower than the precharge potential, the characteristics of a ferroelectric capacitor for a memory cell and the bit line The effect of the variation in capacitance is greatly reduced, and the same holds true for fluctuations in the characteristics of the ferroelectric capacitor during use. Therefore, an FeRAM that operates stably with a wide operation margin and has high reliability can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a memory cell column of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a timing chart of a first data reading operation in the semiconductor memory device according to the first embodiment;

FIG. 3 is a diagram illustrating the principle of a data read operation according to the first embodiment;

FIG. 4 is a voltage-charge amount characteristic diagram showing a state change of a ferroelectric capacitor when data is read in the first embodiment.

FIG. 5 is a timing chart of a second data read operation in the semiconductor memory device according to the first embodiment;

FIG. 6 is a circuit diagram of a memory cell column of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 7 is a circuit diagram of a memory cell column of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 8 is a diagram showing a voltage-charge amount characteristic (hysteresis characteristic) of a memory cell capacitor of FeRAM and DRAM.

FIG. 9 is a diagram showing a memory cell capacitor voltage-charge amount characteristic (hysteresis characteristic) and a state change of a ferroelectric capacitor when data is read from an FeRAM which is a conventional semiconductor memory device.

FIG. 10 is a circuit diagram of a memory cell column of a conventional semiconductor memory device.

FIG. 11 is a timing chart of a data read operation in a conventional semiconductor memory device.

[Explanation of symbols]

 1,21 Ferroelectric capacitor for memory cell 2,22 Access transistor 3,23 Word line 4,24 Cell plate 5,7 Bit line 16 Differential amplifier 17,18 Data line 19,20 Transfer gate 31,32 Transfer Gate 33, 41, 42, 43 Potential supply circuit 44, 45, 46 Switch element

Claims (3)

[Claims] 1. A memory cell using a ferroelectric capacitor having a capacitor insulating film made of a ferroelectric, a first bit line from which data is read when reading data from the memory cell, and a first bit line. A second bit line paired with a cell plate connected to one electrode of a ferroelectric capacitor of the memory cell and supplying a low-level potential and a high-level potential; and a high level and a low level of the cell plate. A potential supply circuit that supplies a potential between the first and second levels as a precharge potential to the first bit line and the second bit line; and a potential supply circuit, the first bit line, and the second bit line. First and second transfer gates that conduct during a precharge period and cut off during data reading, and are held by the second bit line during data reading; A differential amplifier for amplifying a potential difference between the first bit line and the second bit line using the precharge potential as a reference potential. A semiconductor memory device in which a supply period and a period for supplying a high-level potential are both present. 2. A first and a second memory cell using a ferroelectric capacitor having a capacitance insulating film made of a ferroelectric, and a first bit from which data is read when data is read from the first memory cell. A second bit line paired with the first bit line, from which data is read when reading data from the second memory cell; and a second bit line connected to one electrode of a ferroelectric capacitor of the memory cell. A cell plate for supplying a level potential and a high level potential; a potential for supplying a potential between a high level and a low level of the cell plate to the first bit line and the second bit line as a precharge potential A first supply line, a first supply line, and a first bit line and a second bit line, which are turned on during a precharge period and cut off when reading data. And and a second transfer gate, the second from the first memory cell when reading data
The potential difference between the first bit line and the second bit line is amplified using the precharge potential held on the bit line as a reference potential, and the first memory cell reads the first memory cell when reading data from the second memory cell. A differential amplifier that amplifies a potential difference between the first bit line and the second bit line using a precharge potential held on a bit line as a reference potential; A semiconductor memory device in which a period for supplying a low-level potential and a period for supplying a high-level potential are both present. 3. A plurality of selectable potential supply circuits are provided,
3. The semiconductor memory device according to claim 1, wherein each of the plurality of potential supply circuits can supply a different precharge potential.