JP2000040749A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method of forming certain conductivity-type MIS transistors which differ from each other in threshold voltage in a chip, without increasing mask processes in number. SOLUTION: This manufacturing method is carried out in a manner, where the gate electrodes 6 of a first and a second MIS transistor, Tr1 and Tr2, which are different from each other in a channel direction are formed on an Si substrate 2, and then oblique ion implantations 12a to 12d in four steps are carried out for the formation of pocket regions 8a and 8b. At this point, and angle that a projection line of the direction of ion implantations 12a and 12b onto the surface of the semiconductor substrate 2 forms with a line parallel with the channel direction of the gate electrode 6 is set different from that which is related to the ion implantations 12c and 12d, and also the ion implantations 12a and 12b, and the ion implantations 12c and 12d are different from each other in dosage of ions implanted. Through this method, the first and second MIS transistor, Tr1 and Tr2, whose threshold voltages are different can be provided in a single chip.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an improvement in a method of manufacturing a semiconductor device having a plurality of types of MIS transistors having different threshold voltages from each other.

[0002]

2. Description of the Related Art Conventionally, two or more kinds of MIS transistors of the same conductivity type having different threshold voltages from each other are mixed in one chip. For example, a circuit requiring high speed requires a high threshold voltage. There is known a transistor in which the type of the MIS transistor can be selected according to the function of the circuit, such as disposing a transistor having a low threshold voltage in a circuit requiring low power consumption. . In particular, in recent years, the number of cases in which high-speed operation and low power consumption are compatible with the entire chip has been increasing by mixing two or more types of MIS transistors having different threshold voltages from each other in one chip (1997). VLSI Symp
osium Technology Digest p.13 Nikkei Microdevices August 1997, p.113).

In this case, as a method of realizing a threshold voltage between MIS transistors of the same conductivity type, there are a method of changing a thickness of a gate insulating film and a method of changing a concentration of a channel region in a substrate. In particular, as a method of changing the impurity concentration of a channel region in a substrate, for example, the following method is generally used.

FIGS. 6A and 6B are cross-sectional views showing a method of forming two MIS transistors having different threshold voltages in one chip.

In the step shown in FIG.
A LOCOS film 102 surrounding the active region is formed in
A first resist mask 105 having an opening above the first well 103 and the second well 104 surrounded by the OCOS film 102 is formed. Then, the first resist mask 10
5, ions of an n-type impurity are implanted into the first well 103 and the second well 104, for example.

Next, in a step shown in FIG. 6B, after removing the first resist mask 105, a second resist mask 106 having an opening only above the first well 103 is formed. Then, ion implantation of an n-type impurity is performed only in the first well 103 using the second resist mask 106. At this time, generally, the same conductivity type impurity is ion-implanted as in the step shown in FIG. 6A, so that the impurity concentration of the first well 103 is increased. Therefore, the threshold voltage of the MOS transistor formed on the first well 103 is higher than the threshold voltage of the MOS transistor formed on the second well 104. However, in the step shown in FIG. 6B, ions of a p-type impurity having a conductivity type opposite to that of the step shown in FIG. 6A are implanted (counter implantation), and the first well 103 has a lower concentration. May be included. At that time, the MOS transistor formed on the first well 103 becomes a low threshold voltage MOS transistor.

[0007]

However, if the above-mentioned conventional general manufacturing process is used, two types of one conductivity type MOs are used.
Two mask formation steps are required to adjust the threshold voltage of the S transistor. And generally, CMO
Since the S process is employed, a total of four mask forming steps are required for adjusting the threshold voltages of the two types of MOS transistors. If a CMOS device in which three or more types of MOS transistors having different threshold voltages are provided for both an NMOS transistor and a PMOS transistor is to be formed, an extremely large number of masks are formed only for adjusting the threshold voltage. A process is required. As a result, there is a problem that the manufacturing cost is greatly increased.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide means for forming transistors having a plurality of types of threshold voltages in a minimum number of mask forming steps, thereby achieving high speed operation. It is an object of the present invention to provide a method of manufacturing a semiconductor device which can manufacture a semiconductor device having low power consumption and low power consumption at low cost.

[0009]

SUMMARY OF THE INVENTION In view of the above, the present invention provides a method of forming a pocket region, a low-concentration source / drain region or a source / drain region after forming a plurality of gate electrodes having different channel directions. Is to change the conditions for performing the ion implantation for each step.

A first method for manufacturing a semiconductor device according to the present invention comprises:
A method of manufacturing a semiconductor device, comprising providing at least two MIS transistors of the same conductivity type having different threshold voltages on a semiconductor substrate, wherein the MIS transistors have different channel directions. Forming a gate electrode of at least two MIS transistors, and implanting impurity ions of a first conductivity type using the gate electrode as a mask,
Forming a source / drain region of an S-type transistor and implanting impurity ions of the second conductivity type using the gate electrode as a mask by 10 ° from a perpendicular to the semiconductor substrate surface;
A step of forming a pocket region in at least one of the source and drain regions of at least one of the two MIS transistors by performing the above-described inclined direction; Performing a heat treatment for activation.

According to this method, since the pocket regions of each MIS transistor have different shapes,
The threshold voltage of each MIS transistor will be different. In this case, a mask for forming a pocket region or the like of each MIS transistor can be used in common, so that it is not necessary to increase the number of mask forming steps to change the threshold voltage as in the related art. Therefore, high-speed operation and low power consumption can be realized while reducing the manufacturing cost of the semiconductor device.

In the first method for fabricating a semiconductor device, the step of forming the pocket region may include at least two steps.
In each step, the intersection angle between the projection line on the semiconductor substrate surface in the ion implantation direction in each step and the line parallel to the channel direction of the at least two gate electrodes is made different from each other. At least one of the corner and the implantation energy can be different in each step.

According to this method, it is possible to provide a larger threshold voltage difference.

In the first method for fabricating a semiconductor device, impurity ions of a first conductivity type are implanted by using the gate electrode as a mask, and the at least two MISs are implanted.
Forming a low-concentration source / drain region of a type transistor; and forming a sidewall on a side surface of the gate electrode, wherein the step of forming the source / drain region includes the step of forming the gate electrode and the sidewall. The step of forming the pocket region by implanting impurity ions of the first conductivity type serving as a mask can be performed before the step of forming the sidewalls.

According to this method, a semiconductor device including a miniaturized MIS transistor having a so-called LDD structure can be formed.

According to a second method of manufacturing a semiconductor device of the present invention,
A method of manufacturing a semiconductor device, comprising providing at least two MIS transistors of the same conductivity type having different threshold voltages on a semiconductor substrate, wherein the MIS transistors have different channel directions. Forming a gate electrode of at least two MIS transistors; and implanting impurity ions of the first conductivity type using the gate electrode as a mask by 10 ° from a perpendicular to the semiconductor substrate surface.
From at least two of the M
Forming a low concentration source / drain region of the IS type transistor, forming a sidewall on the side surface of the gate electrode, and implanting impurity ions of the first conductivity type using the gate electrode and the sidewall as a mask. And forming a high-concentration source / drain region of the at least two MIS transistors; and performing a heat treatment for activating the impurities implanted in each of the steps. The step of forming the drain region is performed in at least two steps, and the intersection of the projection line of the ion implantation direction onto the semiconductor substrate surface in each step and the line parallel to the channel direction of the at least two gate electrodes The angles are made different from each other, and at least one of the injection amount, the tilt angle, and the injection energy One or Re are different at each step.

According to a third method of manufacturing a semiconductor device of the present invention,
A method of manufacturing a semiconductor device, comprising providing at least two MIS transistors of the same conductivity type having different threshold voltages on a semiconductor substrate, wherein the MIS transistors have different channel directions. Forming a gate electrode of at least two MIS transistors; and implanting impurity ions of the first conductivity type using the gate electrode as a mask by 10 ° from a perpendicular to the semiconductor substrate surface.
From at least two of the M
Forming a source / drain region of the IS type transistor; and performing a heat treatment for activating the impurities implanted in the above-described step.
The step of forming the drain region is performed in at least two steps, and an intersection angle between a projection line of the ion implantation direction on the semiconductor substrate surface in each step and a line of the at least two gate electrodes parallel to the channel direction. Are different from each other, and at least one of the implantation amount, the inclination angle, and the implantation energy is different in each step.

According to the above-described second and third manufacturing methods of the semiconductor device, the source / drain regions or the low-concentration source / drain regions of each MIS transistor have different densities and shapes. The threshold voltage of the MIS transistor will be different. In that case,
Since a mask for forming a pocket region and the like of each MIS transistor can be used in common, there is no need to increase the number of mask forming steps to change the threshold voltage as in the related art. Therefore, high-speed operation and low power consumption can be realized while reducing the manufacturing cost of the semiconductor device.

[0019]

DETAILED DESCRIPTION OF THE INVENTION FIGS. 1 (a), 1 (b) and 1 (c)
A plan view of a semiconductor device according to an embodiment of the present invention,
FIG. 1A is a cross-sectional view taken along the line Ib-Ib, and FIG.
It is sectional drawing in the -Ic line.

As shown in FIGS. 1A to 1C, a semiconductor device according to this embodiment has a p-well 4 formed on a p-type Si substrate and a LOCOS film formed on the p-well 4. 3, first and second active regions Re1 and Re2 surrounded by the LOCOS film 3, and first and second n-type MOS transistors Tr1 and Tr1 formed in the active regions Re1 and Re2, respectively having different threshold voltages. Tr2. Here, in the p well 4, a source / drain region 9 into which arsenic (As) as a high concentration n-type impurity is introduced, and an LDD region 7 (low concentration source / drain) into which low concentration phosphorus is introduced. Region) is formed. Also, on p-well 4,
A gate oxide film 5 made of silicon oxide, a gate electrode 6 made of polysilicon, and an insulator sidewall 13 made of silicon oxide are provided.
Each of the OS transistors Tr1 and Tr2 includes, as constituent elements, a source / drain region 9, an LDD region 7, a gate oxide film 5, a gate electrode 6, and an insulator sidewall 13 having the same structure. Further, an interlayer insulating film 10 is deposited on the substrate, and the source / drain region 9 is formed on the interlayer insulating film 10 via a conductor film embedded in a contact hole formed in the interlayer insulating film 10. Wiring 1 connected to
1 is formed.

Here, the semiconductor device according to the present embodiment is characterized in that, in the first and second MOS transistors Tr1 and Tr2, pocket regions containing p-type impurities are respectively provided in regions adjacent to the lower side of each LDD region 7. 8a and 8b are formed, and the pocket regions 8a and 8b of the transistors Tr1 and Tr2 have different impurity concentrations. Since the impurity concentrations in the pocket regions 8a and 8b are different from each other, the threshold voltages Vt of the first and second MOS transistors Tr1 and Tr2 are different from each other.

FIG. 2 shows the implantation length (dose) of boron ions (B ⁺ ) per step when a pocket region is formed by four-step implantation (rotation by 90 °) as a parameter and the gate length of an nMOS transistor. FIG. 6 is a diagram illustrating a relationship with a threshold voltage. In the figure, the horizontal axis represents the gate length Lg (μm), and the vertical axis represents the threshold voltage Vt (V).
Is represented. The data indicated by □, ○, and Δ in the figure indicate that boron ions were implanted in one step by an oblique ion implantation method at a tilt angle of 25 ° and 10 ¹² c per step.
^These are data obtained by performing pocket implantation at doses of m ⁻² , 2 × 10 ¹² cm ⁻² , and 3 × 10 ¹² cm ⁻² . Also,
Data indicated by ● in the figure is data obtained for an nMOS transistor in which pocket injection has not been performed.

As shown in the figure, it can be seen that the threshold voltage of the MOS transistor can be adjusted by changing the amount of impurity ions implanted into the pocket region in the oblique ion implantation method. In particular, when the gate length Lg is about 0.5
In an nMOS transistor of μm or less, the decrease in the threshold voltage Vt decreases as the amount of implanted boron ions increases. As a result, as the gate length Lg becomes shorter, that is, as the semiconductor device becomes finer, the width of adjustment of the threshold voltage Vt by the amount of boron ions implanted becomes wider. Further, as the dose increases, the gate length dependence of the threshold voltage Vt of the nMOS transistor decreases, that is,
This means that the short channel effect is small.

As described above, according to the semiconductor device of the present embodiment, by making the impurity concentration of the pocket region different among a plurality of MOS transistors provided on a common chip, the plurality of MOS transistors have different thresholds. It can be configured to have a value voltage. That is,
Even if the impurity concentration in the channel region is not changed, it becomes possible to mix a plurality of threshold voltage transistors in one chip only by adjusting the pocket injection.

Next, the manufacturing process of the semiconductor device according to this embodiment will be described. 3A to 3E are cross-sectional views illustrating main steps of a method for manufacturing the nMOS device according to the present embodiment. 3A to 3E are cross-sectional views taken along the line Ib-Ib in FIG.
1E are cross-sectional views taken along line Ic-Ic in FIG.

First, in a step shown in FIG. 3A, an LO having a thickness of about 300 nm is formed in a predetermined region of the P-type Si substrate 2 having an impurity concentration of 1 × 10 ¹⁵ cm ^-3 so as to surround the active region.
A COS film 3 is grown, and boron ions (B ⁺ ) are implanted into the active region of the Si substrate 2 to form a P well 4.
However, the P well 4 is a buried well,
It is composed of three layers, a punch-through stopper and a threshold voltage control region (channel region) (not shown). The formation of the buried well, the punch-through stopper and the threshold voltage control region is 400 keV, 1 × 10 ¹³ cm
^-2 condition, 100 keV, 3 × ¹² cm ^-2 condition, 20k
It is formed by implanting B ⁺ under the conditions of eV and 1 × 10 ¹² cm ⁻² .

Next, in a step shown in FIG. 3B, after forming a gate insulating film 5 and a gate electrode 6 on the P well 4, a resist mask 20 having an opening on the active region is formed on the substrate.
To form Then, using the resist mask 20 and the gate electrode 6 as a mask, phosphorus ions (P ⁺ ) are
V is implanted under the condition of 2 × 10 ¹³ cm ⁻² to form an LDD (low concentration source / drain) region 7 in the P well 4.

Next, in the step shown in FIG. 3C, a pocket region is formed by two-step ion implantation. First,
Using the resist mask 20 and the gate electrode 6 as a mask,
The angle θ1 = 25 with respect to the perpendicular to the substrate surface, parallel to the channel direction (gate length direction) of the first MOS transistor Tr1.
Boron ions (B ⁺ ) from the direction inclined only 20 ke
V, implanted under the condition of 1 × 10 ¹² cm ⁻² (implantation 12
a). Thereafter, the entire substrate is rotated 180 ° about a line perpendicular to the substrate surface, and boron ions (B ⁺ ) are implanted under the same conditions (20 keV, 1 × 10 ¹² cm ⁻² ) (implantation 1).
2b). At this time, both of the implantations 12a and 12b are orthogonal to the channel direction of the gate electrode 6 of the second MOS transistor Tr2, and are parallel to the gate width direction.
As a result, the first MOS transistor Tr1 has L on both sides.
A pocket region 8x extending from a region below the DD region 7 to a region entering the channel region side is formed.
In the OS transistor Tr2, a pocket region 8y including only a region below the LDD regions 7 on both sides is formed.

The inclination angle of the ion implantation direction for forming the pocket region is 10 ° to 60 ° with respect to the perpendicular to the substrate surface.
The angle may be in the range of 10 ° to 45 °.

Next, in the step shown in FIG. 3D, the second MO is formed using the gate electrode 6 and the resist mask 20 as a mask.
Boron ions (B ⁺ ) are implanted under the conditions of 20 keV and 1.5 × 10 ¹² cm ⁻² from a direction parallel to the channel direction of the S transistor Tr2 and inclined at an angle θ2 = 25 from a direction perpendicular to the substrate surface ( Injection 12c). In other words, a higher concentration of impurities is introduced than in the step shown in FIG. Thereafter, the entire substrate is rotated by 180 ° about a line perpendicular to the substrate surface, and boron ions (B ⁺ ) are subjected to the same conditions (20 keV,
1.5 × 10 ¹² cm ⁻² ) (implantation 12d). At this time, both of the implantations 12c and 12d are orthogonal to the channel direction of the gate electrode 6 of the first MOS transistor Tr1, and are parallel to the gate width direction. as a result,
In both the first and second MOS transistors Tr1 and Tr2, the pocket regions 8a and 8 extending from the region below the LDD region 7 on both sides to the region entering the channel region side.
Although b is formed, the pocket region 8b of the second MOS transistor Tr2 contains a higher concentration of impurity when comparing the impurity concentration in the region that has entered the channel region side. MOS transistor threshold voltage Vt
Is greatly influenced by the impurity concentration in the region of the pocket region which enters the channel region side, and the characteristics shown in FIG. 2 indicate that the second MOS transistor Tr2 has a higher threshold voltage Vt. Specifically, in the MOS transistor having a gate electrode with a gate length of 0.25 μm of the present embodiment, the threshold voltage of the first MOS transistor Tr1 is about 0.33 V,
The threshold voltage Vt of the MOS transistor Tr2 is about 0.5
It was 5V. Note that the data in FIG. 2 is an evaluation result when four steps of implantation are performed under the same conditions with a parameter as a dose per one step, and thus does not become direct data in the manufacturing method of the present embodiment. The control of the threshold value is substantially determined by the implantation conditions of the impurity ions entering below the gate electrode, and thus can sufficiently serve as reference data of the present embodiment.

Thereafter, in the step shown in FIG. 3E, after the resist mask 20 is removed, a silicon oxide film is deposited on the substrate and then anisotropically etched to form the gate electrode 6 and the gate oxide film. The insulator side wall 13 is formed on the side surface of the fifth electrode 5. Then, arsenic ions (As) are formed using the gate electrode 6, the insulator sidewalls 13, and a resist mask (not shown) formed at a predetermined position as a mask.
⁺ ) Is implanted into the substrate under the conditions of 20 keV and 5 × 10 ¹⁵ cm ⁻² to form the high-concentration source / drain regions 9.
Further, after removing the resist mask, a predetermined heat treatment is performed to activate the implanted impurities.

Although illustration of the subsequent steps is omitted, the interlayer insulating film 10 and the wiring 11 shown in FIG. 1 are formed by using a known technique.

According to the method of manufacturing a semiconductor device of this embodiment, a plurality of gate electrodes whose gate length directions are orthogonal to each other are formed on a substrate, and the gate electrodes are used as a mask to incline from a perpendicular to the substrate surface. Pocket area 8 from the direction
Impurity ions for forming a and 8b are implanted in four steps (implantation 12a to 12d) and implanted.
The implantation conditions of a and 12b are different from the implantation conditions of the implantations 12c and 12d (in this embodiment, the dose of the impurity). As a result, in the pocket region 8a of the first MOS transistor Tr1 and the pocket region 8b of the second MOS transistor Tr2, the impurity concentration of the portion that enters the channel region side is different from each other. The threshold voltages Vt of the transistors Tr1 and Tr2 are different. Moreover, FIGS. 3 (b) to 3 (d)
Is performed using a common resist mask 20.

It is clear that such a difference in the threshold voltage Vt is caused not only by the difference in the impurity concentration but also by the difference in the shape of the pocket region, particularly, the difference in how the pocket region enters the channel region. That is, the threshold voltage Vt can be adjusted also by the difference in the inclination angle and the difference in the implantation energy at the time of ion implantation. That is, MOS
A plurality of MOS transistors having pocket regions having different shapes and different impurity concentrations can be formed in accordance with the channel direction of the transistors, and a plurality of transistors having different threshold voltages Vt can be formed without adding a mask step. Can be mixed on one chip.
Therefore, high-speed operation and low power consumption of the semiconductor device can be realized at low cost.

(Other Embodiments) In the above embodiment,
In order to maintain the symmetry of the source / drain regions after the pocket implantation, the implantations 12a and 12b for forming the pocket regions 8a and 8b have the same conditions, and the implantations 12c and 12d have the same conditions. , 12c, 12
Any of the conditions of d may be different from each other.

In the step shown in FIG. 3C, for example, only the implantation 12a may be performed. In that case, the first M
Since the shapes of the pocket regions 8x and 8y are different between the OS transistor Tr1 and the second MOS transistor Tr2,
A plurality of transistors Tr1 and Tr2 having different threshold voltages Vt can be formed. That is, it is not always necessary to perform pocket injection divided into a plurality of steps.

Further, instead of changing the dose amount in the pocket implantation, the inclination angle θ and the implantation energy may be changed, or these parameters may be changed in combination.

In the case of low-concentration source / drain implantation or high-concentration source / drain implantation instead of pocket implantation, similarly to the above-mentioned pocket implantation, the dose, tilt angle, and implantation energy in oblique ion implantation are similar. Differences may be used or they may be combined.

FIG. 4 is a diagram showing a change in the threshold voltage Vt with respect to the concentration of an n-type impurity (phosphorous ion P ⁺ ) for forming an LDD region of an n-channel MOS transistor. In the figure, the vertical axis represents the threshold voltage Vt, and the horizontal axis represents the gate length Lg. As shown in the figure, the threshold voltage Vt decreases as the dose increases, and it can be seen that the difference in the threshold voltage Vt of the MOS transistor can be realized also by the difference in the impurity concentration in the LDD region. . Similarly, the threshold voltage Vt of the MOS transistor can be changed by changing the conditions for implanting the impurity ions for forming the high-concentration source / drain regions.

In the above embodiment, a plurality of types of MOS transistors whose channel directions are orthogonal to each other are provided on the substrate. However, a plurality of types of MOS transistors whose channel directions intersect at various angles may be provided.

FIG. 5 shows two types of first and second MOS transistors Tr1 and Tr2 having gate electrodes whose channel directions are orthogonal to each other, and that the channel direction is 45 ° with respect to the channel direction of each of the MOS transistors Tr1 and Tr2. FIG. 14 is a layout diagram illustrating an example of a semiconductor device in which third MOS transistors Tr3 intersecting at an angle are provided in one chip. As shown in the drawing, for example, by performing ion implantation 12a to 12d in the same manner as in the above embodiment, the first MOS transistor having the highest threshold voltage Vt and the second MOS transistor having the lowest threshold voltage Vt are provided. Transistors and
A third MOS transistor Tr3 having an intermediate threshold voltage Vt is formed.

In the above embodiment, an n-channel MOS transistor has been described as an example. However, it is needless to say that the present invention can be applied to a p-channel MOS transistor.

In the above embodiment, the ion implantation is performed in four steps. However, three or two steps may be performed, or the number of steps may be more than four. Also, the rotation angles of the substrate about the normal line of the substrate for each step do not need to be at equal intervals. Although the low concentration source / drain regions are formed using phosphorus ions, for example, arsenic ions are implanted at a dose of, for example, 10 ¹⁴ to 10 ¹⁵ cm ⁻² ,
Low concentration source / drain regions may be formed.

In the above embodiment, a MOS transistor has been described as an example. However, a transistor having a gate insulating film formed of a nitride film or an oxynitride film may be used.
It goes without saying that the present invention can be applied to all S-type transistors.

[0045]

According to the first method of manufacturing a semiconductor device of the present invention, at least two channels having different channel directions are formed on a substrate.
One gate electrode is provided, and ion implantation is performed in an oblique direction using the gate electrode as a mask.
By forming a pocket region on one side under one gate electrode, a plurality of one-conductivity-type MISs having different threshold voltages can be formed without adding a new mask process.
Since the type transistor can be formed in one chip, high-speed operation and low power consumption of the semiconductor device can be realized at low cost.

According to the second method of manufacturing a semiconductor device of the present invention, at least two gate electrodes having different channel directions are provided on a substrate, and the gate electrodes are used as masks to perform oblique directions by at least two steps. By performing ion implantation under different implantation conditions to form LDD regions or source / drain regions, a plurality of one conductivity type having different threshold voltages can be formed without adding a new mask process. 1 MIS transistor
Since the semiconductor device can be formed in a chip, high-speed operation and low power consumption of the semiconductor device can be realized at low cost.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a gate length dependence characteristic of a threshold voltage of an n-channel MOS transistor using an impurity concentration of a pocket region as a parameter.

FIG. 3 is a view illustrating the method of manufacturing the semiconductor device according to the embodiment.

FIG. 4 is a diagram showing the gate length dependence of the threshold voltage of an n-channel MOS transistor using the impurity concentration of an LDD region as a parameter.

FIG. 5 shows each MO in a semiconductor device according to another embodiment.
FIG. 3 is a plan view showing a layout of a gate electrode of an S transistor.

FIG. 6 is a cross-sectional view illustrating a manufacturing process of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 P-type Si substrate 3 LOCOS 4 P well 5 Gate oxide film 6 Gate electrode 7 Low concentration source / drain region 8 Pocket region 9 High concentration source / drain region 10 Interlayer insulating film 11 Wiring 12 Injection 13 Insulator sidewall 20 Resist mask

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor device, comprising providing at least two MIS transistors of the same conductivity type having different threshold voltages on a semiconductor substrate, wherein the MIS transistors have different threshold voltages. Forming the gate electrodes of the at least two MIS transistors, and implanting impurity ions of the first conductivity type using the gate electrodes as masks, so that the source and the source of the at least two MIS transistors are different. Forming a drain region and implanting impurity ions of the second conductivity type using the gate electrode as a mask from a direction inclined by 10 ° or more from a perpendicular to the semiconductor substrate surface to form the two MIS transistors At least one of the source / drain regions of at least one MIS transistor Forming a preparative area, a method of manufacturing a semiconductor device which comprises a step of performing heat treatment for activating the impurity implanted in the above process. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the pocket region is performed in at least two steps, and a projection line of the ion implantation direction onto the semiconductor substrate surface in each step. And a crossing angle of the at least two gate electrodes with a line parallel to the channel direction is made different from each other, and at least one of an injection amount, a tilt angle, and an injection energy is different in each step. A method for manufacturing a semiconductor device. 3. The method of manufacturing a semiconductor device according to claim 1, wherein impurity ions of a first conductivity type are implanted by using said gate electrode as a mask, and said low-concentration source of said at least two MIS transistors is implanted. Forming a drain region; forming a sidewall on a side surface of the gate electrode; forming the source / drain region in the first conductive layer using the gate electrode and the sidewall as a mask; A step of forming the pocket region by implanting impurity ions of a mold, and the step of forming the pocket region is performed before the step of forming the sidewall. 4. A method of manufacturing a semiconductor device, comprising providing at least two MIS transistors of the same conductivity type having different threshold voltages on a semiconductor substrate, wherein the MIS transistors have different threshold voltages. Forming the gate electrodes of the at least two MIS transistors so as to be different from each other, and implanting impurity ions of the first conductivity type using the gate electrodes as masks by 10 ° or more from a perpendicular to the semiconductor substrate surface. Forming a low-concentration source / drain region of the at least two MIS transistors, forming a sidewall on a side surface of the gate electrode, and using the gate electrode and the sidewall as a mask. 1
Implanting conductive impurity ions to form high-concentration source / drain regions of the at least two MIS transistors; and performing a heat treatment for activating the implanted impurities in each of the steps. The step of forming the low-concentration source / drain regions is performed in at least two steps, and a projection line of the ion implantation direction onto the semiconductor substrate surface in each step and a channel of the at least two gate electrodes are formed. The angle of intersection with the line parallel to the direction is made different from each other.
At least one of tilt angle and implantation energy
A method for manufacturing a semiconductor device, wherein each method is different in each step. 5. A method of manufacturing a semiconductor device, comprising: providing at least two MIS transistors of the same conductivity type having different threshold voltages on a semiconductor substrate, wherein the MIS transistors have at least two different threshold voltages. Forming the gate electrodes of the at least two MIS transistors so as to be different from each other, and implanting impurity ions of the first conductivity type using the gate electrodes as masks by 10 ° or more from a perpendicular to the semiconductor substrate surface. Forming a source / drain region of the at least two MIS transistors in a direction, and performing a heat treatment for activating the impurities implanted in the step. Is performed in at least two steps, and ion implantation in each step is performed. Angles of the projection lines on the semiconductor substrate surface in different directions and lines parallel to the channel direction of the at least two gate electrodes are made different from each other, and at least one of the implantation amount, the inclination angle, and the implantation energy is adjusted in each step. A method for manufacturing a semiconductor device, the method comprising: