JP2000046897A - Test apparatus and test method for CMOS integrated circuit - Google Patents

Abstract

(57) [Summary] [PROBLEMS] Since a resistance component is used for current detection, a voltage that decreases according to a flowing IDDQ current value varies in various ways. Cannot be corrected and given. A P-channel MOSFET which becomes a current sensing element and whose back gate potential can be controlled by applying a voltage to a terminal VBG, and a P-channel MOSFET
P-channel MOSFET whose gate is connected and whose back gate potential can be controlled by applying a voltage to VBG for the purpose of amplifying a current value and converting it to a voltage level
3, N-channel MOSFET for current limiting 4,
Inverters 5 and 6 functioning as output buffers are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test apparatus and a test method for a CMOS integrated circuit for measuring a static leakage current flowing to a power supply terminal of a CMOS integrated circuit and judging pass / fail based on the magnitude of the leak current.

[0002]

2. Description of the Related Art Conventionally, a method of measuring IDDQ, which is a leak current flowing through a power supply terminal, has been used for detecting a defect in a CMOS integrated circuit, particularly in a large-scale integrated circuit. C
A MOS integrated circuit has a property that a large current flows only at the time of a state transition of an internal circuit or an internal node, and almost no current flows at the time of rest.

[0003] By utilizing this property, a defect is detected by an IDDQ test. If there is a resistive short which conducts to a certain part of the internal circuit or internal node and the power supply or ground (GND) with a certain resistance value, if the resistance value is extremely large, logically "0" Alternatively, even though the level is determined to be “1”, a current causing a slight change in the voltage level flows. The IDDQ test detects this current and detects a defect inside the CMOS integrated circuit.

In the IDDQ test, it is necessary to measure when the state of each node is "0" and when it is "1". Therefore, the IDDQ test is performed while changing the internal state of the CMOS integrated circuit as needed. Conventionally, this has been done by using a function test pattern for testing the logic function of a CMOS integrated circuit for the purpose of detecting stuck-at faults,
A power supply current measuring device is installed between a power supply supplied to the integrated circuit and the CMOS integrated circuit, and an IDDQ test is performed.

[0005]

A prior art relating to a power supply current measuring device is disclosed in, for example, Japanese Patent Application Laid-Open No. 7-248353. In this prior art, a CMO
A power supply current measuring device is installed between a power supply supplied to the S integrated circuit and the CMOS integrated circuit, and the IDDQ of the CMOS integrated circuit is provided.
Testing is possible.

In such prior art, although the measurement time is somewhat improved due to the contrivance of the circuit, a current detecting resistor element for an IDDQ test installed between a power supply and a CMOS integrated circuit) is used for a circuit. The power supply voltage actually supplied to the CMOS integrated circuit is reduced, and in some cases, the CMO is generated when an inrush current occurs during a state transition in which a large amount of current flows.
The supply voltage to the S integrated circuit may drop abnormally, possibly destroying the CMOS integrated circuit.

In addition, since the resistance component is used for current detection as described above, the voltage lowered by the flowing IDDQ current value varies variously. It is also impossible to give a correction. Furthermore, since a resistance component is used for current detection, it takes a long time to stabilize the current waveform, that is, to settle to the current waveform at rest, which results in a longer measurement time.

Further, since it takes a long time to settle to the quiescent current waveform, even when the IDDQ current measurement is performed using a test pattern for a normal function test, the operating frequency is extremely slowed down. I needed to test. For this reason, the function test and the IDDQ test need to be performed separately even though the same test pattern for a normal function test is used. Was inviting.

[0009]

A CMO according to claim 1
The test apparatus for the S integrated circuit measures a power supply current at rest of the CMOS integrated circuit and compares and determines the power supply current with a reference value. In a CMOS integrated circuit test apparatus having a means, a first MOSFET whose back gate potential is adjustable is used as the power supply current detecting means, and
A source for applying a power supply voltage is connected to a source of the first MOSFET, and a power supply terminal of a CMOS integrated circuit is connected to a drain of the first MOSFET.

According to a second aspect of the present invention, in the testing apparatus for a CMOS integrated circuit, the current-to-voltage conversion means can adjust a back gate potential, and the first MO of the power supply current detection means.
A second MOS in which the SFET and the back gate are commonly connected
An FET and a current limiting circuit connected to the drain of the second MOSFET. The first MOSFET of the power supply current detecting means and the second MOSFET of the current-voltage converting means.
And a current mirror connection with the SFET.

According to a third aspect of the present invention, there is provided a test apparatus for a CMOS integrated circuit, comprising:
3. The testing device for a CMOS integrated circuit according to claim 1, wherein the ET and the second MOSFET of the current-voltage converter are constituted by depletion type transistors.

According to a fourth aspect of the present invention, there is provided a method of testing a CMOS integrated circuit using the CMOS integrated circuit test apparatus according to any one of the first to third aspects. By appropriately controlling the back gate potential of the first MOSFET, the threshold potential of the first MOSFET is set to approximately 0V.

Further, according to a fifth aspect of the present invention, there is provided a method of testing a CMOS integrated circuit, comprising using the CMOS integrated circuit test apparatus according to the second or third aspect of the present invention.
In the test method for an OS integrated circuit, a comparison determination reference value is set based on a current limit value of a current limit circuit constituting the current-voltage conversion unit.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, based on one embodiment,
The present invention will be described in detail.

FIG. 1 shows a CMO according to a first embodiment of the present invention.
FIG. 2 is a block diagram of a test apparatus for an S integrated circuit, and FIG.
MOSFET I- in MOS integrated circuit test equipment
FIG. 3 is a graph showing V characteristics, and FIG. 3 is a graph showing C characteristics according to the second embodiment of the present invention.
FIG. 4 is a configuration diagram of a testing device for a CMOS integrated circuit according to a third embodiment of the present invention.

The testing device for a CMOS integrated circuit according to the present embodiment is a P-channel MOSFET 2 which serves as a current sensing element and can control the back gate potential by applying a voltage to a terminal VBG.
P-channel MOSFET whose gate and gate are connected and whose back gate potential can be controlled by applying a voltage to VBG for the purpose of amplifying the current value and converting it to a voltage level
3, N-channel MOSFET for current limiting 4,
Inverters 5 and 6 functioning as output buffers are provided.

The connection configuration of the test apparatus for a CMOS integrated circuit according to the first embodiment will be described.

When measuring the power supply current, a P-channel MOSFET is used.
The source electrode of T2 is connected to VDD2, and the drain electrode is connected to VDD1 (power supply) terminal of CMOS integrated circuit 1. P-channel MOSFET2 and P-channel MOS
A voltage for controlling the threshold potential near 0 V is applied to the back gate of the FET 3 from the terminal VBG. Note that P
Channel MOSFETs 2 and 3 are depletion type M
In the case of the OSFET, it is not necessary to apply such a voltage for controlling the back gate.

Further, the drain electrode of the P-channel MOSFET 2 is connected to the gate electrode of the P-channel MOSFET 2, and the gate electrode of the P-channel MOSFET 2 is also connected to the gate electrode of the P-channel MOSFET 3. That is, the P-channel MOSFET 2 and the P-channel MOSFET 3 are current mirror connected.

The source electrode of this P-channel MOSFET 3 is connected to VDD2 in the same manner as the source electrode of the P-channel MOSFET 2, and the drain electrode is an N-channel MOSFET.
Connected to the drain electrode of SFET4. The source electrode of the N-channel MOSFET 4 is grounded to GND. The source electrode of the P-channel MOSFET 3 is connected to the input of the inverter 5, and the output of the inverter 5 becomes the input of the inverter 6. The output of the inverter 6 is connected to a determination device such as a tester, and can take in the level at an arbitrary timing.

The measuring method of the power supply current measuring device for a CMOS integrated circuit according to the first embodiment will be described.

A test pattern is applied to the CMOS integrated circuit 1 to activate internal logic. When there is an IDDQ defect, an IDDQ current flows from the source electrode to the drain electrode of the P-channel MOSFET 2 to some extent. At this time, since a potential is applied to the back gate of the P-channel MOSFET 2 so that its threshold voltage becomes substantially 0 V, the potential at V1 has a voltage drop due to the ON resistance of the P-channel MOSFET 2, but is substantially the same as VDD2. It is.

At this time, the ON resistance of the P-channel MOSFET 2 is determined by the gate length and the gate width which determine the size of the MOSFET. Further, since this potential is the gate voltage of the P-channel MOSFET 2, the P-channel MOSFET 2 is self-biased with the gate voltage required to flow the IDDQ current.

Next, since the gate electrode of the P-channel MOSFET 3 is connected to the gate electrode of the P-channel MOSFET 2, a current equal to the drain current of the P-channel MOSFET 2 flows to the drain current of the P-channel MOSFET 3. Therefore, P-channel MOS
The potential of V2, which is on the drain electrode side of FET3, rises sharply when the drain current of MOSFET3 becomes larger than the saturation current of N-channel MOSFET4.

For example, using 10 μA as a criterion for determination,
FIG. 1 shows the operation of the circuit when the DDQ current is detected.
This will be described with reference to FIG. The potential of V2 is
, The gate potential VG and the drain-source potential VDS of the N-channel MOSFET 4 are VG = VDS and Vth
That is, the gate length and gate width of the MOSFET 4 may be determined so that IDS = 10 μA when DS = Vth. The potential of V2 is inverted and amplified by the inverter 5, but is again inverted by the inverter 6 and output with the same polarity as the original.

However, the inverter 5 and the inverter 6 perform the functions of voltage amplification and current buffer for transmitting the potential of V2 to the outside, and the polarity may be either direction. Also, the number of inverters is not limited. Further, a simple buffer may be used instead of the inverter.

Further, by using the power supply current measuring device according to the present invention as current detecting means and appropriately controlling the back gate potential of the MOSFET,
By using depletion type MOSFETs for ET2 and ET3, the threshold potential of these MOSFETs can be set to around 0V, the power supply voltage drop due to the flow of current can be minimized, and the operating speed of these MOSFETs can be increased. It can operate at the same speed as a normal function test.

Further, while the IDDQ test observes the power supply terminal, the function test observes another input terminal, output terminal, or input / output terminal. Therefore, the IDDQ test observes the power supply terminal. However, it is possible to perform the function tests in parallel to determine the theoretical value of the output terminal and the expected output value in parallel and simultaneously.

Next, the second embodiment has exactly the same function as that of the first embodiment. However, as a simple method, the N-channel MOS transistor of the first embodiment is used.
Instead of the FET 4, as shown in FIG. 3, a fixed resistor 8 is inserted after determining the resistance ratio in consideration of the ON resistance of the P-channel MOSFET 3.

Next, the third embodiment has exactly the same function as that of the first embodiment. However, as shown in FIG. 4, a flag register 7 which is a circuit for latching the judgment result is provided. Once connected to the output of inverter 6 and once latched, it maintains its value until reset signal FLG-RST is applied.

That is, if there is even one IDDQ test failure point during the function test, this flag is set, and the IDDQ test failure processing can be performed at an arbitrary timing. The latch clock signal FLG-
CLK is externally applied at an arbitrary timing.

[0032]

As described above in detail, according to the present invention, the power supply current measuring unit, the current-voltage converting unit, the measured value amplifying unit,
With a very simple device configuration called a measurement value judgment unit, a very small IDDQ current can be detected, and a large current generated at the time of transition can flow. Further, even when a large current is generated, the drop of the power supply voltage can be minimized, and the measurement time is very fast.

Since the power supply current measuring device according to the present invention enables the IDDQ test to be performed at high speed, the IDDQ test can be performed at the same time as performing the function test at the frequency at which the function test is performed. It is not necessary to add an IDDQ test specially to the test, the test time does not increase at all, and the IDDQ test can be performed at high quality and at high speed without special preparation of a test pattern.

Further, by using the present invention, it is possible to easily identify an IDDQ test failure.

Further, by using the present invention according to the third or fourth aspect, it is possible to minimize the power supply voltage drop due to the current flow, and to prevent the electric fault given to the CMOS integrated circuit.

Further, by using the present invention described in claim 5.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of a CMOS integrated circuit test apparatus according to the present invention.

FIG. 2 is a diagram showing an IV characteristic of a MOSFET in a CMOS integrated circuit test apparatus according to the present invention.

FIG. 3 is a circuit diagram showing a configuration of a second embodiment of a test apparatus for a CMOS integrated circuit according to the present invention.

FIG. 4 is a circuit diagram showing a configuration of a third embodiment of a CMOS integrated circuit test apparatus according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CMOS integrated circuit 2, 3 P-channel MOSFET 4 N-channel MOSFET 5, 6 Inverter 7 Flag register 8 Resistance

Claims (5)

[Claims] A power supply current detecting means, a current-voltage converting means, a measured value amplifying means, and a measured value judging means for measuring a static power supply current of a CMOS integrated circuit and comparing and judging the measured value with a reference value. In the test apparatus for a CMOS integrated circuit, a first MOSFET whose back gate potential is adjustable is used as the power supply current detecting means, and the first MO is used.
CM, wherein a means for applying a power supply voltage is connected to a source of the SFET, and a power supply terminal of a CMOS integrated circuit is connected to a drain of the first MOSFET.
Test equipment for OS integrated circuits. 2. The power supply current detection means according to claim 1, wherein said current-voltage conversion means has a back gate potential adjustable, and
Second MOSF in which FET and back gate are connected in common
ET and a current limiting circuit connected to the drain of the second MOSFET.
MOSFET and the second MOS of the current-voltage conversion means
A testing device for a CMOS integrated circuit, wherein a FET and a current mirror are connected so that the potential of a gate electrode is common. 3. A first MOSFE of said power supply current detecting means.
3. The testing device for a CMOS integrated circuit according to claim 1, wherein T and the second MOSFET of the current-voltage converter are formed of depletion type transistors. 4. A method for testing a CMOS integrated circuit using the test apparatus for a CMOS integrated circuit according to claim 1, wherein a back gate potential of the first MOSFET is appropriately controlled. A method for testing a CMOS integrated circuit, wherein the threshold potential of the first MOSFET is set to approximately 0V. 5. A method for testing a CMOS integrated circuit using the test apparatus for a CMOS integrated circuit according to claim 2 or 3, wherein the current limiting circuit constituting the current-to-voltage conversion means includes a current limiting circuit. A method for testing a CMOS integrated circuit, wherein a comparison determination reference value is set according to a value.