JP2000068405A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable making into multiple-pin constitution and superior compatibility that can switch types of chips as well as achieve a package of the minimal size, when a memory or a memory logic mixed chip is packaged in a CSP structure. SOLUTION: This device is provided with a semiconductor chip 11, having electrode pads 12, an electrode pad forming surface 11a fastened to the element mounting surface via an adhesive, external terminals (ball bumps 15) for external connection provided on the surface opposite to the element mounting surface and a base substrate 13 with multilayered wiring, on which wiring conductors 16, 17, 18 connected to each external terminal are formed. At a position corresponding to the electrode pad on the semiconductor element side of the substrate, a slit 25 is drilled so that at least one electrode pad is exposed and the wiring conductor and the electrode pad on the chip side are connected by the bonding wire 26 through the slit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a CSP
(Chip Size Package) Structure and BGA
(Ball Grid Array) The present invention relates to a semiconductor device including a semiconductor package having a structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, there has been a remarkable demand for higher integration of semiconductor devices. For example, a 1 GB SDRAM (Dynamic Sync.
Large-capacity memories such as hronous random access memories) are being developed. In manufacturing a semiconductor package using such a semiconductor element (hereinafter, referred to as a semiconductor chip or simply “chip”), it is desired to meet the following requirements.

That is, the above-mentioned 1 GB SDRA
In the case of M, the chip size becomes larger than that of the conventional one, and the number of external terminals increases, so that it is necessary to increase the number of pins. In manufacturing a semiconductor package using such a semiconductor chip, it is necessary to reduce the chip size as much as possible, reduce the size of the package, and reduce the number of external terminals as much as possible.

In a semiconductor package using the above-mentioned chip, it is desired that the electrode pads on the chip side and the external terminals for external connection be connected by a structure as simple as possible. Furthermore, in forming the power supply wiring conductor and the ground wiring conductor in the above-described package, it is also desirable to reduce the wiring resistance as much as possible.

[0005] Therefore, when a semiconductor package is manufactured using the above-described semiconductor chip, a package having the following structure has been proposed assuming that the package size is formed to be substantially the same as the chip size. .

For example, in Japanese Patent Application Laid-Open No. Hei 8-306853, instead of a lead extending outward from a side wall portion of a semiconductor package having a conventional LOC (Lead On Chip) structure, a semiconductor is formed on a flat portion of a lead frame. A semiconductor package having a structure in which a projection bump serving as an external connection terminal is connected to a surface opposite to a chip is disclosed. This conventional semiconductor package is an LO package using a lead frame.
It has a C structure and a CSP structure.

Japanese Patent Application Laid-Open No. 10-107172 discloses a TAB (Tape Automated B) instead of a metal lead.
onding) TAB connection to the center pad using tape,
A semiconductor package having a LOC structure and a CSP structure in which bumps are connected to external connection terminals is disclosed.

[0008]

However, in the above-mentioned conventional semiconductor device, the former Japanese Patent Application Laid-Open No. Hei 8-306853 has been disclosed.
Since the semiconductor package described in the above publication has a LOC structure and a CSP structure, as the number of pins increases, the number of wirings that can pass the pitch between external terminals is restricted.
Practically, the number of external terminal rows with respect to the electrode pads is limited to two rows.

Further, the conventional semiconductor package described in the latter Japanese Patent Application Laid-Open No. 10-107172 has a TAB connection structure, so that its wiring board must be formed in accordance with each product type and lacks compatibility. , Resulting in high costs. In such a connection structure using a TAB tape, a tensile stress is generated at the connection portion, and it is difficult to improve the reliability of the entire device.

In particular, such a TAB tape has flexibility and a coefficient of thermal expansion which is significantly different from that of a chip.
There is a possibility that a tensile stress is generated due to a temperature change and a lead connection portion may be detached, which is a problem in securing reliability. Further, the wiring distance from the electrode pads of the semiconductor chip to the external terminals is long, the wiring resistance is increased, and the inductance is increased.

The present invention has been made in view of such circumstances, and when packaging a memory or a memory-logic mixed chip by a CSP structure, it is possible to increase the number of pins and to switch types to achieve compatibility. It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, which can obtain an excellent structure and can minimize a package.

[0012]

According to a first aspect of the present invention, there is provided a semiconductor device in which electrode pads are formed on one side surface in a predetermined arrangement pattern, and The electrode pad forming surface is fixed to the element mounting surface via an adhesive, and external terminals (for example, ball bumps) for external connection are provided in a predetermined arrangement pattern on a surface opposite to the element mounting surface. A slit having a size such that at least one of the electrode pads is exposed at a position corresponding to each electrode pad on the semiconductor element side of the base substrate, the wiring substrate being provided with a wiring conductor connected to a terminal; And the wiring conductor and the electrode pad on the semiconductor element side are electrically connected by wire bonding through the slit.

According to a second aspect of the present invention, in the semiconductor device, the connection land portion of the external terminal and the slit are formed close to each other on a surface of the base substrate on which the external terminal is provided. Features.

According to a third aspect of the present invention, in the semiconductor device, a center pad portion is formed by arranging an electrode pad at a center in a width direction of an electrode pad forming surface of the semiconductor element, and the center pad portion is formed on the base substrate. A center slit larger than that is formed at a corresponding position, and wiring is performed so that a part of the wiring conductor faces a side edge portion of the center slit.

A semiconductor device according to a fourth aspect of the present invention is characterized in that a power supply wiring conductor and a ground wiring conductor are formed separately on the element mounting surface of the base substrate.

A semiconductor device according to a fifth aspect of the present invention includes a base substrate provided with a center slit corresponding to a center pad portion of the semiconductor element, wherein the power supply wiring conductor and the ground wiring conductor are connected to the base substrate. The element mounting surface of the substrate is formed separately on both sides of the center slit.

In a semiconductor device according to a sixth aspect of the present invention, a wiring circuit using the signal wiring conductor is formed on at least one of an element mounting surface of the base substrate and a terminal arrangement surface on which external terminals are provided. It is characterized by the following.

The semiconductor device according to claim 7, wherein a multilayer circuit board is used as the base substrate, and a wiring circuit formed by the signal wiring conductor is formed by forming the power supply wiring conductor and the ground wiring conductor. It is characterized in that it is formed on a surface other than the mounting surface and the terminal arrangement surface on which the external terminals are provided.

In a semiconductor device according to an eighth aspect of the present invention, a ground wiring conductor is provided on the element mounting surface of the base substrate, the portion being opposed to the signal external terminal and the wiring conductor, and the ground terminal and the wiring conductor. A power supply wiring conductor is formed by laminating a power supply wiring conductor on a portion facing the power supply external terminal and the wiring conductor with an insulating layer interposed therebetween.

In a semiconductor device according to a ninth aspect of the present invention, the base substrate is formed of a resin substrate made of, for example, a glass epoxy resin, a ceramic substrate made of, for example, alumina, or a film substrate made of, for example, a polyimide resin. It is characterized by having done.

According to a tenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a semiconductor element having electrode pads formed on one side surface in a predetermined arrangement pattern; and an element mounting surface for mounting the electrode pad forming surface of the semiconductor element. An external terminal (for example, a ball bump) for external connection is provided in a predetermined arrangement pattern on the opposite surface, and a base substrate on which a wiring conductor connected to each external terminal is formed is prepared. The pad forming surface is mounted and fixed on the element mounting surface of the base substrate with an adhesive, and the wiring conductor formed on the surface opposite to the element mounting surface of the base substrate and the electrode pad on the semiconductor element side are formed as described above. At least one of the electrode pads is exposed at a position corresponding to each of the electrode pads on the semiconductor element side of the base substrate through a slit. Electrically connecting by wire bonding, providing external terminals for external connection on a surface opposite to the element mounting surface of the base substrate, and then sealing the wire-bonded slit portion of the base substrate with a resin. Features.

According to the present invention (the first aspect of the present invention), a slit formed in the base substrate corresponding to the electrode pad on the chip side and a wire bonding connection utilizing the slit are used to connect the chip to the substrate side. This allows free wiring connection to the ball bumps. In particular, according to the present invention (the invention described in claim 2), the shortest distance is obtained by bringing the land portion on which the external terminal of the base substrate is provided and the slit close to each other, and the wiring conductor on the base substrate side has the minimum length. , And the inductance can be reduced, and the electrical characteristics can be improved. In addition,
The size of the slit may be set to be slightly larger than the size of the corresponding electrode pad.

Further, according to the present invention (the first and third aspects of the present invention), since wire bonding connection is used, when a plurality of electrode pads on the chip side are made to correspond within the same slit, the adjacent Not only between the electrode pads to be connected, but also between the electrode pads that are not adjacent to each other can be freely performed.

According to the present invention (the first, second, third, and ninth aspects of the invention), a printed circuit board is used as a base substrate, and electrode pads on a chip side are formed by wire bonding. Is connected to

According to the present invention (the fourth aspect of the present invention), the wiring conductors serving as the power supply wiring and the grounding wiring can be formed in a wide area and a wide wiring width by effectively utilizing the element mounting surface of the base substrate. Can be formed. In particular, according to the present invention (the inventions described in claims 4 and 5), a reduction in resistance and an improvement in electrical characteristics can be achieved.

Further, according to the present invention (claims 6, 7 and 8), in the base board, the signal external terminal and its wiring conductor, and the ground terminal and its ground conductor are opposed to each other. In addition to forming the wiring conductor to be the ground wiring, and forming the power supply terminal and the wiring conductor to be the power supply wiring facing the wiring conductor, the wiring resistance is reduced and the impedance is matched. And prevent the effects of noise.

In particular, according to the present invention (claims 4 and 5), the wiring conductors serving as the power supply wiring and the ground wiring are separated from each other at a long distance from each other with a slight insulation distance. Since they are in contact with each other, the capacitance between them is large and external power supply noise can be absorbed. According to the present invention (claims 6, 7, and 8), a chip capacitor conventionally provided for absorbing noise on a circuit using a semiconductor package becomes unnecessary.

The present invention (the invention according to claim 10)
According to the above, when packaging a memory or a memory-logic mixed chip in a CSP structure as described above, it is possible to increase the number of pins and to switch the product type.

Further, the present invention (the invention according to claim 1)
According to this, it is possible to switch to another product using one printed circuit board. Further, since the wire bonding connection is used, no stress is generated at the chip connecting portion.

The base substrate is any one of a resin substrate made of glass epoxy resin, for example, a ceramic substrate made of alumina or the like, and a film substrate made of polyimide resin or the like, for example, two layers, three layers or more layers. A printed circuit board is preferably used. The external terminals provided on the base substrate for external connection are, for example, ball bumps.

The slit formed in the base substrate is
With a size corresponding to each electrode pad on the chip side,
Alternatively, any one having a size corresponding to a plurality of electrode pads may be used.

[0032]

1 to 3 show a first embodiment of a semiconductor device and a method of manufacturing the same according to the present invention. 1 is a semiconductor device (hereinafter, referred to as a semiconductor package). The semiconductor package 10 includes a flat semiconductor chip 11 having a rectangular shape in plan view, as shown in FIG. Prepare. The semiconductor chip 11 is to be a large-capacity memory such as a 1 GB SDRAM, and the degree of integration is increasing. The basic structure of the semiconductor chip 11 is widely known. Specific description is omitted.

On one side surface of the semiconductor chip 11, a number of electrode pads 12 for external connection are formed in a predetermined arrangement pattern. In this embodiment, the chip 1
The electrode pads 12 are arranged in a matrix on one side surface (hereinafter, referred to as an electrode pad formation surface 11a). In FIG. 1, reference numeral 12a denotes an insulating film formed on the electrode pad forming surface 11a of the semiconductor chip 11 except for the electrode pads 12.

The semiconductor chip 11 is bonded and fixed via an adhesive 14 to a chip mounting surface (element mounting surface) 13a of a base substrate 13 having a size substantially equal to the chip size. Further, ball bumps 15 are arranged on a surface of the base substrate 13 opposite to the chip mounting surface 13a (hereinafter, referred to as a terminal mounting surface 13b) as external terminals for external connection in a predetermined arrangement pattern (terminal arrangement in this embodiment). It is provided in a matrix on the installation surface 13b.

Further, wiring conductors 16, 17, 18 connected to the respective ball bumps 15 are provided on the base substrate 13.
Are formed. These wiring conductors include a signal wiring conductor 16, a power supply wiring conductor 17, and a ground power supply conductor 18. Terminal mounting surface 13 of the base substrate 13
b is a connection land portion 1 connected to the wiring conductors 16, 17, 18 and to which the ball bumps 15 are connected.
9, 20, 21 are formed. In the figure, the land portions 19, 20, and 21 connected to the signal wiring conductor 16, the power supply wiring conductor 17, and the ground power supply conductor 18 have "S", respectively.
“Vdd” and “GND” are added.

According to the present invention, at a position corresponding to each electrode pad 12 on the semiconductor chip 11 side of the base substrate 13, a size slightly larger than the pad 11 is set so that at least one of the electrode pads 11 is exposed. Slit 2
5 are drilled. And each of these slits 25
The wiring conductors 16, 17, 18 and the electrode pads 12 on the semiconductor chip 11 side are bonded through bonding wires 26.
Is characterized by wire bonding connection.

In this embodiment, the terminal mounting surface 13b of the base substrate 13 provided with the ball bumps 15 is provided.
The connection land portions 19 and 2 of the ball bump 15
0, 21 and the slit 25 are formed as close as possible.

In the drawing, reference numerals 16a, 17a, and 18a denote wiring conductors 1 on the terminal mounting surface 13b of the base substrate 13.
6, 17 and 18, and these conductors 16a, 17a and 18a are formed facing the edge of the slit 25 and connected by wire bonding. Also, in FIG.
It is a sealing resin that is sealed inside or at a portion of the terminal arrangement surface 13 b of the base substrate 13 except for the ball bumps 15.

In FIGS. 3A and 3B, reference numeral 21 denotes
Reference numerals a and 20a denote through holes for connecting the connection lands 21 and 20 with the power supply wiring conductor 18 and the ground wiring conductor 17 formed on the element mounting surface 13a of the base substrate 13. Here, the above-described power supply wiring conductor 1
7 and the ground wiring conductor 18 are formed in a thin film shape (a so-called solid layer) on the element mounting surface 13a of the base substrate 13 by dividing the respective regions. By doing so, the wiring resistance of these wiring conductors 17 and 18 can be reduced. Note that an insulating protective film is formed on the surfaces of the wiring conductors 17 and 18 in consideration of the material of the insulating material 14 and the like. The chip 11 is mounted on the surface of the insulating protective film via the adhesive 14.

Further, the slits 25 formed in the base substrate 13 corresponding to the electrode pads 12 on the chip 11 side and the wire bonding connection using the slits 25 are used to connect the ball bumps 15 from the chip 11 to the substrate 13 side. Can be freely connected. In particular, when the land portions 19, 20, 21 on which the ball bumps 15 of the base substrate 13 are provided and the slits 25 approach each other, the distance becomes the shortest, and the signal wiring conductor 16 on the base substrate 13 is wired with the shortest length. It is possible to reduce the inductance and improve the electrical characteristics.

In the above-described first embodiment, the slits 25 are provided close to the respective ball bumps 15, so that the signal wiring conductors 16 are particularly formed with the minimum necessary wiring length. Can be formed. here,
Although a detailed illustration is omitted, if there is a portion other than the conductor portion 16 a of the signal wiring conductor 16, this portion is placed on the chip mounting surface 13 a side of the substrate 13, for example.
7. It may be formed via a ground wiring conductor 18 and an insulating layer. However, the present invention is not limited to this, and a wiring circuit may be formed on the terminal arrangement surface 13b on which the ball bumps 15 are provided.

FIGS. 4 and 5 show a second embodiment of the present invention. The above-mentioned signal wiring conductor 16, power supply wiring conductor 17, and ground wiring conductor are provided on the terminal arrangement surface 13b of the base substrate 13. 18 is shown. It goes without saying that an insulating layer (not shown) is interposed at an appropriate position.

Here, in the above-described first and second embodiments, the base substrate 13 is formed of a two-layer wiring circuit board made of a ceramic substrate made of, for example, alumina. However, the present invention is not limited to this, and may be any of a resin substrate made of, for example, a glass epoxy resin, and a film substrate made of, for example, a polyimide resin.

FIG. 6 shows a third embodiment of the present invention.
Here, a printed circuit board having a three-layer structure composed of two boards is used as the base board 13. In this embodiment, the wiring circuit formed by the signal wiring conductors 16 is replaced by a wiring circuit other than the power supply wiring conductor 17, the element mounting surface 13 a on which the ground wiring conductor 18 is formed, and the terminal mounting surface 13 b on which the ball bumps 15 are provided. It is formed in the middle layer.

A conductor portion 16a is provided for the signal wiring conductor 16 formed in the intermediate layer portion, and the step portion of the substrate 13 provided with the conductor portion 16a and the electrode pad 12 on the chip 11 side are connected by wires. Bonding connection. In the figure, reference numeral 19a denotes the wiring conductor 16 and the ball bump 1
5 is a through-hole for connecting to No. 5.

In the chip mounting surface 13a of the base substrate 13, the signal ball bumps 15 and the wiring conductors 16, and the ground terminals (by the ball bumps 15) and the portions facing the wiring conductors (21a) are connected to the ground. The power supply wiring conductor 17 is formed in a portion of the wiring conductor 18 facing the power supply external terminal (by the ball bump 15) and the wiring conductor (20a). In FIG. 4, reference numeral 22 denotes an insulating layer formed between the wiring conductors 17 and 18 and the land portion 19. Further, an insulating protective film is formed on the surfaces of the wiring conductors 17 and 18 as in the above-described embodiment.

That is, the power supply wiring conductor 17 and the ground wiring conductor 18 are formed on the chip mounting surface 13 a of the base substrate 13, and an insulating layer such as an alumina coat layer is formed. The chip 11 is mounted. By using such a printed circuit board, a multilayer structure can be adopted and a plurality of board surfaces can be used.
It becomes easy to form a wiring circuit pattern.

Semiconductor package 10 having the above configuration
Is manufactured as follows. That is, the electrode pad 12
And a chip mounting surface 13a on which the electrode pad forming surface 11a of the semiconductor chip 11 is mounted.
Ball bump 1 for external connection on the surface (13b) opposite to
5 and wiring conductors 16, 17, 18, 19, 20, 21 connected to these ball bumps 15.
A base substrate 13 on which a chip 11 is formed is prepared.
The electrode pad forming surface 11a is mounted and fixed on the chip mounting surface 13a of the base substrate 13 with an adhesive 14.

The element mounting 1 of the base substrate 13
Wiring conductors 19 and 2 formed on surface 13b opposite to surface 3a
0, 21 and the electrode pads 12 on the chip 11 side are electrically connected by wire bonding through the slits 26 of the base substrate 13, and the land portions 19, 20, 21 on the terminal arrangement surface 13 b side of the base substrate 13. Except for the above, after the connection portion by wire bonding, the slit 26 and the like are sealed with a resin, a ball bump 15 for external connection is provided on the lands 19, 20 and 21.

FIGS. 7 and 8 (a), 8 (b) and 8 (c) show a fourth embodiment of a semiconductor device and a method of manufacturing the same according to the present invention.
A case 1 is a center pad type, in which a semiconductor chip 11 is mounted on a base substrate 13 provided with a center slit 32 for bonding corresponding to the center pad section 31 by bonding with an adhesive 14.

On the electrode pad forming surface 11a, which is the active surface of the semiconductor chip 11, a large number of electrode pads 12 are arranged in the center pad portion 31 in two rows. The circuit wiring in the chip 11 is appropriately wired to each electrode pad 12 in the center pad section 31 as shown in FIG. In the slit 32 of the base substrate 13, an electrode pad 33 on the substrate 13 side is arranged at a peripheral portion of a step formed in the intermediate layer.

According to the present invention, the aforementioned semiconductor chip 1
After the substrate 1 is mounted on the base substrate 13 via the adhesive 14, the electrode pads 33 and 12 of the substrate 13 and the chip 11 are connected by wire bonding with the bonding wires 26 at the center slit 32. . It is needless to say that the above-described wire bonding connection portion by the center slit 32 is sealed with a resin, though not shown. This is performed in order to ensure the reliability of the connection portion by the bonding wire 26 at the above-described center slit 32 and to prevent moisture from entering.

Thus, the semiconductor package 10 having a size equal to or slightly larger than the chip size can be obtained. In addition, as described above, by using a rigid substrate such as a glass epoxy substrate or a ceramic substrate as described above, the reliability of the semiconductor package 10 can be improved. In particular, chip 1
1 and the base substrate 13, the connection between any of the electrode pads 12, 33 can be performed relatively easily and reliably, and the degree of freedom in connection with each wiring circuit is large. In addition, efficient wiring is possible, and the manufacturing cost can be reduced.

In such a wire bonding connection, the connection between the electrode pads 12 at the center pad portion 31 is also possible. By using such a wire bonding connection in the chip 11, the chip bonding can be performed. There is also an advantage that the wiring circuit structure in 11 can be simplified.

As shown in FIG. 8 (c), a multilayer wiring circuit board is used as the base board 13, and the power supply and ground wiring conductors 1 are mounted on the chip mounting surface 13a of the board 13 as shown in FIG.
7, 18 (Vdd layer, GND layer) are formed. In this embodiment, the power supply wiring conductor 17 is provided on one side of the center slit 32 on the chip mounting surface 13 a of the substrate 13.
A ground wiring conductor 18 is formed on the other side.

In such a structure, the power supply wiring conductor 17
The ground wiring conductor 18 can be formed in a wide area on the substrate, and the wiring resistance can be greatly reduced, and the electrical characteristics can be improved. That is, by forming these wiring conductors 17 and 18 with a large area, resistance and inductance can be suppressed low. In addition, such a wiring conductor 17,
The formation of 18 can be performed relatively easily by a so-called solid layer, and the manufacturing cost can be reduced.

In forming these power supply wiring conductors 17 and ground wiring conductors 18 on the same substrate surface of the base substrate 13, the left and right divisions are made based on the center slit 32 as described above. Not limited to FIG.
The wiring conductors 17 and 18 described above may be formed in a region where the wiring resistance can be reduced as shown in FIG.

In the wiring conductor as described above,
If the ground wiring conductor 18 is formed at a position corresponding to the wiring circuit of the signal wiring 16 formed on the other substrate surface of the base substrate 13, it is possible to prevent the influence of noise and improve the electrical characteristics.

Further, according to the semiconductor package 10 having such a structure, even when the semiconductor chips 11 having different sizes and types are used, the base substrate 13 and the like can be used in common, and the versatility and compatibility are improved. And the package 10 can be standardized.

The main surface of the base substrate 13 is provided with an appropriate arrangement pattern, for example,
9, 20, 21 are provided, and respective land portions 19,
Ball bumps 15 for external connection are provided as external terminals for 20, 21. Needless to say, these ball bumps 15 are connected to the electrode pads 33 via circuit wiring wired on the base substrate 13 and are connected to the chip 11 by wire bonding.

Here, as described above, if the wiring circuit board is used as the base board 13 and the connection with the chip 11 is made by wire bonding using the slit 32 formed in the base board 13, The problem that the number of leads (the number of wirings) that can pass between the bumps 15 and 15 is limited as in the structure is eliminated, and the circuit wiring on the substrate 13 can be freely performed. Therefore, the number of pins of the semiconductor chip 11 can be increased. In particular, such an advantage becomes even more advantageous when the above-described base substrate 13 is formed of a multilayer wiring circuit board.

Further, as described above, the power supply wiring conductor 17 and the ground wiring conductor 17 are formed by dividing the base substrate 13 into appropriate regions, and the signal wiring conductor 16 is formed on another substrate surface. Then, the power supply wiring (power supply wiring conductor 17, ground wiring conductor 18, and signal wiring conductor 16) conventionally required in two or more layers can be efficiently composed of at least two layers, and the number of boards can be reduced. There is an advantage that you can.

According to the above configuration, since the connection between the center pad portion 31 of the chip 11 and the base substrate 13 is connected by wire bonding, the connection strength can be secured and the reliability of the connection portion can be improved. Can be. Also,
Since the chip 11 is mounted on the base substrate 13 made of a rigid substrate, the thermal expansion coefficients and the like of the two are made uniform, and the above-described wire bonding connection portion of the pad 12 does not come off due to a difference in thermal expansion or the like. For example, TA
Since the coefficient of thermal expansion with the chip is large in the B tape, there is an advantage as compared with the fact that the connection portion is easily detached by the stress.

The present invention is not limited to the structure described in the above embodiment, and it goes without saying that the shape and structure of each part can be appropriately modified and changed. For example, as a semiconductor device (semiconductor package 10), for example, 1G
Although the case of a memory such as a byte SDRAM has been exemplified, the present invention is not limited to this, and can be applied to various semiconductor devices as well as a semiconductor device in which a memory and a logic are mixed.

Further, in the semiconductor device according to the present invention,
The case where a two-layer or three-layer multilayer wiring circuit board is used as the base board 13 has been exemplified, but the present invention is not limited to this. Furthermore, although the ceramic substrate has been illustrated, the invention is not limited thereto, and may be any of a resin substrate made of, for example, a glass epoxy resin, and a film substrate made of, for example, a polyimide resin.

[0066]

As described above, according to the semiconductor device and the method of manufacturing the same according to the present invention, in packaging a memory or a memory-logic mixed chip by a CSP structure, it is possible to increase the number of pins and to switch types. A possible structure can be obtained, and minimization of the package can be realized.

That is, according to the present invention, a slit formed in the base substrate in correspondence with the electrode pad on the chip side,
Free wire connection from the chip to the ball bump on the substrate side is possible by wire bonding connection utilizing this. In particular, the distance between the land on which the external terminals of the base substrate are provided and the slit are made closer to each other, so that the shortest distance can be obtained. Can be improved. Note that the size of the slit is preferably set to be slightly larger than the size of the corresponding electrode pad.

Further, according to the present invention, since a plurality of electrode pads on the chip side are made to correspond to each other in the same slit because of wire bonding connection, not only between adjacent electrode pads but also between non-adjacent electrode pads. Connections can be made freely. Therefore, it is possible to meet various demands such as a change in the wiring circuit on the chip side, a change in the arrangement of external terminals on the base substrate side, and a change in the wiring circuit of the wiring conductor.

Further, according to the present invention, the printed circuit board is used as the base substrate, and the connection with the electrode pads on the chip side is made by wire bonding. In comparison with the case where the semiconductor device is used as a connection means to the electrode pad, high-density wiring is possible, and it is possible to meet a demand for a multi-pin semiconductor package.

According to the present invention, the wiring conductors serving as the power supply wiring and the ground wiring are formed so as to increase the formation area and the wiring width by effectively utilizing the element mounting surface of the base substrate. Each wiring resistance is reduced, and the resistance can be reduced. In particular, the wiring conductors serving as the power supply wiring and the ground wiring are formed on the element mounting surface of the base substrate so as to be divided into regions and have the same potential.
As well as lowering the resistance, the electrical characteristics can be improved.

Further, on the base board, a signal external terminal and its wiring conductor, a ground terminal and a wiring conductor serving as a ground wiring facing the wiring terminal, and a power supply terminal and the wiring conductor facing the wiring conductor are formed. Since the wiring conductor serving as the power supply wiring is formed, it is possible to lower the resistance of each wiring and to match the impedance, thereby preventing the influence of noise and improving the characteristics.

Further, according to the present invention, the wiring conductors serving as the power supply wiring and the ground wiring are configured to be in contact with each other over a long distance with a slight insulation distance therebetween. There is an advantage that the capacitance is increased and external power supply noise can be absorbed. According to such a configuration, there is an advantage that a chip capacitor conventionally provided for absorbing noise on a circuit using a semiconductor package becomes unnecessary.

Further, according to the present invention, when packaging a memory or a memory-logic mixed chip in a CSP structure as described above, it is possible to increase the number of pins, switch types, and have excellent compatibility. Can be easily manufactured with a minimum required configuration.

Further, according to the present invention, since the electrode pads on the chip side are connected to the external terminals provided on the base substrate by wire bonding, switching to another type using one wiring circuit board is performed. Becomes possible. Further, according to such a wire bonding connection, the configuration can be made such that the stress of the chip connection portion is not applied, so that the reliability of the package is improved.

Further, according to the present invention, it is not necessary to pass a wiring between the external terminal pitches, so that mutual interference (crosstalk) between the wiring conductor and the external terminal does not occur. Further, for example, when the base substrate is formed of a multilayer wiring circuit board and the signal wiring conductor is formed in the intermediate layer, some crosstalk occurs, but there is no problem as the wiring is densely arranged as in the related art.

According to the present invention, when a specific wiring length is set, the impedance is set to 50Ω or 75Ω by providing a ground wiring conductor and defining the thickness and dielectric constant of the insulating layer with respect to the wiring width. be able to. Therefore, by matching the impedance, the reflection of the signal output from the semiconductor chip does not occur in the wiring, and the signal can be transmitted 100% to the printed wiring board side.

In particular, when the memory-logic mixed chip is connected to CS
In order to realize a P structure, it is necessary to increase the number of pins, and the number of external terminals is dramatically increased as compared with the current memory alone. In such a case, the pads are generally distributed more uniformly over the entire chip than in the center pad system of the memory. In the present invention, the signal can be transferred from the electrode pad of the chip to the base substrate in the shortest distance, so that the influence of an increase in resistance and crosstalk can be minimized.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a main part and an enlarged view of the main part showing a first embodiment of a semiconductor device and a method of manufacturing the same according to the present invention.

2A is a schematic plan view of the semiconductor device of FIG. 1 as viewed from a side where ball bumps are provided, and FIG. 2B is an enlarged view of a main part thereof.

FIGS. 3A and 3B are plan views of a semiconductor device shown in FIGS. 1 and 2 in which a terminal mounting surface of a base substrate is viewed, FIG. 3B is a plan view of a chip mounting surface, and FIG. FIG. 4 is a plan view of the electrode bump formation surface of FIG.

FIG. 4 is a sectional view of a main part and an enlarged view of the main part showing a second embodiment of the semiconductor device and the method of manufacturing the same according to the present invention.

FIG. 5 is a plan view showing a terminal arrangement surface of a base substrate for explaining the semiconductor device of FIG. 4;

FIG. 6 is a sectional view of a main part and an enlarged view of the main part showing a third embodiment of a semiconductor device and a method of manufacturing the same according to the present invention.

FIG. 7 is a perspective view, in section, of a main part showing a fourth embodiment of a semiconductor device and a method for manufacturing the same according to the present invention.

8A is a plan view of the semiconductor device of FIG. 7 viewed from the side where ball bumps are provided, FIG. 8B is a diagram for explaining a state of forming a wiring conductor in a base substrate, and FIG. FIG. 4 is a diagram showing a shape of a wiring conductor on a chip mounting surface of a base substrate.

FIG. 9 is a schematic diagram showing a modification of the shapes of the power supply wiring conductor and the ground wiring conductor in FIG. 8C.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Semiconductor package as a semiconductor device, 11 ... Semiconductor chip (semiconductor element), 11a ... Electrode bump formation surface, 12 ... Electrode bump, 12a ... Insulation film, 13 ... Base substrate, 13a ... Chip mounting surface (Element mounting surface) , 13b ...
Terminal arrangement surface, 14: adhesive, 15: ball bump (external terminal), 16: signal wiring conductor, 17: power supply wiring conductor, 18: ground wiring conductor, 16a, 17a, 18
a: conductor part, 19, 20, 21 ... connection land part, 22
... insulating layer, 25 ... slit, 26 ... bonding wire, 28 ... sealing resin, 31 ... center pad part, 32 ... center slit, 33 ... substrate side electrode pad part.

Claims (10)

[Claims] 1. A semiconductor element having electrode pads formed on one side surface thereof in a predetermined arrangement pattern, and an electrode pad forming surface of the semiconductor element is fixed to an element mounting surface via an adhesive, and the side opposite to the element mounting surface. A base substrate on which external terminals for external connection are provided in a predetermined arrangement pattern and a wiring conductor connected to each of the external terminals is formed, and each electrode pad on the semiconductor element side of the base substrate A slit having a size such that at least one of the electrode pads is exposed, and electrically connecting the wiring conductor and the electrode pad on the semiconductor element side through the slit by wire bonding. A semiconductor device characterized by the following. 2. The semiconductor device according to claim 1, wherein a connection land portion of the external terminal and the slit are formed close to a terminal arrangement surface of the base substrate on which the external terminal is provided. Characteristic semiconductor device. 3. The semiconductor device according to claim 1, wherein a center pad portion is formed by arranging an electrode pad at a center in a width direction of an electrode pad formation surface of the semiconductor element, wherein the center pad portion is formed on the base substrate. A semiconductor device, wherein a larger center slit is formed at a corresponding position, and wiring is performed so that a part of the wiring conductor faces a side edge portion of the center slit. 4. The semiconductor device according to claim 1, wherein a power supply wiring conductor and a ground wiring conductor are formed on the element mounting surface of the base substrate, respectively, in different regions. A semiconductor device characterized by the above-mentioned. 5. The semiconductor device according to claim 4, wherein the base substrate has a center slit corresponding to a center pad portion of the semiconductor element, and the power supply wiring conductor and the ground wiring conductor are connected to the base by the base. A semiconductor device, which is formed on an element mounting surface of a substrate on both sides of the center slit. 6. The semiconductor device according to claim 4, wherein the wiring circuit formed by the signal wiring conductor is at least one of an element mounting surface of the base substrate and a terminal arrangement surface provided with external terminals. A semiconductor device formed on one side. 7. The semiconductor device according to claim 4, wherein a multilayer wiring circuit board is used as the base substrate, and a wiring circuit formed by the signal wiring conductor is replaced with the power supply wiring conductor and the ground wiring conductor. A semiconductor device formed on a surface other than the element mounting surface on which is formed and the terminal arrangement surface on which the external terminals are provided. 8. The semiconductor device according to claim 4, 5, 6, or 7, wherein the signal external terminal and the wiring conductor, and the ground terminal and the wiring are on the element mounting surface of the base substrate. A semiconductor device comprising: a ground wiring conductor formed at a portion facing a conductor; and a power wiring conductor formed at a portion facing the power supply external terminal and the wiring conductor, with an insulating layer interposed therebetween. 9. The semiconductor device according to claim 1, 2, 3, 4, 5, 6, 7, or 8, wherein the base substrate is a resin substrate. A semiconductor device comprising a ceramic substrate or a film substrate. 10. A semiconductor element having electrode pads formed on one side surface in a predetermined arrangement pattern, and external terminals for external connection on a surface opposite to an element mounting surface on which the electrode pad forming surface of the semiconductor element is mounted. Prepare a base substrate provided with the arrangement pattern of and the wiring conductors connected to these external terminals are formed, and the electrode pad forming surface of the semiconductor element is mounted on the element mounting surface of the base substrate with an adhesive. The wiring conductor and the electrode pad on the semiconductor element side formed on the surface of the base substrate opposite to the element mounting surface are fixed at least at positions corresponding to the respective electrode pads on the semiconductor element side of the base substrate. Electrically connected by wire bonding through a slit drilled in such a size that one of the electrode pads is exposed, and mounting the element on the base substrate And the external terminals for external connection on the opposite side is provided, a method of manufacturing a semiconductor device of the slit portion of wire bonding connections Thereafter the base substrate, characterized in that the resin sealing.