JP2000012868A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) Abstract: An object of the present invention is to provide a semiconductor device capable of reducing the chip size and increasing the operation speed by reducing the junction capacitance of a diffusion layer, and a method for manufacturing the same. In a MOS type field effect transistor using an SOI substrate, contact holes are provided.
2 is formed over the source / drain diffusion layers 10 and 11 over the adjacent element isolation oxide film 7 to a depth reaching the silicon substrate 1, and impurities are ion-implanted in the exposed surface region of the silicon substrate. It is characterized in that a PN junction is formed by implantation. Since the silicon substrate and the source / drain diffusion layers of the same conductivity type as this substrate can be electrically separated by the PN junction, the silicon substrate and the source / drain diffusion layers are separated via the metal wiring layers 14-1 and 14-2. Can be prevented from being short-circuited. As a result, the chip size can be reduced, the junction capacitance of the source / drain diffusion layers can be reduced, and the operation speed can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to an MO device formed on an SOI substrate.
The present invention relates to a structure of an S-type field effect transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, device technologies for speeding up an LSI and operating with low power consumption have been actively developed. Above all, MOS field-effect transistors using an SOI substrate can achieve a higher operating speed and a drastic reduction in power consumption during operation by drastically reducing the parasitic capacitance and improving the S factor. It is greatly expected as a basic device.

A conventional structure for forming a MOS field effect transistor on such an SOI substrate and a method for manufacturing the same will be sequentially described with reference to FIGS. First, as shown in FIG. 19, an SO including a P-type silicon substrate (semiconductor substrate) 101, a buried oxide film (insulating layer) 102 having a thickness of about 1500 Å, and a silicon active layer 103 having a thickness of about 1500 Å.
After an oxide film 104 having a thickness of about 200 Å is formed on the I-substrate 100 by thermal oxidation, an LPCV
A polysilicon layer 105 having a thickness of 3500 angstroms and an oxide film 106 having a thickness of about 3000 angstroms are deposited and formed by the method D.

Next, as shown in FIG. 20, a resist pattern 120 is formed by lithography, RIE is performed using the resist pattern 120 as a mask, and an oxide film 106 and a polysilicon layer in a region where an element isolation region is to be formed are formed. 105 is removed.

Thereafter, as shown in FIG. 21, after the resist pattern 120 is removed, the oxide film 104 and the silicon active layer 103 are removed by RIE using the oxide film 106 as a mask.
To remove selectively.

[0006] Subsequently, as shown in FIG.
Using method D, an oxide film 107 having a thickness of about 2000 Å is deposited and formed on the entire surface. Further, the polysilicon layer 105 is planarized by using the polysilicon layer 105 as a stopper by using the etch back by RIE or the CMP method to expose the polysilicon layer 105 on the element region. Thereafter, a CDE process is performed to completely remove the polysilicon layer 105 as shown in FIG. 23, thereby exposing the oxide film 104 on the element region.

Then, as shown in FIG. 24, a resist pattern 121 is formed by lithography so as to cover a region where a PMOS (P-channel MOS) transistor is to be formed.
Is formed, and a P-type impurity is ion-implanted into a region where an NMOS (N-channel type MOS) transistor is to be formed to form a channel region.

Similarly, as shown in FIG. 25, a resist pattern 122 is formed by lithography so as to cover a region where an NMOS transistor is to be formed, and an N-type impurity is ion-implanted into a region where a PMOS transistor is to be formed. To form

Next, after the oxide film 104 on the surface is removed by HF wet etching, as shown in FIG. 26, a gate oxide having a thickness of about 100 Å is formed on the surface of the silicon active layer 103 by thermal oxidation. A film 108 is formed. Further, on the oxide film 107 and the gate oxide film 108, an N-type impurity-doped thickness 2500
After depositing about angstrom of polysilicon, patterning is performed by RIE using lithography,
A gate electrode 109 is formed.

Next, the source / drain diffusion layers 110, 110 of the NMOS transistor are formed by ion-implanting N-type impurities by masking the region where the PMOS transistor is to be formed by using lithography. The PMO is ion-implanted by masking a region where a transistor is to be formed, so that a PMO
Source / drain diffusion layers 111 and 11 of S transistor
1 (see FIG. 27).

Subsequently, as shown in FIG. 28, an oxide film is deposited on the entire surface as an interlayer insulating film 112 by LPCVD to a thickness of 5000 angstroms, and then the source / drain diffusion of the PMOS transistor and NMOS transistor is performed by RIE. Layers 110, 110, 111, 11
Are formed on the first contact hole 113. Here, the contact holes 113, 113,.
The margins Δd, Δd,... Of the end portions of the drain diffusion layers 110, 110, 111, 111 are normally maintained at about 0.2 to 0.5 μm. Thereafter, metal wiring layers 114, 114,... Of Al, W, etc. are formed as source / drain electrodes to complete the device.

By the way, a MOS formed on a silicon substrate
In the field effect transistor, the margins Δd, Δd,.
0 or less, that is, the contact hole is formed from the end of the source / drain diffusion layer to the element isolation oxide film, thereby reducing the chip size and the junction capacitance of the source / drain diffusion layer. .

However, in the MOS type field effect transistor using the SOI substrate 100 as described above, the contact holes 113, 113,... Are formed over the source / drain diffusion layers 110, 111 over the element isolation oxide film 107. In this case, since the controllability of the RIE etching depth is not sufficient, there is a possibility that the buried oxide film 102 as a lower layer may be etched through the element isolation oxide film 107. In such a state, the silicon substrate 1
01 and the source / drain diffusion layers 110, 110 or 111, 111 of the same conductivity type as the substrate 101 are short-circuited via the metal wirings 114, 114,...

[0014]

As described above, in the conventional semiconductor device using the SOI substrate and the method of manufacturing the same, when a contact hole is formed from the source / drain diffusion layer to the element isolation oxide film, There is a possibility that the buried oxide film may be etched together with the element isolation oxide film by RIE at the time of forming the contact hole, and there is a problem that the chip size and the junction capacitance of the diffusion layer cannot be sufficiently reduced.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device using an SOI substrate in which a semiconductor substrate and a diffusion layer of the same conductivity type as the substrate are used. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which can reduce the chip size without causing a short circuit and can increase the operation speed by reducing the junction capacitance of the diffusion layer.

[0016]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: an insulating layer formed on a semiconductor substrate; a semiconductor layer formed on the insulating layer; A first insulating film for element isolation formed on a region different from the semiconductor layer; a first semiconductor region formed in the semiconductor layer and having a conductivity type different from that of the semiconductor layer; A second insulating film formed on the first insulating film; and a second insulating film formed over the first semiconductor region of the second insulating film and over a part of the first insulating film. An opening in which the first semiconductor region and the semiconductor substrate are exposed; a wiring layer formed in the opening; and the wiring layer in the opening so as to be separated from the first semiconductor region. A semiconductor region formed in a surface region of the semiconductor substrate in contact with the semiconductor substrate, It is characterized by comprising a second semiconductor region electrically separating the the plate first semiconductor region.

According to a second aspect of the present invention, in the semiconductor device of the first aspect, the semiconductor substrate has a first conductivity type, and the first and second semiconductor regions have a second conductivity type.
The semiconductor substrate and the first semiconductor region are electrically separated by a PN junction between the semiconductor substrate and the second semiconductor region.

According to a third aspect of the present invention, in the semiconductor device of the first aspect, the semiconductor substrate and the first semiconductor region are each of a first conductivity type, and the second semiconductor region is a second conductivity type. A first impurity region and a second impurity region of the first conductivity type formed in the first impurity region, and a PN junction between the first impurity region and the second impurity region. The semiconductor substrate may be electrically separated from the first semiconductor region.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming an insulating layer on a semiconductor substrate; forming a semiconductor layer on the insulating layer; Forming an isolation region for element isolation;
Forming a first semiconductor region of a conductivity type different from that of the semiconductor layer in the semiconductor layer; forming an interlayer insulating film on the semiconductor layer and the isolation region; Forming an opening having a depth reaching the semiconductor substrate from above the first semiconductor region to a part of the isolation region; and forming a PN junction in the surface region of the semiconductor substrate exposed in the opening. Forming a second semiconductor region for forming the first semiconductor region separately from the first semiconductor region; and forming a wiring layer in the opening, wherein the PN is formed.
The semiconductor substrate and the first semiconductor region are electrically separated by bonding.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourth aspect, the semiconductor substrate is of a first conductivity type, and the first and second semiconductor regions are of a second conductivity type. The step of forming the second semiconductor region includes a step of ion-implanting a second conductivity type impurity into a surface region of the semiconductor substrate exposed in the opening.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourth aspect, the semiconductor substrate and the first semiconductor region are each of a first conductivity type, and the second semiconductor region is formed. Forming a first impurity region by ion-implanting a second conductivity type impurity into a surface region of the semiconductor substrate exposed in the opening; and forming a first impurity region in the first impurity region. Forming a second impurity region of the first conductivity type by ion-implanting a conductivity-type impurity.

Further, in the method of manufacturing a semiconductor device according to the present invention, a step of forming an insulating layer on a semiconductor substrate of a first conductivity type;
Forming a first semiconductor layer and a second semiconductor layer of a second conductivity type; forming an isolation region that insulates and separates the first and second semiconductor layers; and forming a second isolation layer in the first semiconductor layer. 2
Forming a first semiconductor region of a conductivity type;
Forming a second semiconductor region of the first conductivity type in the semiconductor layer, forming an interlayer insulating film on the insulating layer and on the first and second semiconductor layers, A first opening having a depth reaching the semiconductor substrate over a part of the adjacent isolation region from above the first semiconductor region; and a first opening of the isolation region adjacent from above the second semiconductor region. Forming a second opening at a depth reaching the semiconductor substrate over a portion thereof; and forming a third conductive type third hole in the semiconductor substrate exposed in the first opening. Forming a semiconductor region, forming a fourth semiconductor region of a second conductivity type in the semiconductor substrate exposed in the second opening, and forming a first semiconductor region in the fourth semiconductor region. Forming a fifth semiconductor region of a conductivity type, and wiring in the first and second openings; It is characterized by comprising a step of forming a.

According to the structure of the first aspect, the semiconductor substrate and the first semiconductor region can be electrically separated by the second semiconductor region, so that the opening is formed on the first semiconductor region from the first insulating region. Even when the first semiconductor region and the semiconductor substrate are formed over a partial region of the film, a short circuit between the first semiconductor region and the semiconductor substrate due to the wiring layer can be prevented. Thus, the chip size can be reduced, the junction capacitance of the first semiconductor region can be reduced, and the operation speed can be increased.

According to a second aspect of the present invention, the semiconductor substrate is a first type.
When the first semiconductor region of the conductivity type is the second conductivity type, the second semiconductor region of the second conductivity type is provided on the surface region of the semiconductor substrate, so that the semiconductor substrate and the second semiconductor region have a P-type conductivity.
An N-junction is formed to prevent a short circuit between the first semiconductor region and the semiconductor substrate due to the wiring layer.

According to a third aspect of the present invention, the semiconductor substrate and the first
When the first semiconductor region of the first conductivity type is provided with the first impurity region of the second conductivity type and the second impurity region of the first conductivity type in the surface region of the semiconductor substrate, the first and second impurities are provided. By forming a PN junction in the region, a short circuit between the first semiconductor region and the semiconductor substrate due to the wiring layer can be prevented.

According to the manufacturing method of the present invention, after the opening is formed, the second semiconductor region is formed in the surface region of the semiconductor substrate exposed in the opening, and the semiconductor substrate is formed by PN junction. The first semiconductor region is electrically separated from the first semiconductor region. Therefore, even if the opening is formed from the first semiconductor region to a part of the isolation region between the elements, the first semiconductor region is formed by the wiring layer. A short circuit between the region and the semiconductor substrate can be prevented. Thus, the chip size can be reduced, the junction capacitance of the first semiconductor region can be reduced, and the operation speed can be increased.

According to a fifth aspect of the present invention, the semiconductor substrate is a first type.
When the first semiconductor region is of the second conductivity type in the conductivity type, the second semiconductor region is formed by ion-implanting impurities of the second conductivity type into the surface region of the semiconductor substrate, thereby forming the second semiconductor region and the second semiconductor region. By forming a PN junction with the semiconductor region, a short circuit between the first semiconductor region and the semiconductor substrate due to the wiring layer can be prevented.

According to a sixth aspect of the present invention, the semiconductor substrate and the first
When the semiconductor region of the first conductivity type is the first conductivity type, the second conductivity type impurity is ion-implanted into the surface region of the semiconductor substrate to form the first impurity region, and then the first conductivity type impurity is ion-implanted. By forming the two impurity regions, a PN junction is formed by the first and second impurity regions, and a short circuit between the first semiconductor region and the semiconductor substrate due to the wiring layer can be prevented.

Further, according to the manufacturing method of the present invention, after the first and second openings are formed, the surface regions of the semiconductor substrate exposed in the first and second openings are respectively formed. Forming third and fourth semiconductor regions of the second conductivity type;
By forming the fifth semiconductor region of the first conductivity type in the fourth semiconductor region below the opening, the semiconductor substrate and the first and second semiconductor regions are electrically separated from each other by the PN junction. Forming a first opening from the first semiconductor region to a portion of the isolation region between the devices, and forming a second opening from the second semiconductor region to the isolation region between the devices. Even if it is formed over a part of the region, the short circuit between the first and second semiconductor regions and the semiconductor substrate due to the wiring layer can be prevented. Thus, the chip size can be reduced, the junction capacitance of the first semiconductor region can be reduced, and the operation speed can be increased.

[0030]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of the present invention.
FIG. 4 is a cross-sectional configuration diagram of a MOS field effect transistor formed on an SOI substrate, for describing the semiconductor device according to the embodiment.

As shown in FIG. 1, the SOI substrate 30 includes a P-type silicon substrate (semiconductor substrate) 1, a buried oxide film (insulating layer) 2, and silicon active layers (semiconductor layers) 3-1 and 3-.
2 are laminated. The silicon active layer 3
-1, N-type source / drain diffusion layers (first semiconductor regions) 10, 10 are formed, and these diffusion layers 10, 10 are formed.
A gate electrode 9-1 is provided on a channel region between the gate electrodes 10 via a gate insulating film 8-1 to form an NMOS transistor. Similarly, the silicon active layer 3-
2, P-type source / drain diffusion layers (first semiconductor regions) 11, 11 are formed, and these diffusion layers 11, 1 are formed.
The gate electrode 9-2 is provided on the channel region between the gate electrodes 9-2 via the gate insulating film 8-2, so that the PMOS
A transistor is configured. An oxide film (first insulating film) 7 for element isolation is provided on the buried oxide film 2 between the silicon active layers 3-1 and 3-2.
On the oxide film 7 and the silicon active layers 3-1, 3-2
An interlayer insulating film (second insulating film) 12 is formed on the entire upper surface, and the source / drain diffusion layers (first semiconductor regions) 10 of the PMOS transistor and the NMOS transistor of the interlayer insulating film 12 are formed. Contact holes (openings) 13-1, 13-1, 13-2, which have a depth reaching the silicon substrate 1, are provided at positions corresponding to the positions on the silicon substrate 10, 11, 11, respectively.
13-2 is formed. These contact holes 13-1,
Reference numerals 13-1, 13-2, and 13-2 denote elements for element isolation adjacent to the ends of the source / drain diffusion layers 10, 10, 11, 11 from the viewpoints of reducing the chip size and the diffusion layer capacitance. It is formed over oxide film 7. The source / drain diffusion layers 10, 10 and the surface of the silicon substrate 1 are exposed in the contact holes 13-1, 13-1, and the source / drain diffusion layers 11 are located in the contact holes 13-2, 13-2. , 11 and the surface of the silicon substrate 1 are exposed. On the interlayer insulating film 12 in the contact holes 13-1 and 13-1 and near the openings of the contact holes 13-1 and 13-1, a metal wiring layer 14-1 serving as a source / drain electrode of an NMOS transistor is formed. A source 14-1 of the PMOS transistor is formed on the interlayer insulating film 12 in the contact holes 13-2, 13-2 and near the openings of the contact holes 13-2, 13-2.
Metal wiring layers 14-2, 14-2 serving as drain electrodes are formed.

Further, the contact holes 13-1, 13-
On the surface region of the silicon substrate 1 exposed in the 1, N ⁺
Type impurity diffusion layers (second semiconductor regions) 15, 15 are formed. The impurity diffusion layers 15 and 15 and the silicon substrate 1 form a PN junction, and the silicon substrate 1
And the source / drain diffusion layers 10, 10 are the metal wiring layer 1
Short circuit is prevented via 4-1 and 14-1.
Similarly, in the surface region of the silicon substrate 1 exposed in the contact holes 13-2, 13-2, N ⁺ -type impurity diffusion layers 16, 16 are formed.
P ⁺ -type impurity diffusion layers 17, 17 are formed in 6, 16. These impurity diffusion layers (second semiconductor regions) 1
PN junctions are formed by the silicon substrate 1 and the source / drain diffusion layers 1 and 6, respectively.
1 and 11 are prevented from being short-circuited via the metal wiring layers 14-2 and 14-2.

According to the above configuration, the silicon substrate 1 is connected to the source / drain by the PN junction formed in the surface region of the silicon substrate 1 below the contact holes 13-1, 13-1, 13-2, 13-2. Diffusion layers 10, 10, 11, 1
1 are electrically isolated from each other, so that the contact holes 13
-1, 13-1 are formed over the source / drain diffusion layers 10, 10 over a part of the insulating film 7 for element isolation, and the contact holes 13-2, 13-2 are formed in the source / drain regions. Even if it is formed over the diffusion layers 11 and 11 over a partial region of the insulating film 7 for element isolation, the metal wiring layer 14-
The source / drain diffusion layers 10, 10, 11, 11 and the silicon substrate 1 via 1, 14-1, 14-2, 14-2
Can be prevented from being short-circuited. As a result, the chip size can be reduced, the junction capacitance of the source / drain diffusion layers can be reduced, and the operation speed can be increased.

Next, a method of manufacturing the MOS field-effect transistor shown in FIG. 1 will be sequentially described with reference to FIGS. First, as shown in FIG. 2, a SOI substrate 30 including a P-type silicon substrate 1, a buried oxide film 2 having a thickness of about 1500 Å, and a silicon active layer 3 having a thickness of about 1500 Å is thermally oxidized. After the oxide film 4 having a thickness of about 200 angstroms is formed, a polysilicon layer 5 having a thickness of about 3500 angstroms and an oxide film 6 having a thickness of about 3000 angstroms are formed by LPCVD.

Next, as shown in FIG. 3, a resist pattern 20 is formed by lithography, RIE is performed using the resist pattern 20 as a mask, and an oxide film 6 and a polysilicon layer in a region where an element isolation region is to be formed are formed. 5 is selectively removed.

Further, after the resist pattern 20 is removed, the oxide film 4 and the silicon active layer 3 are selectively removed by RIE using the oxide film 6 as a mask as shown in FIG. Thereby, semiconductor layers 3-1 and 3-2 for forming the NMOS transistor and the PMOS transistor are formed.

Subsequently, as shown in FIG.
An oxide film 7 having a thickness of about 2,000 angstroms is deposited and formed on the entire surface by the method. After that, planarization is performed using the polysilicon layer 5 as a stopper by using etch back by RIE or a CMP method to expose the polysilicon layer 5 on the element region. Thereafter, the polysilicon layer 5 is completely removed by performing a CDE process, and the oxide film 4 on the element region is exposed as shown in FIG.

Subsequently, as shown in FIG. 7, a resist pattern 21 is formed by lithography so as to cover a region where the PMOS transistor is to be formed, and a P-type impurity is ion-implanted into the region where the NMOS transistor is to be formed to form a channel region. To form

Similarly, as shown in FIG. 8, a resist pattern 22 is formed by lithography so as to cover a region where an NMOS transistor is to be formed, and an N-type impurity is ion-implanted into a region where a PMOS transistor is to be formed. To form

Next, after removing the oxide film 4 on the surface using HF wet etching, a gate oxide film having a thickness of about 100 Å is formed on the surfaces of the silicon active layers 3-1 and 3-2 by thermal oxidation. 8-1 and 8-2 are formed.
Further, on the oxide film 7 and the gate oxide films 8-1, 8
After depositing polysilicon having a thickness of about 2500 angstroms doped with an N-type impurity on -2 and patterning by RIE using lithography to form gate electrodes 9-1 and 9-2, FIG. As shown.

Next, N-type impurities are ion-implanted by masking a region where the PMOS transistor is to be formed by using lithography, thereby forming source / drain diffusion layers 10 and 10 of the NMOS transistor. When the source / drain diffusion layers 11 and 11 of the PMOS transistor are formed by ion-implanting an N-type impurity while masking a region where the transistor is to be formed, a configuration as shown in FIG. 10 is obtained.

Subsequently, as shown in FIG. 11, an oxide film is deposited as an interlayer insulating film 12 over the entire surface by LPCVD to a thickness of 5000 angstroms, and then the source / drain diffusion layers 10 of the NMOS transistor and the PMOS transistor are deposited. , 10, 11, 11 have contact holes 13-1, 13 to a depth reaching silicon substrate 1 by RIE.
-1, 13-2 and 13-2 are respectively opened. At this time, the contact holes 13-1, 13-1, 13-2, 13
-2 are source / drain diffusion layers 10, 10,.
Openings are formed from the end portions of 11, 11 over a part of the adjacent oxide film 7 for element isolation.

Next, as shown in FIG. 12, a resist pattern 23 covering the formation region of the PMOS transistor is formed by lithography, and the contact holes 13-1, 13-1 are formed using this resist pattern 23 as a mask.
N type impurities such as P and As are ion-implanted only in the inside, and N ⁺ type impurity diffusion layers 15 are formed in the surface region of the silicon substrate 1 exposed in the contact holes.

Subsequently, as shown in FIG. 13, a resist pattern 24 covering the formation region of the NMOS transistor is formed by lithography.
Are used as masks to form contact holes 13-2, 13-.
After N-type impurities such as P and As are ion-implanted into the substrate ₂ , P-type impurities such as B and BF2 are ion-implanted. Thus, N ⁺ -type impurity diffusion layers 16 and 16 and P ⁺ -type impurity diffusion layers 17 and 17 are formed in the surface region of silicon substrate 1 exposed in contact holes 13-2 and 13-2. . Here, ion implantation conditions, such as an acceleration voltage and a dose, are set so that the impurity diffusion layers 17 and 17 are formed in the impurity diffusion layers 16 and 16.

Thereafter, as shown in FIG. 14, metal wiring layers 14-1, 1, such as Al and W, are formed as source / drain electrodes.
4-1, 14-2 and 14-2 are formed to complete P-channel and N-channel MOS field effect transistors.

According to the above-described manufacturing method, after the contact holes 13-1, 13-1, 13-2, and 13-2 are opened, impurities are ion-implanted into these contact holes to form P
Since it is sufficient to form an N-junction, the contact holes 13-1, 13-1, 13-2,.
13-2 are the source / drain diffusion layers 10, 10, 11,
11 can be formed over the oxide film 7 for element isolation, the chip size can be reduced, the junction capacitance of the source / drain diffusion layers can be reduced, and the operation speed can be increased.

Next, a semiconductor device and a method of manufacturing the same according to a second embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. 15 to 18 show M
2 shows a part of a manufacturing process of an OS type field effect transistor.

First, by the manufacturing steps of FIGS. 2 to 8 described in the first embodiment, FIG.
An element isolation structure as shown in FIG. Next, the oxide film 4 on the surface is peeled off using HF wet etching, and as shown in FIG. 16, a gate having a thickness of about 1000 angstroms is formed on the surfaces of the silicon active layers 3-1 and 3-2 by thermal oxidation. Oxide films 8-1 and 8-2 are formed. Further, after depositing and forming polysilicon having a thickness of about 2500 angstroms doped with N-type impurities and a nitride film 18 having a thickness of about 1000 angstroms, patterning is performed by lithography to form a gate electrode 9-.
1, 9-2 are formed.

Next, a nitride film is deposited on the entire surface to a thickness of about 500 angstroms, and then etched back by RIE to form gate electrodes 9-1 and 9- as shown in FIG.
The spacers 19 are formed on the side wall of the second.

Subsequently, an oxide film is deposited on the entire surface as the interlayer insulating film 12 to a thickness of 5000 angstroms, and contact holes 13-1 and 13-2 for taking out source or drain electrodes are opened by lithography and RIE. I do. At this time, in order to further reduce the element size as compared with the first embodiment, the contact holes 13-
1, 13-2 are formed over the gate electrodes 9-1 and 9-2, over the source / drain diffusion layers, and over the adjacent oxide film 7 for element isolation. These contact holes 13-
In the RIE for opening the openings 1 and 13-2, a condition is adopted in which a sufficient selectivity can be obtained for the nitride films 18 and 19 covering the gate electrodes 9-1 and 9-2.

Thereafter, the device is completed by using the manufacturing method described in FIGS. 12 to 14 in the first embodiment. According to the second embodiment, since the contact holes 13-1 and 13-2 can be formed up to the gate electrodes 9-1 and 9-2, the element size can be further reduced as compared with the first embodiment. Also, the capacity of the diffusion layer can be reduced.

In the first and second embodiments, a MOS field effect transistor has been described as an example of a semiconductor device. However, the present invention is similarly applied to other semiconductor elements such as a MOS capacitor and a method of manufacturing the same. Of course it is possible.

[0053]

As described above, according to the present invention, in a semiconductor device using an SOI substrate, the chip size can be reduced without causing a short circuit between the semiconductor substrate and a diffusion layer of the same conductivity type as the substrate. It is possible to obtain a semiconductor device and a method of manufacturing the same, which can increase the operation speed by reducing the junction capacitance of the diffusion layer.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a MOS-type field effect transistor formed on an SOI substrate for describing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention, showing a first manufacturing step of the MOS field-effect transistor shown in FIG.

FIG. 3 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention, showing a second manufacturing step of the MOS field-effect transistor shown in FIG.

FIG. 4 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention, showing a third manufacturing step of the MOS field-effect transistor shown in FIG.

FIG. 5 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention, showing a fourth manufacturing step of the MOS field-effect transistor shown in FIG.

FIG. 6 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention, showing a fifth manufacturing step of the MOS field-effect transistor shown in FIG.

FIG. 7 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention, showing a sixth manufacturing step of the MOS field-effect transistor shown in FIG.

FIG. 8 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention, showing a seventh manufacturing step of the MOS field-effect transistor shown in FIG.

9 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention, showing an eighth manufacturing step of the MOS field-effect transistor shown in FIG.

FIG. 10 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention, showing a ninth manufacturing step of the MOS field-effect transistor shown in FIG.

FIG. 11 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention, showing a tenth manufacturing step of the MOS field-effect transistor shown in FIG.

12 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention, showing an eleventh manufacturing step of the MOS field-effect transistor shown in FIG.

13 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention, showing a twelfth manufacturing step of the MOS field-effect transistor shown in FIG.

14 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention, showing a thirteenth manufacturing step of the MOS field-effect transistor shown in FIG.

FIG. 15 is a view for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention, and shows a part of the manufacturing process of the MOS field effect transistor;
Sectional drawing which shows a 1st manufacturing process.

FIG. 16 is a view for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention, and shows a part of the manufacturing process of the MOS field effect transistor;
Sectional drawing which shows a 2nd manufacturing process.

FIG. 17 is a view for explaining the method of manufacturing the semiconductor device according to the second embodiment of the present invention, and illustrates a part of the manufacturing process of the MOS field effect transistor;
Sectional drawing which shows a 3rd manufacturing process.

FIG. 18 is a view for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention, and shows a part of the manufacturing process of the MOS field effect transistor;
Sectional drawing which shows a 4th manufacturing process.

FIG. 19 is a cross-sectional view for explaining the conventional semiconductor device and the manufacturing method thereof, showing a first step of forming a MOS field-effect transistor on an SOI substrate.

FIG. 20 is a cross-sectional view for explaining the conventional semiconductor device and the manufacturing method thereof, showing a second step of forming a MOS field-effect transistor on an SOI substrate.

FIG. 21 is a cross-sectional view for explaining the conventional semiconductor device and the manufacturing method thereof, showing a third step of forming a MOS field-effect transistor on an SOI substrate.

FIG. 22 is a cross-sectional view for explaining the conventional semiconductor device and the manufacturing method thereof, showing a fourth step of forming a MOS field-effect transistor on an SOI substrate.

FIG. 23 is a cross-sectional view for explaining the conventional semiconductor device and the manufacturing method thereof, showing a fifth step of forming a MOS field-effect transistor on an SOI substrate.

FIG. 24 is a cross-sectional view for explaining the conventional semiconductor device and the manufacturing method thereof, showing a sixth step of forming a MOS field-effect transistor on an SOI substrate.

FIG. 25 is a cross-sectional view for explaining the conventional semiconductor device and the manufacturing method thereof, showing a seventh step of forming a MOS field-effect transistor on an SOI substrate.

FIG. 26 is a cross-sectional view for explaining the conventional semiconductor device and the manufacturing method thereof, showing an eighth step of forming a MOS field-effect transistor on an SOI substrate.

FIG. 27 is a cross-sectional view for explaining the conventional semiconductor device and the manufacturing method thereof, showing a ninth step of forming a MOS field-effect transistor on an SOI substrate.

FIG. 28 is a cross-sectional view for explaining the conventional semiconductor device and the manufacturing method thereof, showing a tenth step of forming the MOS field-effect transistor on the SOI substrate.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Embedded oxide film, 3-1 and 3-
2 silicon active layer, 4 oxide film, 5 polysilicon layer, 6 oxide film, 7 oxide film, 8-1, 8-2 gate oxide film, 9-1, 9-2 gate electrode, 10, 11: source / drain diffusion layer, 12: interlayer insulating film, 13-1,
13-2: contact hole, 14-1, 14-2: metal wiring layer, 15: N ⁺ type impurity diffusion layer, 16: N ⁺ type impurity diffusion layer, 17: P ⁺ type impurity diffusion layer, 18: nitride film , 1
9: spacer (nitride film), 20, 21, 22, 23, 2
4 ... resist pattern, 30 ... SOI substrate.

Claims (7)

[Claims] An insulating layer formed on a semiconductor substrate; a semiconductor layer formed on the insulating layer; and a first element isolation element formed on a region of the insulating layer different from the semiconductor layer.
An insulating film formed in the semiconductor layer, a first semiconductor region of a conductivity type different from the semiconductor layer, and a second insulating film formed on the semiconductor layer and the first insulating film. ,
The second insulating film is formed from over the first semiconductor region to over a portion of the first insulating film, and the first insulating film is formed inside the first insulating region.
An opening where the semiconductor region and the semiconductor substrate are exposed,
A wiring layer formed in the opening, and formed in a surface region of the semiconductor substrate in contact with the wiring layer in the opening so as to be separated from the first semiconductor region; And a second semiconductor region electrically separating the first semiconductor region from the first semiconductor region. 2. The semiconductor substrate is of a first conductivity type, the first and second semiconductor regions are of a second conductivity type, and the semiconductor substrate is formed by a PN junction between the semiconductor substrate and the second semiconductor region. 2. The semiconductor device according to claim 1, wherein a substrate and said first semiconductor region are electrically separated. 3. The semiconductor substrate and the first semiconductor region are each of a first conductivity type, and the second semiconductor region is a first impurity region of a second conductivity type and a first impurity region of the second conductivity type. A second impurity region of the first conductivity type formed, and electrically connects the semiconductor substrate and the first semiconductor region by a PN junction between the first impurity region and the second impurity region. The semiconductor device according to claim 1, wherein the semiconductor device is separated. 4. A step of forming an insulating layer on a semiconductor substrate, a step of forming a semiconductor layer on the insulating layer, a step of forming an isolation region for element isolation of the semiconductor layer, Forming a first semiconductor region of a conductivity type different from that of the semiconductor layer, forming an interlayer insulating film on the semiconductor layer and on the isolation region, and forming a first semiconductor region on the first semiconductor region of the interlayer insulating film; Forming an opening having a depth reaching the semiconductor substrate over a portion of the isolation region, and forming a PN junction in a surface region of the semiconductor substrate exposed in the opening. Forming a second semiconductor region apart from the first semiconductor region; and forming a wiring layer in the opening, wherein the PN junction forms the semiconductor substrate and the first semiconductor region. It is characterized by being electrically separated from the area Semiconductor device manufacturing method. 5. The semiconductor substrate is of a first conductivity type, the first and second semiconductor regions are of a second conductivity type, and the step of forming the second semiconductor region includes: 5. The method according to claim 4, further comprising a step of ion-implanting a second conductivity type impurity into the exposed surface region of the semiconductor substrate. 6. The semiconductor substrate and the first semiconductor region are each of a first conductivity type, and the step of forming the second semiconductor region includes a step of forming a surface region of the semiconductor substrate exposed in the opening. The first conductivity type impurity is ion-implanted into the first
Forming a second impurity region of the first conductivity type by ion-implanting an impurity of the first conductivity type into the first impurity region. A method for manufacturing a semiconductor device according to claim 4. 7. A step of forming an insulating layer on a semiconductor substrate of a first conductivity type, and forming a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type on the insulating layer. Performing a step of forming an isolation region that insulates and separates the first and second semiconductor layers; forming a first semiconductor region of a second conductivity type in the first semiconductor layer; Forming a second semiconductor region of a first conductivity type in a second semiconductor layer; forming an interlayer insulating film on the insulating layer and on the first and second semiconductor layers; A first opening having a depth reaching the semiconductor substrate over a part of the isolation region adjacent to the first semiconductor region of the insulating film; and the isolation opening adjacent to the second semiconductor region. Forming second openings each having a depth reaching the semiconductor substrate over a part of the region; Forming a third semiconductor region of a second conductivity type in the semiconductor substrate exposed in the first opening; and forming a third semiconductor region in the semiconductor substrate exposed in the second opening. Forming a fourth semiconductor region of the second conductivity type, forming a fifth semiconductor region of the first conductivity type in the fourth semiconductor region, and forming the first and second openings in the fourth semiconductor region. Forming a wiring layer in the semiconductor device.