JP2000020486A - SIMD type computing unit - Google Patents

Abstract

(57) [Summary] [PROBLEMS] In a conventional SIMD type arithmetic unit, when an overflow occurs as a result of an arithmetic operation or when a double precision arithmetic operation is performed, arithmetic processing of three cycles or more is required, and the number of processing times can be reduced. It aims to. SOLUTION: A plurality of (2 ⁿ ) data storage units are provided in two data input units, and only half of the data storage units are used as valid data storage units, and the rest are used as invalid data storage units. At the time of arithmetic processing, only data stored in the valid data storage unit is used. The length of the data is doubled, connected to each operation, and output to a double-length data storage unit to solve the above problem. The above solution is effective even when one of the data input means has only one valid data storage. At the time of arithmetic processing, the sign extension of data is also considered.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a SIMD (Single Instruction) for a microprocessor.
The present invention relates to an ion multiple data type arithmetic unit.

[0002]

2. Description of the Related Art There is a SIMD as a method for processing a plurality of data in a microprocessor in parallel. Generally, the SIMD method is a processing unit in a microprocessor in which a plurality of operations having different data but the same function are processed in parallel by a single instruction. There is an advantage that sharing can be achieved and the time of the execution process can be reduced.

[0003]

In the conventional SIMD type arithmetic unit, the length of the data length of the data storage section of the input means is the same as the length of the data length of the data storage section of the output means. For this reason, when overflow occurs as a result of an operation or when a double-precision operation is performed, at least one operation for generating a lower output result and an operation for generating a higher output result is performed.
It is necessary to separately perform processing for each time and combine the obtained upper and lower output results.

For example, FIGS. 1 (a), 1 (b) and 1 (c)
The state of a conventional SIMD operation in which the input means 2 having a length of 64 bits is composed of eight 8-bit data, four 16-bit data, and two 32-bit data is shown. In the conventional SIMD operation, if the data length of the input data storage unit 4 is 8 bits, the same eight-bit operation is simultaneously executed eight times and the result is output to the output means 6 [A
Illustration of DD instruction, FIG. 1 (a)]. When performing double precision operation in this configuration, first, the lower 8-bit operation of the output is performed, the result is stored in the memory, then the upper 8-bit operation of the output is performed, and the lower-order data stored earlier is stored. Must be loaded to create double precision data.

An object of the present invention is to provide a SIMD type arithmetic unit capable of performing double-precision arithmetic with a smaller number of cycles than in the prior art. Further, according to the present invention, when one fixed value is used as a coefficient in multiplication, for example, only one coefficient data is prepared and the SIMD operation is executed [FIG.
(See FIG. 2 (a)), and the coefficient data can be converted without preparing a SIMD type arithmetic unit [FIG. 2 (b)] capable of performing the double precision operation as described above or SIMD type input data in which a plurality of the same numerical values are arranged. A SIMD type arithmetic unit [FIG. 2 (c)] that loads only one register and executes a SIMD operation [broadcast format, see FIG. 3 (b)] and capable of performing the double precision operation as described above. It is intended to be.

[0006]

Means for Solving the Problems A first aspect of the present invention is as follows.
A SIMD type operation unit having two operation data input means and one operation result data output means, wherein both the first input means and the second input means have a predetermined data length, and has 2 ⁿ pieces are of equal data storage unit, the output unit are the same length and said input means, and to 2 ^n-1 pieces have a same data storage unit of length. Conventional SIMD
If it is a type arithmetic unit, data (A) stored in each data storage unit of the first input means and corresponding data (B) stored in each data storage unit of the second input means (C) obtained as a result of performing a predetermined operation using
Is stored in the data storage section of the corresponding output means. In the SIMD type arithmetic unit of the present invention, each of the first input means and the second input means has 2 ^{n -1} data storage sections. , And 2 ^{n -1} invalid data storage units, and the valid data of the first input means and the second
The result calculated using the corresponding valid data of the input means is stored in the corresponding data storage of the output means.

In the above computing unit, 2 ^{n -1} invalid data storage units and 2 ^{n -1} valid data storage units are provided for the data storage units in each of the first input means and the second input means. They may be arranged alternately.

[0008] The value of n can change depending on the designation of an instruction.

A second embodiment of the present invention is a SIM having two operation data input means and one operation result data output means.
A D-type arithmetic unit, wherein the first input means has 2 ⁿ data storage units having a predetermined data length and the same length, and the second input means has at least the first input means. One data storage unit having a length equal to or greater than the data length of the data storage unit of the means and having the same length as the data storage unit of the first input means.
And the output means has 2 ^{n -1} data storage units having the same length and the same length as the first input means.
If it is a conventional SIMD type arithmetic unit, data (A) stored in each data storage unit of the first input means and data (B) stored in one data storage unit of the second input means The data (C) obtained as a result of performing a predetermined operation by using the above is stored in the data storage unit of the corresponding output means.
Each of the data storage units in the input means comprises 2 ^n-1 valid data storage units and 2 ^n-1 invalid data storage units,
The result calculated using each valid data of the first input means and the data of the second input means is stored in a corresponding data storage section of the output means.

In the above-mentioned arithmetic unit, 2 ^{n -1} invalid data storage units and 2 ^{n -1} valid data storage units may be alternately arranged with respect to the data storage unit in the first input means.

Further, the value of n can be changed by the designation of an instruction.

In both the first and second modes of the present invention, the data stored in the valid data storage section of the input means is extended to the data length of the data storage section of the output means. Then, when connecting to a predetermined operation, it is possible to select whether to perform sign extension or not.

[0013]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 2A shows a first embodiment of S
An IMD type operation unit (hereinafter, referred to as an operation unit) 10 is shown,
The arithmetic unit 10 has a first input register 12, a second input register 14, and an output register 16. In the present embodiment, the first input register 12 has a data length of 64.
The input data storage section 18 is divided into eight bits and divided into eight bits. These eight input data storage units 18 form a set of two adjacent data storage units,
The upper side is an invalid data storage unit (DC: Don't C).
are) 20 and the lower side is a valid data storage unit 22. The second input register 14 is the first input register 1
2, and includes a plurality of adjacent upper invalid data storage units (DC: Don't Care) 24 and lower valid data storage units 26.

The output register 16 includes the input register 12,
14 has a data length of 64 bits, and is divided into 16 bits to output four output data storage units (C0 to C3).
28. Here, each data storage unit 28
Are valid data storage units 22 of the input registers 12 and 14,
26, for example, a data storage unit (hereinafter referred to as a data storage unit C
It is called 0. ) Correspond to the valid data storage units A0 and B0.

According to the arithmetic unit 10 having the above configuration,
The operation data A0 to A3 stored respectively in the valid data storage unit 22 of the first input register 12 and the corresponding valid data storage unit 26 of the second input register 14
A predetermined operation is performed using the operation data B0 to B3 stored in the storage device, and the operation result is stored in the corresponding output data storage units C0 to C3.

According to the arithmetic unit 10 configured as described above, the data length of each output data storage unit 28 is twice the data length of each input data storage unit. Double-precision calculations that required higher-order calculations, lower-order calculations, and synthesis calculations can be performed by one calculation process.

Each valid data store 22 in the first input register 12 must be associated with a different one of the valid data stores 26 in the second input register 14. This is because arithmetic processing is performed based on this association. However, if the correspondence is established, each valid data storage unit 22, 26 and each invalid data storage unit 2
0 and 24 may be arranged at random.

The number 2 ⁿ of the data storage units 18 in the input registers 12 and 14 (that is, twice the number of the data storage units 28 in the output register 16) 2 ⁿ can be varied depending on the contents of the instruction to the arithmetic unit 10 (FIG. a), (b),
(C)). Even if the value of n fluctuates, a double-precision SIMD operation can be performed by one operation in the same manner as described above.

FIG. 2B shows an arithmetic unit according to the second embodiment. This arithmetic unit is generally composed of a first input register 32, a second input register (or immediate value, etc.) 34, and an output register 36, similarly to the arithmetic unit of the first embodiment described above. The first input register 32 stores the first
It has the same configuration as the first input register 12 of the embodiment. The second input register (or immediate value, etc.) 34
It has a data length of 12 bits, which is composed of an 8-bit valid data storage section 42 and a 4-bit invalid data storage section 40.

The output register 36 has the same configuration as the output register 16 of the first embodiment. Here, each data storage unit 44 is associated with only one valid data storage unit 42 of the second input register (or immediate value, etc.) 34 and each valid data storage unit 38 of the first input register 32. For example, the data storage unit C0
Corresponds to the valid data storage units A0 and B0, and C1 corresponds to A1 and B0.

According to this arithmetic unit, the operation data A0 to A3 stored in the effective data storage unit 38 of the first input register 32 and the corresponding second input register (or immediate value) 34 are stored. A predetermined operation is performed using the operation data B0 stored in the effective data storage unit 42 of the output data storage unit 42 corresponding to the output data storage unit C0.
To C3.

According to the arithmetic unit configured as described above, not only the effect obtained in the first embodiment but also the necessity of preparing a second input register in which four pieces of operation data B0 are arranged in parallel is eliminated. , A second input register (or an immediate,
Etc.) There is an inherent advantage that the data length of 34 can be shortened.

FIG. 2C shows an arithmetic unit according to the third embodiment.
Shown in This computing unit is also generally composed of a first input register 52, a second input register 54, and an output register 56, similarly to the computing unit of the first embodiment described above.
The first input register 52 has the same configuration as that of the first input register 12 of the first embodiment, except that the first input register 52 is divided into 16 bits and configured by four input data storage units. The second input register 54 has a data length of 64 bits of the same length as that of the first input register 52, and
It comprises a 6-bit valid data storage unit 62 and a 48-bit invalid data storage unit 60.

The output register 56 of the first embodiment is also the same as that of the first embodiment except that the output register 56 is divided into 32 bits and is constituted by two output data storage sections (C0, C1) 64.
Has the same configuration as Here, each data storage unit 64
Is associated with only one valid data storage unit 62 of the second input register 54 and each valid data storage unit 58 of the first input register 52. For example, the data storage unit C0 stores the valid data In the storage units A0 and B0,
C1 corresponds to A1 and B0.

According to this arithmetic unit, the operation data A0 and A1 stored in the effective data storage unit 58 of the first input register 52 and the corresponding effective data storage unit of the second input register 54 are stored. A predetermined operation is performed using the operation data B0 stored in 62 and the operation result is stored in the corresponding output data storage units C0 and C1.

According to the arithmetic unit configured as described above, not only the effect obtained in the first embodiment but also the necessity of preparing a second input register in which two operation data B0 are arranged in parallel is eliminated. There are inherent advantages of

In the second and third embodiments, each valid data storage section 38,
58 and the invalid data storage units 46 and 66 may be arranged at random. In the second input registers 34 and 54, the valid data storage units 42 and 62 may be located anywhere on the registers. In the third embodiment, the data length of the second input register 54 may be longer than that of the first register 52.

In the second and third embodiments, the data storage units 48, 6 in the first input registers 32, 52
8 (that is, twice the number of the data storage units 44 and 64 in the output registers 36 and 56) 2 ⁿ can be varied depending on the contents of the instruction to the arithmetic unit (FIGS. 2A and 2B).
(C)). Even if the value of n fluctuates, a double-precision SIMD operation can be performed by one operation as in the above.

In the above description, the data length between the first input register (and the second input register in the first and third embodiments) and the output register is 64 bits. The data length is not limited to this, for example, 128
It may be a bit.

In the arithmetic unit according to the present invention, input data is extended when performing double precision arithmetic. At this time, if the data is regarded as signed data (two's complement), the sign of the data is extended to the upper part, and if the data is regarded as absolute value data, “0” is substituted into the upper part. The selection is made by separately writing the operation instruction. Specifically, FIG. 4 shows a state where sign extension is performed as 16-bit data when performing double-precision operation on 8-bit data. When the 8-bit input data 200 is regarded as signed data (SIGN), the sign bit X7 is extended to a higher order and connected to the operation. The 8-bit input data 200 is converted to absolute value data (UN
SIGN), “0” is assigned to the extension bit S.

[0031]

As is apparent from the above description, according to the SIMD type arithmetic unit of the present invention, double-precision arithmetic operations which conventionally required at least three cycles can be realized with a smaller number of cycles. In addition, in the calculation, selection of signed or unsigned data can be considered.

The double precision operation can be realized even when one of the two input means has only one valid data storage. In addition, in the calculation in that case, selection of signed or unsigned data can be considered.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a conventional SIMD arithmetic unit (single precision).

FIG. 2 is a configuration diagram of a double precision SIMD arithmetic unit according to the present invention.

FIG. 3 is an explanatory diagram of a single precision conventional broadcast.

FIG. 4 is an explanatory diagram of a SIGN extension.

[Explanation of symbols]

2 ... input means, 4, 18, 48, 68 ... input data storage unit, 6 ... output means, 10 ... SIMD type arithmetic unit of the first embodiment, 12, 32, 52 ... First input register, 14, 54... Second input register, 3
4... Second input register (or immediate value, etc.), 1
6, 36, 56 ... output register, 20, 46, 66
... Invalid data storage of first register, 22, 3
8, 58 ... valid data storage section of first register, 2
4, 40, 60: invalid data storage of the second register, 26, 42, 62: valid data storage, 28,
44, 64... Output data storage unit, A0, A1, A
2, A3, B0, B1, B2, B3, C0, C1, C
2, C3 ... operation data, 200 ... 8-bit input operation data

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor: Sugitaka Shioki 1-3-6 Nakamagome, Ota-ku, Tokyo Inside Ricoh Co., Ltd. (72) Kazuhiko Hara 1-3-6 Nakamagome, Ota-ku, Tokyo No. Inside Ricoh Company

Claims (7)

[Claims] An SIMD (Single I / O) having two operation data input means and one operation result data output means.
a first input means and a second input means each having a predetermined data length and having 2 ⁿ data storage units having the same length; The means has 2 ^{n -1} data storage units having the same length and the same length as the input means, and data (A) stored in each data storage unit of the first input means and The data (C) obtained by performing a predetermined operation using the data (B) stored in each data storage unit of the second input means corresponding to the second input means is stored in the data storage unit of the corresponding output means. In the arithmetic unit, each data storage unit in each of the first input means and the second input means comprises 2 ^n-1 valid data storage units and 2 ^n-1 invalid data storage units. Valid data of the first input means and second input Stored in the corresponding data storage portion of the output means a result obtained by calculation using the stage of the corresponding valid data. 2. The data storage section of each of the first input means and the second input means, wherein 2 ^n-1 invalid data storage sections and 2 ^n-1 valid data storage sections are alternately arranged. The arithmetic unit according to claim 1, wherein: 3. A first input means and second input means and output means having a 2 ^n-1 pieces of data storage unit having 2 ⁿ pieces of data storage unit, the value of n is the specification of the instruction An arithmetic unit according to any one of the preceding claims, which can vary. 4. An SIMD type arithmetic unit having two operation data input means and one operation result data output means, wherein the first input means has a predetermined data length and is equal in length. It has 2 ⁿ data storage units, and the second input means is at least as long as the data length of the data storage section of the first input means, and has a length equal to that of the data storage section of the first input means. The output means has the same length as the first input means and has 2 ^{n -1} data storage parts having the same length; Data (C) obtained by performing a predetermined operation using data (A) stored in each data storage unit and data (B) stored in one data storage unit of the second input means. ) In the data storage section of the corresponding output means, the first input means Definitive respective data storage unit is made up of a 2 ^n-1 pieces of valid data storage unit and the 2 ^n-1 pieces of invalid data storage unit, and the data of each valid data and the second input means of the first input means The result of the calculation is stored in the corresponding data storage of the output means. 5. The data storage section of the first input means, wherein 2 ^n-1 invalid data storage sections and 2 ^n-1 valid data storage sections are alternately arranged. Arithmetic unit. 6. The output means having a first input means and the 2 ^n-1 pieces of data storage unit with the 2 ⁿ data storage unit, the value of n may vary with the specified instruction, claims An arithmetic unit according to claim 4 or claim 5. 7. The arithmetic unit according to claim 1, wherein the data stored in the valid data storage unit of the input unit is extended to a data length of the data storage unit of the output unit and a predetermined length is set. When linking to an operation, it is possible to select whether to perform sign extension or not.