JP2000022331A - Method for forming wiring pattern of build-up multilayer board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To flatten the surface of a wiring layer by equalizing the thickness of the plating of the wiring pattern made by electrolytic plating, in the manufacturing process of a build-up multilayer board. SOLUTION: One piece or plural pieces of wiring pattern formation blocks 22 are made at a work board 21, and wiring patterns for one piece or plural pieces of build-up multilayer boards 11 are made at each wiring pattern formation block 22. A band-shaped dummy patter 23 is made around each wiring pattern formation block 2 by electrolytic copper plating at the same time with the wiring pattern within the wiring pattern formation block 22. The width w of the dummy pattern 23 is made 1/10-1/3 of one side of the wiring pattern formation block or made in 10 mm or more. After electrolytic copper plating, the surface of the wiring pattern formation block 22 is polished to equalize the thickness of the plating of the wiring pattern. At this time, the dummy pattern 23 performs the role as the guide for regulating the quantity of polishing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring pattern on a build-up multilayer substrate, wherein a wiring pattern is formed on an insulating layer by electrolytic copper plating in a process of manufacturing the build-up multilayer substrate.

[0002]

2. Description of the Related Art With the recent increase in performance and miniaturization of IC chips, increasing the wiring density and increasing the number of pins of a substrate on which the IC chip is mounted have become important technical issues. Current,
An example of a high-density mounting board that has been put into practical use is a build-up multilayer board. A general manufacturing method of this build-up multilayer board is to form an epoxy-based photosensitive insulating layer on both sides or one side of a glass epoxy substrate serving as a core substrate, and to form a via hole in the photosensitive insulating layer by a photo-etching method. Thereafter, an inner layer wiring pattern and a via conductor are formed thereon by electrolytic copper plating, and thereafter, the same steps are sequentially repeated to form a multilayer.

[0003]

With the recent increase in the performance of IC chips, the number of stacked build-up multi-layer substrates tends to increase. Unevenness tends to be large. In particular, when the wiring pattern is formed by electrolytic copper plating, the thinner the line width of the wiring pattern is, the more easily the plating thickness becomes thicker, and the plating thickness is not affected by the difference in current distribution at the time of plating due to the unevenness of the wiring density. Become uniform. For this reason, the plating thickness of the wiring pattern formed by electrolytic copper plating varies, and the maximum height difference between the wirings is 10
μm. In a build-up multi-layer board, a plurality of insulating layers and wiring pattern layers are alternately formed. growing. Therefore, when an IC chip is surface-mounted by flip-chip bonding (C4) on a build-up multi-layer substrate having a large number of stacked layers, a connection failure easily occurs due to unevenness of the substrate surface, and a contact failure in an inner layer occurs. It will be easier. Therefore, in the current build-up multilayer substrate, the number of laminations is limited due to the necessity of reducing unevenness on the substrate surface and each layer, resulting in a limitation on high-density wiring.

The present invention has been made in view of such circumstances, and accordingly, it is an object of the present invention to make a plating thickness of a wiring pattern formed by electrolytic copper plating uniform in a manufacturing process of a build-up multilayer substrate. A method of forming a wiring pattern of a build-up multilayer board that can flatten the wiring layer surface and achieve both high-density wiring by increasing the number of layers of the build-up multilayer board and improvement in chip bonding reliability can be achieved. To provide.

[0005]

According to a first aspect of the present invention, there is provided a method for forming a wiring pattern on a build-up multilayer substrate, comprising the steps of: forming a strip-shaped dummy pattern around a wiring pattern forming block; At the same time, it is formed by electrolytic copper plating. In this way, during electrolytic copper plating, a current can be stably supplied to the wiring pattern forming portion through the dummy pattern forming portion around the wiring pattern forming block, and the variation in the plating thickness of the wiring pattern can be reduced. it can.

In this case, one or a plurality of wiring patterns of the build-up multilayer substrate are formed in the wiring pattern forming block, and the dummy pattern formed around the wiring pattern is finally formed. You may make it resect.

Further, the surface of the wiring pattern forming block may be polished. In electrolytic copper plating, the thinner the line width of the wiring pattern is, the more easily the plating thickness becomes thicker.Therefore, the plating thickness of the strip-shaped dummy pattern, which is much wider than the wiring pattern, is greater than the plating thickness of the wiring pattern. However, since the distribution of current flowing through the strip-shaped dummy pattern during electrolytic copper plating becomes uniform, the plating thickness of the dummy pattern becomes uniform. Therefore, if the surface of the wiring pattern forming block is polished with a polishing pad or the like using the plating thickness of the dummy pattern as a guide, the plating thickness of the wiring pattern can be made uniform with the plating thickness of the dummy pattern.

In this case, the width of the dummy pattern is set to be 1/10 of one side of the wiring pattern forming block.
It is good to form above. By doing so, the plating thickness of the dummy pattern is sufficiently uniform, and when the surface of the wiring pattern forming block is polished with a polishing pad or the like, the dummy pattern sufficiently serves as a guide for regulating the polishing amount. The mechanical strength that can be achieved can be secured.

Alternatively, the width of the dummy pattern may be formed to be 10 mm or more. In this way, at the time of electrolytic copper plating, the current supply from the dummy pattern forming portion to the wiring pattern forming portion is sufficiently stable, and the variation in the plating thickness of the wiring pattern is sufficiently reduced,
It is not necessary to polish the surface of the wiring pattern forming block, or it is only necessary to polish lightly.

Further, as the area of the wiring pattern forming block increases, the current distribution of the wiring pattern during electrolytic copper plating varies (the plating thickness of the wiring pattern varies).
In consideration of the increase in the size, it is preferable that one side of the wiring pattern forming block is formed to be 50 mm or less. By doing so, the variation in the current distribution in the wiring pattern forming portion in the wiring pattern forming block is reduced, and the plating thickness of the wiring pattern is almost uniform,
It is not necessary to polish the surface of the wiring pattern forming block, or it is only necessary to polish lightly.

[0011]

[Embodiment (1)] An embodiment (1) of the present invention will be described below with reference to the drawings. First, the structure of the build-up multilayer substrate 11 manufactured by the manufacturing method of the embodiment (1) will be described with reference to FIG. The core substrate 12 is formed of, for example, a glass epoxy substrate, a metal substrate, or the like, and a through hole 13 is formed at a predetermined position. The wiring pattern 14 and the through-hole conductor 15 are formed on the upper and lower surfaces of the core substrate 12 and the inner peripheral surface of the through hole 13 by electroless copper plating or electrolytic copper plating so as to be electrically connected to each other. The groove and the inside of the through-hole conductor 15 are filled with a flattening resin 16 so that the substrate surface is flattened.

An epoxy-based photosensitive insulating layer 17 is formed on the wiring patterns 14 on both surfaces of the core substrate 12, and via holes 18 are formed at predetermined positions of the photosensitive insulating layer 17 by photoetching. A wiring pattern 19 and a via conductor 20 are formed on the surface of the photosensitive insulating layer 17 and the via holes 18 by electrolytic copper plating. These insulating layers 17, wiring patterns 19, and via conductors 20 are formed in the required number of layers (only two layers are shown in FIG. 1). Although not shown, the lowermost via conductor 20 on the lower surface side of the build-up multilayer substrate 11 has Ni / Au
BGA (Ball Grid Array) bumps are formed through plating, and flip-chip bonding pads are formed on the uppermost via conductors 20 on the upper surface side of the build-up multilayer substrate 11.

When manufacturing this build-up multilayer board 11, a large number of build-up multilayer boards 11 are simultaneously formed on one work board 21 as shown in FIG. One or a plurality of wiring pattern forming blocks 22 are formed on the work substrate 21, and each wiring pattern forming block 2 is formed.
In 2, a wiring pattern 19 for one or a plurality of build-up multilayer substrates 11 (in the example of FIG. 2, nine) is formed. Around the wiring pattern forming block 22, a strip-shaped dummy pattern 23 is formed by a semi-additive method at the same time as the wiring pattern 19 in the wiring pattern forming block 22 by electrolytic copper plating. In this case, the width W of the dummy pattern 23 is one side L of the wiring pattern forming block 22.
1/10 or more (preferably 1/10 to 1/3) or 1
It is formed so as to be 0 mm or more (W ≧ L / 10 or W ≧ 10 mm).

Next, the manufacturing process of the build-up multilayer substrate 11 will be described with reference to FIGS. Here, FIG.
Is a flowchart showing a flow of a manufacturing process of the build-up multilayer substrate 11, and FIGS. 4 and 5 are partial cross-sectional views schematically showing a substrate formation state in each process.

First, in the first step (1), a through hole 18 is punched at a predetermined position on the core substrate 12 having the same size as the work substrate 21 shown in FIG.
Then, the wiring pattern 14 and the through-hole conductor 15 are formed on the upper and lower surfaces of the core substrate 12 and on the inner peripheral surface of the through-hole 13 by electroless copper plating or electrolytic copper plating so as to be electrically connected to each other.

In the next step (3), the groove between the wiring patterns 14 of the core substrate 12 and the inside of the through-hole conductor 15 are filled with a planarizing resin 16 to planarize the substrate surface. In the next step (4), an epoxy-based photosensitive resin is applied on the core substrate 12 with a spin coater or the like, and is pre-baked to form a photosensitive insulating layer 17. In the next step (5), the photosensitive insulating layer 17 is exposed to light and developed to form a photosensitive insulating layer 17.
Then, a via hole 18 is formed.

In the next step (6), an electroless copper plating film 24 is formed on the entire surface of the photosensitive insulating layer 17 and the inner peripheral surface of the via hole 18 by electroless copper plating. In the next step (7), a plating resist pattern 25 is formed on the surface of the electroless copper plating film 24 as follows. First, a dry film of a photosensitive resist is laminated on the entire surface of the electroless copper plating film 24. Alternatively, instead of laminating the dry film, a liquid photosensitive resist may be applied to the entire surface of the electroless copper plating film 24 using a spin coater or the like. Thereafter, the photosensitive resist is exposed and developed to remove portions of the photosensitive resist where the via-hole conductor 20, the wiring pattern 19 and the dummy pattern 23 are to be formed, thereby forming a plating resist pattern 25. At this time, the width W of the dummy pattern 23 is equal to or more than 1/10 of one side L of the wiring pattern forming block 22 (preferably 1 /
10 to 1/3) or 10 mm or more (W ≧ L / 10 or W
≧ 10 mm)
To form

In the next step (8), the electroless copper plating film 2
4 is subjected to electrolytic copper plating on the portion exposed from the plating resist pattern 25 to form an electrolytic copper plating pattern (a surface portion of the via hole conductor 20, the wiring pattern 19 and the dummy pattern 23). In the electrolytic copper plating, the thinner the line width of the electrolytic copper plating patterns 19, 20, and 23, the more easily the plating thickness becomes thicker.
As shown in FIG. 6A, the plating thickness of the strip-shaped dummy pattern 23 whose line width is much larger than that of the wiring pattern 19 is smaller than the plating thickness of the wiring pattern 19. Since the distribution of the flowing current is uniform, the plating thickness of the dummy pattern 23 is uniform. Further, the plating thickness of the wiring pattern 19 becomes non-uniform due to a difference in current distribution at the time of plating due to a variation in wiring density.

Therefore, in the next step (9), a polishing pad,
A polishing member 26 such as a whetstone is formed by electrolytic copper plating patterns 19 and 2.
The surface of the wiring pattern forming block 22 is polished by repeatedly reciprocating sliding in the horizontal direction while being placed on the wiring pattern
Uniform plating thickness. At this time, the dummy pattern 23
Serves as a guide for regulating the polishing amount, and makes the plating thickness of the wiring pattern 19 uniform with the plating thickness of the dummy pattern 23 as shown in FIG.

In the next step (10), the plating resist pattern 25 is stripped and removed using a stripper, and in the etching step (11), the electrolytic copper plating patterns 19, 20, and 2 are removed.
Using 3 as an etching resist (mask), unnecessary portions (exposed portions) of the electroless copper plating film 24 are removed by etching. Thereby, the via-hole conductor 20,
The wiring pattern 19 and the dummy pattern 23 are formed.

Since the surfaces of the via hole conductor 20 and the wiring pattern 19 are roughened in the etching step (11), the polishing step may be performed again in the next step (12). This polishing step (12) need not be performed if the degree of surface roughening due to etching is small. Since the polishing step (9) is intended for planarization, it may be performed after the plating resist pattern stripping step (10) or after the etching step (11).

In the above steps, the first photosensitive insulating layer 17
After that, these steps are sequentially repeated until the required number of laminations is reached.
One or a plurality of build-up multilayer substrates 11 are simultaneously formed in one or a plurality of wiring pattern forming blocks 22. In the last step, a portion of the dummy pattern 23 is cut off from the work board 21. Further, when a plurality of build-up multilayer boards 11 are formed in the wiring pattern forming block 22, each of the build-up multilayer boards 11 is formed. Substrate 11
Are cut along the boundary line 27 (see FIG. 2) to divide each build-up multilayer substrate 11. Thus, the manufacture of the build-up multilayer substrate 11 is completed.

In the embodiment (1) described above, after the electrolytic copper plating, the surface of the wiring pattern forming block 22 is polished by the polishing member 26 using the dummy pattern 23 as a guide. Can be uniformed to the plating thickness of the dummy pattern 23, and the wiring layer can be flattened. For this reason, even if the number of layers of the build-up multilayer substrate 11 is increased as compared with the conventional case, unevenness on the substrate surface can be reduced,
The reliability of flip-chip bonding can be improved, and both high-density wiring due to an increase in the number of stacked layers and improvement in reliability of flip-chip bonding can be achieved.

In addition, since the width W of the dummy pattern 23 is formed to be 1/10 or more or 10 mm or more (W ≧ L / 10 or W ≧ 10 mm) of one side L of the wiring pattern forming block 22, the dummy pattern during electrolytic copper plating is formed. The current flow to the pattern 23 is stable, the plating thickness of the dummy pattern 23 can be made uniform at a constant thickness, and the mechanical strength that the dummy pattern 23 can sufficiently serve as a guide for regulating the polishing amount is secured. it can. Thereby, the plating thickness of the wiring pattern 19 can be reliably made uniform at a constant thickness.

In the present embodiment (1), the width W of the dummy pattern 23 is formed to be 1/3 or less of one side L of the wiring pattern forming block 22.
It is possible to reduce the part to be cut from 1
The yield can be improved, and the product cost can be reduced.

[Embodiment (2)] In the above embodiment (1), the plating thickness of the wiring pattern 19 is made uniform by polishing the surface of the wiring pattern forming block 22. In (2), the step of polishing the surface of the wiring pattern forming block 22 is omitted or lightly polished by performing electrolytic copper plating in the electrolytic copper plating step so as to reduce the variation in the plating thickness of the wiring pattern 19 as described later. Just do it. Other steps are the same as those of the above-described embodiment (1).

In the present embodiment (2), the width W of the dummy pattern 23 is formed to be 10 mm or more in order to reduce the variation in the plating thickness of the wiring pattern 19 in the electrolytic copper plating step. Further, in consideration of the fact that the larger the area of the wiring pattern forming block 22 is, the larger the variation in the current distribution of the wiring pattern 19 during electrolytic copper plating (variation in the plating thickness of the wiring pattern 19) is, the larger the wiring pattern forming block 22 is. One side L of 22 is formed to be 50 mm or less.

As described above, when the width W of the dummy pattern 23 is formed to be 10 mm or more, the current supply from the portion where the dummy pattern 23 is formed to the portion where the wiring pattern 19 is formed becomes stable during electrolytic copper plating. The effect of reducing the variation in the plating thickness is obtained. Furthermore, if one side L of the wiring pattern forming block 22 is formed to be 50 mm or less, the variation in the current distribution in the wiring pattern 19 forming portion in the wiring pattern forming block 22 is reduced. The effect of reducing the variation is obtained. As a result, the surface of the wiring pattern forming block 22 does not need to be polished or need only be lightly polished.

In the configuration example of FIG. 1, the photosensitive insulating layer 17 and the wiring layer are laminated on both surfaces of the core substrate 12, but the photosensitive insulating layer 17 and the wiring layer are formed only on one surface of the core substrate 12. They may be stacked. The formation of the insulating layer is not limited to a photosensitive resin, and a via hole may be formed by laser using a non-photosensitive resin.

[0030]

As is apparent from the above description, according to the method for forming a wiring pattern of a build-up multilayer substrate according to the first aspect of the present invention, a strip-shaped dummy pattern is formed around a wiring pattern forming block with the wiring pattern. At the same time, it is formed by electrolytic copper plating, so it is possible to reduce the variation in the plating thickness of the wiring pattern, and achieve both high density wiring and improvement of chip bonding reliability by increasing the number of build-up multilayer boards. Can be done.

Furthermore, in the second aspect, since the dummy pattern portion is finally cut off, it is possible to avoid an increase in the size of the build-up multilayer substrate, and to meet a demand for a reduction in the size of the substrate.

Furthermore, since the surface of the wiring pattern forming block is polished in the third aspect, the plating thickness of the wiring pattern can be made uniform by ensuring that the plating thickness of the wiring pattern is equal to the plating thickness of the dummy pattern. Can be further improved.

According to the fourth aspect, the width of the dummy pattern is formed to be at least 1/10 of one side of the wiring pattern forming block, so that the plating thickness of the dummy pattern can be sufficiently made uniform and the polishing amount can be regulated. The mechanical strength of the dummy pattern can also be secured.

According to the present invention, since the width of the dummy pattern is formed to be 10 mm or more, the current supply from the dummy pattern forming portion to the wiring pattern forming portion can be stabilized at the time of electrolytic copper plating. Wiring patterns with little variation can be formed by electrolytic copper plating, eliminating the need for polishing the surface of the wiring pattern forming block.
Alternatively, it can be finished with light polishing.

According to the present invention, since one side of the wiring pattern forming block is formed to be 50 mm or less, variation in current distribution (variation in plating thickness) in the wiring pattern forming portion can be reduced. Polishing of the surface is unnecessary or can be completed by light polishing.

[Brief description of the drawings]

FIG. 1 is a partially enlarged longitudinal sectional view showing a structure of a build-up multilayer substrate according to an embodiment (1) of the present invention.

FIG. 2 is a partial plan view of a work board forming a build-up multilayer board.

FIG. 3 is a flowchart showing a flow of a manufacturing process of a build-up multilayer substrate.

FIG. 4 is a partial cross-sectional view schematically showing a substrate state in each step of a manufacturing process of a build-up multilayer substrate (part 1).

FIG. 5 is a partial cross-sectional view schematically showing a substrate state in each step of a manufacturing process of a build-up multilayer substrate (part 2).

FIG. 6A is an enlarged vertical sectional view showing a state of a wiring pattern and a dummy pattern before polishing (after electrolytic copper plating),
(B) is an enlarged vertical sectional view showing the state of the wiring pattern and the dummy pattern after polishing.

[Explanation of symbols]

11: Build-up multilayer board, 12: Core board, 13 ...
Through-hole, 14: wiring pattern, 15: through-hole conductor, 16: flattening resin, 17: photosensitive resin, 18 ...
Via hole, 19: wiring pattern, 20: via conductor, 2
DESCRIPTION OF SYMBOLS 1 ... Work board, 22 ... Wiring pattern formation block, 2
3 ... Dummy pattern, 24 ... Electroless copper plating film, 25
... plating resist pattern, 26 ... polishing member.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5E346 AA02 AA12 AA15 AA43 BB01 BB15 CC09 CC32 DD24 DD32 DD33 EE33 FF09 FF10 FF14 GG40 HH11 HH25

Claims (6)

[Claims] 1. A method of forming a wiring pattern on an insulating layer by electrolytic copper plating in a process of manufacturing a build-up multilayer substrate, comprising: forming a strip-shaped dummy pattern around a formation block of the wiring pattern with the wiring pattern. A method for forming a wiring pattern on a build-up multilayer substrate, wherein the wiring pattern is formed by electrolytic copper plating at the same time. 2. A forming block of the wiring pattern,
2. The method for forming a wiring pattern of a build-up multilayer substrate according to claim 1, wherein a wiring pattern for one or a plurality of build-up multilayer substrates is formed, and a portion of the dummy pattern is finally cut off. . 3. The method for forming a wiring pattern of a build-up multilayer substrate according to claim 1, wherein the surface of the wiring pattern forming block is polished. 4. The build-up multilayer board according to claim 1, wherein the width of the dummy pattern is formed to be at least 1/10 of one side of a block on which the wiring pattern is formed. Wiring pattern forming method. 5. The method for forming a wiring pattern on a build-up multilayer substrate according to claim 1, wherein the width of the dummy pattern is formed to be 10 mm or more. 6. The method for forming a wiring pattern of a build-up multilayer substrate according to claim 1, wherein one side of the block on which the wiring pattern is formed is formed to be 50 mm or less.