JP2000035878A - Addition operation device and semiconductor memory device with addition operation function - Google Patents

Abstract

(57) [Summary] [Problem] An addition operation is realized using a memory array itself. [MEANS FOR SOLVING PROBLEMS] When performing an addition operation of each digit with respect to two pieces of binary data, the value of a binary input bit is previously written in each of the memory cells MCa, MCb, MCc by a normal writing procedure in a DRAM. Bit line pair BLi
, BLi- are precharged to a reference voltage of 0.5 VDD, and the corresponding word lines Wa, Wb, Wc are activated, and the charges stored in the memory cells MCa, MCb, MCc are transferred via the common bit line BLi. Add together. The first sense amplifier S / A1 performs a normal binary-type detection and amplification operation, and performs the potential Ve4 of the bit line BLi and the comparison reference voltage Vre.
It outputs binary data of "1" or "0" according to the magnitude relationship with f1. The second sense amplifier S / A2 also performs a normal binary detection and amplification operation, and sets "1" according to the magnitude relationship between the potential Ve4 of the bit line BLi and the comparison reference voltage Vref2.
Alternatively, binary data of “0” is output. As a result, 2-bit binary data [Ve4 (MSB), Ve4 (LSB)] is obtained from the sense amplifiers S / A1 and S / A2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0010]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for performing an addition operation on binary data, and more particularly to a semiconductor memory device capable of performing not only storage of information but also an addition operation.

[0020]

2. Description of the Related Art FIG. 40 shows the principle of an addition operation on binary data. Assuming that the number of bits of the augend a and the addend b are (n + 1), the least significant bits (a0, b0)
), (N + 1) addition operations are performed one digit at a time. In the addition operation of each digit (x digit), three input bits of an augend bit ax, an addend bit bx, and a carry bit cix from the lower digit are added with equal weights, and are added to a truth table as shown in the figure. Therefore, the sum Sx and the carry bit Cox to the upper digit are generated.

FIG. 41 shows a Boolean algebra representing the above truth table, and a circuit configuration of an addition operation circuit which faithfully implements the logic of the Boolean algebra with a gate circuit. Although the conventional binary addition operation device has a smaller number of gates than that shown in the figure, it is basically constituted by the same logic circuit.

[0040]

The above-described conventional logic-circuit-type addition operation device has limitations in terms of processing time and efficiency for large-scale data. For example, when a required addition operation is performed by image processing or the like, the addition operation must be repeatedly performed one pixel or one line at a time, and the addition operation cannot be simultaneously performed on all image data of one frame. . Therefore, a considerable amount of calculation time is required as a whole. In addition, in a configuration in which the addition operation circuits for one line are arranged in parallel, the circuit scale increases.

An object of the present invention is to provide an addition operation device which enables simultaneous addition operation to large-scale data.

Another object of the present invention is to provide a semiconductor memory device having an addition operation function for implementing an addition operation using a memory array itself.

Another object of the present invention is to provide a dynamic RAM
It is an object of the present invention to provide a semiconductor memory device having an addition operation function that not only can perform data storage as an original function but also realizes an addition operation of data with a configuration to which a few circuit elements are added.

[0080]

In order to achieve the above-mentioned object, an addition operation device according to the present invention comprises a preset 2
Binary data supply means for supplying 1-bit binary data having any one of the values, and N pieces of binary data provided from the binary data supply means, and summing the sums First conversion means for converting into (N + 1) value data having any one of preset (N + 1) values, and a value of the (N + 1) value data generated by the addition means Second converting means for detecting and converting the detected value into binary data having a predetermined number of bits.

Further, another addition operation device according to the present invention is arranged so that any one of two predetermined quantization levels is used.
A binary parameter supply element for providing a 1-bit first electrical parameter having two values, and N (N is an integer of 2 or more) first electrical parameters provided by the binary parameter supply element. First conversion means for adding and summing the sum to a second electrical parameter having any one of predetermined (N + 1) values at a quantization level; and the addition means And a second conversion means for detecting the value of the second electrical parameter generated by the above and converting the detected value into binary data having a predetermined number of bits.

A semiconductor memory device with an addition operation function according to the present invention is connected to any one of bit lines and stores a plurality of binary-level charges corresponding to quantization information corresponding to binary information in bit units. Memory cells, a sense amplifier connected to each complementary bit line pair, and one or more common charges stored in the selected N (N is an integer of 2 or more) memory cells. Adding means for adding on the bit lines, generating a bit line potential of a quantization level (N + 1) having a voltage value corresponding to the sum of the charges on the bit line; Bit line potential supply means for separately applying via the bit lines respectively corresponding to the number of the sense amplifiers equal to the number of bits required for binary number display, and the bit line voltage supplied to the plurality of sense amplifiers Comparison reference voltage supply means for respectively providing a preset different comparison reference voltage for detection, and causing the plurality of sense amplifiers to detect the bit line potential based on the corresponding comparison reference voltages at predetermined timings. , Each of those sense amplifiers
And sense amplifier control means for obtaining binary data representing an added value by combining the value outputs.

In the above-mentioned semiconductor memory device, preferably, the adding means adds the common one or a plurality of the common memory cells before adding the electric charges respectively stored in the selected N memory cells. May be included in order to precharge the bit line of this type to a predetermined reference potential.

Preferably, prior to the addition means adding the electric charges respectively stored in the selected N memory cells, a part or all of the N memory cells are respectively added. And a storage charge copy unit for copying the stored charge of each of the storage cells to another predetermined memory cell.

Preferably, prior to the addition means adding the electric charges respectively stored in the selected N memory cells, the adding means may store the electric charges in a part of the N memory cells. It may include an inversion copy unit that logically inverts the electric charge and copies it to another predetermined memory cell.

Preferably, at least one of the selected N memory cells may store a charge representing carry data.

[0150] Preferably, the adding means includes a sum of electric charges stored in the selected N memory cells, a capacitance of each of the electric charges, a capacitance of the common one or a plurality of bit lines, respectively. The configuration may be such that a bit line potential having a value corresponding to the parasitic capacitance is generated.

Preferably, the bit line potential supply means may include a transistor connected between each bit line of the plurality of adjacent sense amplifiers.

Preferably, the sense amplifier control means performs a sensing operation by shifting a predetermined time to the plurality of sense amplifiers in ascending order of a digit of a binary output constituting the binary binary data. It may be configured to perform the operation.

Preferably, the comparison reference voltage supply means determines a comparison reference potential for the sense amplifier of the next lower digit in accordance with a binary output obtained from the sense amplifier of each upper digit. It may be.

Another semiconductor memory device having an addition operation function according to the present invention includes a plurality of semiconductor memory devices connected to any one of bit lines, which store binary-level binary charges corresponding to binary information in bit units. And the charges stored in the selected N (N is an integer of 2 or more) memory cells are added together on one common bit line, and a voltage value corresponding to the sum of the charge amounts is added. Adding means for generating, on the bit line, a bit line potential of a quantization level (N + 1) having the following expression: M (M is N in binary notation) connected in parallel to each complementary bit line pair (The required number of bits), bit line potential supply means for separately applying the bit line potential to the M sense amplifiers via the bit lines, and applying the bit line voltage to the M sense amplifiers. To detect Comparison reference voltage supply means for respectively providing different comparison reference voltages that have been set, and causing the M sense amplifiers to detect the bit line potentials at predetermined timings based on the corresponding comparison reference voltages. And sense amplifier control means for obtaining M-bit binary data representing an added value by combining the respective binary outputs of the amplifiers.

[0200]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

First, the basic principle of the present invention will be described with reference to FIGS. For example, two (n + 1) -bit binary data a (an... A1 a0) and b (bn... B1 b0)
In the present invention, as an example, as shown in FIG. 1, in the present invention, a quaternary or quaternary value is inserted between input bits (ax, bx, cix) and output bits (cox, sx) of each digit. An intermediate value e4x is introduced. The intermediate value e4x represents a value obtained by adding three input bits (ax, bx, cix) with equal weights in a quaternary number.

As a first step, each input bit (a
(x, bx, cix) is not a binary value (0/1) but a value on a quaternary number (0/1) and is added to obtain an intermediate value e4x of the quaternary number.

Next, as a second step, the intermediate value e4x of the quaternary number is converted to 2-bit binary data [e4x (MSB), e4x
(LSB)]. Here, the upper bit e4x (MSB) of the binary data matches the carry cox to the upper digit (x + 1), and the lower bit e4x (LSB) matches the sum sx of the digit (x). That is, the same operation result as that of a normal full adder is obtained.

FIG. 2 shows an example of the basic configuration of an addition operation device for realizing the above algorithm of the present invention.

As shown in FIG.
The two capacitors Ca, Cb, Cc are electrically connected to a common conductor DL via a switch, for example, a transistor switch SW.
It is connected to a voltage detection circuit 10 of a value detection type. Each capacitor Ca, Cb, Cc stores a predetermined charge Q in advance or hardly stores any charge. This corresponds to writing binary information 1 or 0, and the voltages Va, Vb, Vc of the capacitors Ca, Cb, Cc are set to predetermined charging voltage values (for example, 3 volts) or non-charging voltage values (for example, 0 volts).

When all the switches SW are closed at the same time, the electric charges stored in the respective capacitors Ca, Cb, Cc are added via the conductor DL. The potential Ve4 on the conductor DL is determined by ignoring the parasitic capacitance of the conductor DL, the sum Qt of the accumulated charges and the capacitors Ca, Cb, Cc.
And the voltage value determined by the capacitance. Since the capacitance is constant and the total sum Qt of the stored charges is four (0, Q, 2Q, 3Q) at the quantization level or the discrete level, the potential Ve4 on the lead DL is the value (Vt) when Qt is 0 (V
e4 (0)), the value when Qt is Q (Ve4 (1)), the value when Qt is 2Q (Ve4 (2)), Qt
Takes one of the values when V is 3Q (Ve4 (3)).

The voltage detection circuit 10 determines that the potential Ve4 on the lead line DL has four levels (Ve4 (0), Ve4 (1), Ve4 (2),
Ve4 (3)) may be detected or determined. This mechanism consists of three containers Ka, each containing only a predetermined volume Q or little liquid.
, Kb and Kc are graduated cylinders with 4-value scale
Is similar to reading the scale of the graduated cylinder 12.

The voltage detection circuit 10 converts the detection result into 2-bit binary data [Ve4 (MSB), Ve4 (LSB)].
]. That is, [0,0] is output when Ve4 (0) is detected, [0,1] is output when Ve4 (1) is detected, and [1,1] is output when Ve4 (2) is detected.
0] is output, and [1, 1] may be output when Ve4 (3) is detected. The upper bit Ve4 (MSB) of the 2-bit binary data corresponds to the carry cox to the upper digit (x + 1), and the lower bit Ve4 (LSB) corresponds to the sum sx of the digit (x).

FIG. 3 shows another basic configuration example of the addition operation device according to the present invention. In this method, three resistance paths Pa, Pb, and P can be used to select each resistance value to one of two predetermined values (R1, R2 in this example) in terms of a quantization level.
c is connected in parallel to the power supply voltage Vcc, and when the main switch SWM is closed, each of the current path circuits Pa, Pb, P
The four-value detection type current detection circuit 16 detects the total current Ie4, which is the sum of the currents Ia, Ib, and Ic flowing through c, using an appropriate current sensor 14. Here, the resistance value of the resistor R1 is, for example, 1 more than the resistance value of the resistor R0.
It is assumed to be about 000 times larger.

The setting switches SWa, SWb, SWc provided in each of the current path circuits Pa, Pb, Pc are switched to the left or right position in the figure according to the binary value (0/1). Each current Ia, Ib, I
c is a predetermined binary value in terms of quantization level (I0, I1)
Takes one of the following values. Therefore, the combined current Ie4 is obtained as a quantization level quaternary value [3I0, (2I0 + I
1), (I0 + 2I1), 3I1].

The current detection circuit 16 determines that the combined current Ie4 has four values [3I0, (2I0 + I1), (I0 + 2I1), 3I
1], and 2-bit binary data [Ie4 (MSB), Ie4 (LSB) representing the detection result.
] May be output.

As described above, the addition operation device of the present invention can use various electric parameters.

In the following embodiments, application examples in which the present invention is applied to a dynamic RAM (DRAM) will be described.

First, referring to FIG. 4 and FIG.
The basic principle in the case of realizing with a RAM will be described.

In the DRAM, one transistor and one transistor
Each memory cell MC including a plurality of capacitor cells (capacitors) is electrically connected to any one of bit lines BLi, and the bit line BLi is connected to a complementary bit line BLi.
A pair with i- is connected to one of the sense amplifiers S / A. In each memory cell MC, a transistor forms a switch, and a capacitor cell stores charge.

Therefore, as shown in FIG. 4, a configuration in which, for example, three memory cells MCa, MCb, MCc are electrically connected to sense amplifier S / A via common bit line BLi can be obtained. . Here, if the sense amplifier S / A is constituted by a quaternary detection type sense amplifier, one equivalent to the above-described addition operation device in FIG. 2 can be obtained. However, in the DRAM, the parasitic capacitance CB of the bit line BL is much larger than the capacitance Cs of the memory cell MC, so that it is necessary to add this parasitic capacitance CB to one of the circuit elements.

As in ordinary data storage in a DRAM, a predetermined amount of charge Q is stored in each of the memory cells MCa, MCb, and MCc when writing data “1”, and almost all charges are written when writing data “0”. Avoid accumulation. In terms of voltage level, data "1" corresponds to a fixed charging voltage VDD (for example, 3 volts), and data "0" corresponds to a non-charging voltage (for example, 0 volt).

As described above, the two binary data a, b
When performing the addition operation of each digit for each of the memory cells MCa, MC
The values of the binary input bits (ax, bx, cix) are previously written in b and MCc.

After the bit line pair BLi, BLi- is precharged to a normal reference voltage of 0.5 VDD (VDD is a power supply voltage), each corresponding word line Wa, Wb, W
c is activated and each of the memory cells MCa, MCb,
The charges stored in MCc are added via a common bit line BLi. Then, the potential Ve4 of the bit line BLi is calculated according to the following equations (1), (2),
Four types of voltage values Ve4 (0), Ve represented by (3) and (4)
The value takes one of e4 (1), Ve4 (2), and Ve4 (3).

Ve4 (0) = 0.5VDD {1-3Cs / (CB + 3Cs)} (1) Ve4 (1) = 0.5VDD {1-Cs / (CB + 3Cs)} (2) Ve4 (2) = 0.5VDD {1 + Cs / (CB + 3Cs)} (3) Ve4 (3) = 0.5VDD {1 + 3Cs / (CB + 3Cs)} (4)

From the above equations (1) to (4), 0 <Ve4 (0),
Ve4 (1) <0.5VDD, 0.5VDD <Ve4 (2), Ve4
(3) <There is a magnitude relation of VDD, more specifically 0 <
Ve4 (0) <0.5VDD ｛1-2Cs / (CB + 3Cs
)｝ <Ve4 (1) <0.5VDDD <Ve4 (2) <0.5VD
D {1 + 2Cs / (CB + 3Cs)} <Ve4 (3) <VDD
It can be seen that there is a magnitude relation of

Therefore, as the four-value detection type sense amplifier S / A in this embodiment, for example, a combination of a pair of two-value detection type sense amplifiers S / A1 and S / A2 as shown in FIG. 5 is employed. .

The first sense amplifier S / A1 receives a reference voltage Vref1 from the complementary bit line BLi- side of 0.5.
Give VDD. The sense amplifier S / A1 performs a normal binary detection and amplification operation and outputs binary data of "1" or "0" according to the magnitude relationship between the potential Ve4 of the bit line BLi and the comparison reference voltage Vref1. I do. More specifically, Ve4>
When 0.5 VDD, (VDD, 0) is output on BLi, BLi-, and when Ve4 <0.5 VDD, (0, VDD) is output on BLi, BLi-.

On the other hand, the second sense amplifier S / A 2 has:
When the detection result of the first sense amplifier S / A1 is "1" as the comparison reference voltage Vref2 from the complementary bit line BLi- side, 0.5VDD ｛1 + 2Cs / (CB + 3C
s)}, and when the detection result of S / A1 is "0", 0.5 VDD {1-2Cs / (CB + 3Cs)} is given.

This sense amplifier S / A 2 also performs a normal binary detection and amplification operation, and outputs “1” or “0” according to the magnitude relationship between the potential Ve 4 of the bit line BLi and the comparison reference voltage Vref 2. Output value data. More specifically, Ve4
> {1 + 2Cs / (CB + 3Cs)} or Ve4> {1
-2Cs / (CB + 3Cs)}, BLi, BLi-
Then, (VDD, 0) is output and Ve4 <41 + 2Cs / (C
B + 3Cs)} or Ve4 <{1-2Cs / (CB + 3)
(Cs)}, (0, VDD) is output on BLi and BLi-.

As a result, the sense amplifiers S / A1 and S / A
From FIG. 2, when Ve4 (0) is detected, (0,0), Ve4 (0)
When (1) is detected, (0,1), when Ve4 (2) is detected, (1,0), and when Ve4 (3) is detected, (1,1), two bits 2 Hexadecimal data [Ve4 (MSB), Ve4
(LSB)] is obtained.

Similarly to the above, the upper bit Ve4 (MSB) of the 2-bit binary data is set as the carry cox to the upper digit (x + 1), and the lower bit V4e (LSB) is set as the sum sx of the digit (x). be able to.

Next, the configuration and operation of a specific example of the DRAM with the addition operation function according to this embodiment will be described with reference to FIGS.

FIG. 6 shows a circuit configuration of a main part of a DRAM with an addition operation function in this embodiment. In this DRAM, a memory cell array, a memory cell M in the array,
Basic elements such as C, word line W, bit lines BLi, BLi-, and sense amplifier S / A have a normal configuration. Transfer gates (T16, T17, T26, T27) provided on each bit line BLi, BLi- for selectively conducting / cutting off each sense amplifier S / A and the memory array are also conventional means.

The characteristic configuration is between a pair of adjacent sense amplifiers S / A1 and S / A2 and the memory cell array (FIG. 6).
In the example of (1), temporary memory cells MC01, for addition operation are added to transfer gates T16, T17, T26, and T27).
MC02, MC11, MC12, MC13, MC21, MC22, M
C23 and transistors T03, T04, T14, T15, T2
4, T25 is added.

More specifically, two temporary memory cells MC12 and MC12 are connected between bit line BL1 and ground potential.
13 are connected in parallel. A transistor T14 is connected between the connection point of the transistor T13 and the capacitor C13 of the MC13 and the ground potential.

[0520] Two temporary memory cells MC11 and MC01 are connected between the bit line BL2 and the ground potential. A transistor T03 is connected between a connection point between the transistor T01 and the capacitor C01 of the MC01 and the bit line BL1-. The transistor T15 is connected between the bit lines BL1 and BL2.

[0531] Two temporary memory cells MC22 and MC23 are connected in parallel between the bit line BL1- and the ground potential. MC23 transistor T23 and capacitor C
The transistor T24 is connected between the connection point 23 and the ground potential.

[0537] Two temporary memory cells MC21 and MC02 are connected in parallel between the bit line BL2- and the ground potential. MC02 transistor T02 and capacitor C
The transistor T is connected between the connection point of the bit line BL2 and the bit line BL1.
04 is connected. A transistor T25 is connected between the bit lines BL2 and BL2-.

Each transistor T has a sequence control unit 2
0 (FIG. 9) provides a required control signal φ. More specifically, the transfer gates T on the bit lines BL1 and BL2
17 and T16 are given φ1. The transistor T15 is supplied with φ2. Temporary memory cells MC11, M
Φ3 is given to each of the transistors T11 and T12 of C12. Φ4 is given to the transistor T13 of the temporary memory cell MC13. The transistor T14 has φ
5 is given. Φ6 is applied to the transistor T01 of the temporary memory cell MC01. Transistor T03
Is given φ7.

The transistor T04 is supplied with φ8.
Φ9 is applied to the transistor T02 of the temporary memory cell MC02. Φ10 is given to the transistor T24. Transistor T23 of temporary memory cell MC23
Is given φ11. The temporary memory cells MC21,
Φ12 is given to each of the transistors T21 and T22 of the MC22. Φ13 is given to the transistor T25. Φ14 is given to the transfer gates T26 and T27.

The sequence control unit 20 receives a command CD1 for normal data writing / reading from a memory control logic unit (not shown) and the like, a command CD2 for addition operation in this embodiment, and the like. A clock CK is input from a circuit (not shown), and the above-described various control signals φ are generated at a predetermined sequence and timing.

FIG. 7 shows sense amplifiers S / A (S / A 1,
S / A2) is shown. This sense amplifier S / A
Is activated by a pair of complementary control signals φA, φA− from the sequence control unit 20, inputs the potentials on the complementary bit line pair BL, BL−, detects the difference between them, and detects the power supply voltage VDD. , And a binary detection type differential amplifier that amplifies to the level of the ground potential.

Although not shown in FIG. 6, in the vicinity of each sense amplifier S / A or outside the memory cell array, for example, a precharge circuit 2 having a circuit configuration as shown in FIG.
2 are provided. The precharge power supply line 24 is connected to a precharge power supply circuit (not shown).

The sequence controller 20 sets the control signal φP to H
When activated to the level, the precharge transistor T
P1 and TP2 and the equalizing transistor TP3 become conductive, respectively, so that the pair of bit lines BLi and BLi- is precharged to the voltage level (0.5 VDD) of the precharge reference voltage VP from the precharge power supply circuit. .

In FIG. 6, each sense amplifier S / Ai
Are selectively selected by a Y address selection signal YSi from a Y address decoder (not shown). When selected, the input / output of the sense amplifier S / Ai, that is, the bit line pair BLi, BLi- is connected to the data input / output lines I / O, I / O.
-Connected to.

Next, in this DRAM, two (n + 1) -bit binary data A (An
... A1 A0) and B (An... A1 A0) will be described. 11 to 21 referred to in the following description, the Y address select line YS and the data input / output lines I / O and I / O- are omitted for ease of illustration.

First, prior to executing the addition operation, DRA
In the normal write mode at M, the binary data A and B to be added are stored in appropriate memory cells MC in the memory cell array.

For example, as shown in FIG. 11, bits Bn... B1 B0 of addend data B are stored in bit line BL1 and bits An... A1 A0 of addend data A are stored in bit line BL2. Store. Here, it is important to write the bits of the same digit in both data A and B to the memory cells MC on the same word line W. In a normal DRAM operation such as this data storage processing, the control signals φ2 to φ13 for the addition operation are set to the inactive state (L level).
Fixed to.

FIG. 12 shows the first step of the addition operation. The addition starts from the least significant bits A0 and B0.

First, two memory cells M in the memory cell array storing the least significant bits A0 and B0, respectively.
Select the word line W0 commonly connected to C and MC,
The sense amplifiers S / A1 and S / A2 sense the contents of the least significant bits A0 and B0 via the bit lines BL1 and BL2 by a normal DRAM reading procedure. At this time, the control signals φ1 and φ14 are set to the H level,
Each transfer gate T16, T17, T26, T27 is made conductive, and the memory cell array and the sense amplifiers S / A1, S / A
2 is electrically connected.

When the sensing operation of the sense amplifiers S / A1 and S / A2 is completed, the control signal φ3 is activated to an H level, and the contents of the least significant bits A0 and B0 are written to the temporary memory cells MC11 and MC12, respectively. This means that the contents of the least significant bits A0 and B0 have been copied from the memory cells MC and MC in the memory cell array to the temporary memory cells MC11 and MC12, respectively.

At the point in time when this copy operation is completed, control signal φ3 is returned to the L level, and temporary memory cell MC
11 and MC12 are electrically disconnected from the bit lines BL1 and BL2, respectively, and the copy contents are stored. Further, the operations of both sense amplifiers S / A1 and S / A2 are stopped, and the word line W
Return 0 to L level. This means that the copy source information (A0, B0) has been rewritten in the memory cell array.

[0690] On the other hand, the control signal φ5 is set to the H level to turn on the transistor T14, and the temporary memory cell MC
13 is written with binary data “0”. This binary data "0" is used for the input carry of the least significant digit operation.

After the copy operation, the precharge circuit 22 shown in FIG. 8 is activated to activate each bit line pair (BL1, BL1).
-), (BL2, BL2-) are precharged to a reference voltage of 0.5 VDD.

Next, as shown in FIG. 13, the control signal φ12 is activated to the H level under the precharge state, and the precharge reference voltage 0.5VDD is written to the temporary memory cells MC21 and MC22. Immediately after that, the control signal φ2
, Φ13 are activated (H level) and the transistor T1
5, T25 is made conductive, and the bit lines BL1, BL2 are connected to each other and BL1-, BL2- are connected to each other in a short-circuit state.

[0720] Immediately before the end of the precharge, the control signals φ1 and φ14 are returned to the L level and the transfer gate T
16, T17, T26, and T27 are turned off. As a result, the memory cell array is electrically disconnected from the sense amplifier S / A in the subsequent operation.

After the completion of the precharge, control signal φ
3. Activate φ4 to H level. FIG. 14 shows this state clearly as an electric network. This is equivalent or equivalent to the electrical network of FIG. Therefore, the same truth table and equations (1) to (4) as in FIG. 4 apply, and a potential Vdata having the same quantization level value as potential Ve4 in FIG. 4 is obtained on bit lines BL1 and BL2. In addition,
At this point, the sense amplifier S / A1 has not been activated yet.

Next, as shown in FIG. 15, the control signal φ2
, Φ13 are returned to the L level to turn off the transistors T15 and T25, and the bit lines BL1 and BL2 and BL
1- and BL2- are electrically separated from each other. Even after this separation, the potential of each bit line BL does not fluctuate because it is in a high impedance state. That is,
The potential Vdata on the bit lines BL1 and BL2 maintains the same voltage value as before, and the potentials on the bit lines BL1- and BL2- maintain the reference voltage (0.5 VDD).

[0750] Here, the sense amplifier S / A1 is activated. The sense amplifier S / A1 is connected to the potential V on the bit line BL1.
Data and reference voltage (0.5VDD) on complementary bit line BL1-
And amplify by detecting the voltage difference between. That is, Vdata
> 0.5VDD (that is, Vdata (2) or Vdata
In (3)), a voltage of the VDD level is output on the bit line BL1, and a voltage of the ground potential VGND is output on the bit line BL1-. When Vdata <0.5VDD (that is, Vdata
data (0) or Vdata (1)) outputs the voltage of the ground potential VGND on the bit line BL1 and outputs the voltage of the VDD level on the bit line BL1-.

FIG. 16 shows an electric circuit network around the sense amplifier S / A1 when performing the sensing operation as described above. As will be understood, the binary voltage (VDD / VGND) obtained on the bit line BL1 by the sensing operation of the sense amplifier S / A1 represents the carry output Co as a result of the addition operation of the least significant bits A0 and B0.

[0770] Even if the sense amplifier S / A1 operates, the potentials on the bit lines BL2 and BL2- are not affected at all, and the voltage values Vdata and 0.5VDD up to that time are maintained, respectively.

[0780] Before and after the sensing operation of the sense amplifier S / A1, the control signals φ7 and φ8 are activated to the H level to turn on the transistors T03 and T04, respectively, and the sensing information of the sense amplifier S / A1 is stored in the temporary memory cell M.
Write to C01 and MC02.

[0790] That is, when the sense amplifier S / A1 detects Vdata (2) or Vdata (3) on the bit line BL1, and outputs VDD and VGND on the bit lines BL1 and BL1-, respectively, the temporary memory cell Bit line B on MC01
The voltage VGND on L1- is written and the voltage VDD on the bit line BL1 is written to the temporary memory cell MC02.
(Carry output Co = “1”) is written.

Also, sense amplifier S / A1 is connected to bit line B
When Vdata (0) or Vdata (1) is detected on L1 and VGND and VDD are output on the bit lines BL1 and BL1-, respectively, the bit line BL is transferred to the temporary memory cell MC01.
In addition to the writing of the voltage VDD above, the voltage VGND (carry output Co = "0") on the bit line BL1 is written to the temporary memory cell MC02.

[0811] However, both temporary memory cells MC
Of MC01 and MC02, only MC02 that copies carry output Co is effective in this embodiment.
MC01 does not function substantially.

[0820] Also, the control signals φ3 and φ4 are activated (H level).
Level), the carry output C on the bit line BL1 is also applied to the temporary memory cells MC12 and MC13.
The binary voltage of o (VDD / VGND) is copied. This copy is significant for the carry storage MC13. M
The data copied to C12 is replaced with other information in a later operation. At this time, the sense amplifier S / A2 has not been activated yet.

[0832] When the copy of carry output Co (VDD / VGND) to temporary memory cell MC02 is completed as described above, control signals φ7, φ are output as shown in FIG.
8 is returned to the L level to shut off the transistors T03 and T04.

[1045] Then, the control signal φ9 is activated to an H level, and both temporary memory cells MC are activated on the bit line BL2-.
02 and the electric charges stored in MC21 are added together.

FIG. 18 shows the state at this time as an electric circuit network. The potential Vdata on the bit line BL2, which is one differential input of the sense amplifier S / A1, maintains the voltage value in the state of FIG. 14, that is, one of Vdata (0) to Vdata (3). However, the potential Vref2 on the bit line BL2- which is the other differential input is equal to the carry output Co (VDD / VGN) stored in the temporary memory cell MC02.
According to D), the voltage shifts to a voltage value represented by either of the following equations (5) or (6).

[0859] That is, when carry output Co is 1 (VDD), Vref2 = 0.5VDD {1 + 2Cs / (CB + 3Cs)} (5)

When carry output Co is 0 (VGND), Vref2 = 0.5VDD {1-2Cs / (CB + 3Cs)} (6)

FIG. 19 shows the derivation of these equations (5) and (6). The capacitance of the capacitor cells C02 and C21 of the temporary memory cells MC02 and MC21 connected to the bit line BL2- of the reference voltage supply circuit is selected to a predetermined value for obtaining the reference voltage Vref2. In this embodiment, for example, C02 = Cs and C21 = Cs / 2.

[0890] In FIG. 17 again, the sense amplifier S / A2 is activated immediately after the activation of the control signal φ9 as described above.

When carry output Co is 1 (VDD), sense amplifier S / A2 outputs potential V on bit line BL2.
data (Vdata (2) or Vdata (3)) and complementary bit line B
A voltage difference between the reference voltage Vref2 (5) on L2- is detected and amplified.

[0910] That is, when Vdata> Vref2 (5) (that is, when Vdata (3)), the voltage VDD is output on the bit line BL2, and the voltage VGND is output on the bit line BL2-. When Vdata <Vref2 (5) (that is, Vdata
In (2)), the voltage VGND is output on the bit line BL2, and the voltage VDD is output on the bit line BL2-.

[0920] When carry output Co is 0 (VGND), sense amplifier S / A2 outputs potential V on bit line BL2.
data (Vdata (0) or Vdata (1)) and complementary bit line B
The voltage difference between the reference voltage Vref2 (6) on L2- and the voltage difference is detected and amplified.

[0930] That is, when Vdata> Vref2 (6) (that is, when Vdata (1)), the voltage VDD is output on the bit line BL2, and the voltage VGND is output on the bit line BL2-. When Vdata <Vref2 (6) (that is, Vdata
(0), the voltage VGND is output on the bit line BL2, and the voltage VDD is output on the bit line BL2-.

[0939] Thus, the binary voltage (VDD / VGND) obtained on the bit line BL2 by the sensing operation of the sense amplifier S / A2 represents the sum S0 of the addition operation result of the least significant bits A0 and B0. Note that the potential on the bit line BL1 is the carry output C of the addition operation result of the least significant bits A0 and B0.
A binary voltage (VDD / VGND) representing 0 is maintained.

As a result, the result of the addition operation on the least significant bits A0 and B0 is converted into binary data ((Co, So)) as both sense amplifiers S / A1, S / A2 or both bit line pairs B (BL1, BL1-). , (BL2, BL2-).

Next, the binary data (Co
, So) are stored at appropriate locations in the memory cell array. For example, as shown in FIG.
By activating the word line WO and the word line WO, the least significant bits A0 and B0 to be added may be overwritten and stored in the memory cell MC. If the original data A0 and B0 are to be stored, they may be written to another memory cell MC. It is also possible to read data (Co, So) to the outside of the memory via the data input / output lines I / O, I / O-.

[0970] The addition operation for the least significant bits A0 and B0 is thus completed. Next, the second lowest (second
The same processing as described above is repeated for bits A1 and B1 of (digit).

[0980] That is, in the first step, the operation target bits A1 and A1 stored in the corresponding memory cells MC and MC in the memory cell array are processed in the same procedure as described above.
The contents of B1 are copied to temporary memory cells MC11 and MC12, respectively.

[0990] However, as shown in FIG.
5 is fixed at the L level (inactivation level). As a result, carry output Co stored in temporary memory cell MC13 in the preceding (lower digit) addition operation is used as carry input C1 in the present addition operation. Subsequent processing is performed in the same sequence as in the above-described addition operation of the least significant bit.

In the above operation, the procedure for once writing the data to be added to the memory cell array and then performing the addition operation has been described.

[1010] However, it is also possible to execute the addition operation simultaneously with the data writing. In this case, at the same time that the corresponding word line W is activated in the memory cell array, the control signal φ3 is also activated so that the data to be written in the memory cell array is temporarily stored in the temporary memory cells MC11 and MC11.
Also write to MC12. In the addition operation of the least significant bit, the control signal φ5 is activated to the H level in the same manner as described above, and the data “0” is written to the temporary memory cell MC13.

[1020] Then, after the data writing to the memory cell array is completed, the control signals φ1, φ14 are returned to L level to shut off the transfer gates T16, T17, T26, T27, and the memory array is disconnected from the addition operation unit. After that, the addition operation may be performed in the same sequence as described above.

Next, an embodiment in which not only addition operation but also subtraction operation can be performed in this DRAM will be described.

The subtraction in a binary number is accomplished by calculating the two's complement value of the subtrahend and adding the two's complement value of the subtrahend and the subtrahend.

The two's complement of a binary number is obtained by logically inverting all bits of the binary number and adding 1 to the value generated by the inversion operation. For example, to obtain the two's complement of an 8-bit binary number [01011010], all bits are first inverted. By this operation, a binary number [10100101] is obtained. The number [10100110] obtained by adding 1 to this number is the 2's complement value of the original number.

[1060] FIG. 22 shows a configuration of a main part of the DRAM according to this embodiment. In this embodiment, independent control signals φ31, φ32, φ121, φ122 are applied to the temporary memory cells MC11, MC12, MC21, MC22, respectively. Also,
The other terminals of the transistors T14 and T24 connected to the temporary memory cells MC13 and MC23 are supplied with a control signal φ15 instead of the ground potential. The other parts have the same configuration as the above-described addition operation circuit.

However, in this embodiment, both temporary memory cells MC11 and MC12 may be selected by the same control signal φ. In fact, the control signal φ121
, Φ122 are controlled only at the same timing, and may be the same control signal φ. A separate control signal φ
The reason why they are set to 121 and φ122 is to provide a configuration in which opposite control signals φ31 and φ32 on the opposite side of the sense amplifier are used to easily realize layout symmetry of the sense amplifier portion.

In the subtraction operation, data (A, B) necessary for the operation is previously written in an appropriate place in the memory cell array in a normal DRAM write mode. In this case, of the control signals φ, φ2, φ31, φ32, φ4, φ5
, Φ6, φ7, φ8, φ9, φ10, φ11, φ121, φ1
22, φ13 and 15 are kept inactive (L level)
If φ1 and φ14 are activated to the H level to make the transfer gates T16, T17, T26 and T27 conductive, the normal DRA
Since it becomes M, data writing is performed in that state.

In the first step of the subtraction operation, the least significant bit A0 of the minuend (A in this example) is copied to the temporary memory cell MC11. At the same time, the least significant bit of the two's complement of the subtraction (B) is generated.

[1100] In FIG. 23, the elements and control signals activated in this step are shown by solid lines. First, the word line W0 is activated, and the least significant bits A0 and B0 of the minuend A and the subtrahend B are activated.
Is read out to the sense amplifiers S / A1 and S / A2 via the bit lines BL1 and BL2, respectively.
A1 and S / A2 sense binary data A0 and B0. Thereafter, control signals φ31, φ7, φ8 are activated to H level. At the same time, the control signals φ5, φ10, φ15 are also activated to the H level.

[1110] Of course, φ8 and φ10 may be kept at L level. In this example, the control signals φ7, φ7
In order to balance with 15, φ8 and φ10 are also activated.

By the above operation, the least significant bit A0 of the minuend A stored in the memory cell array is copied to the temporary memory cell MC11 via the sense amplifier S / A2. On the other hand, the least significant bit B0 of the decrement B is read by the sense amplifier S / A1, and the bit-inverted value B0- obtained on the bit line BL1- is written to the temporary memory cell MC01.

[1130] Note that B read on bit line BL1 is
The data of 0 is written to the temporary memory cell MC02, but this value is not used. Therefore, this writing need not be performed.

[1140] When the control signals φ5 and φ15 both become H level as described above, the temporary memory cell M
Data "1" is written to C13. Therefore, the sum of the data of the two temporary memory cells MC01 and MC13 is the least significant bit of the 2's complement of the decrement B. This completes the preparation of the least significant bit required for subtraction.

Next, the control signals φ1 and φ14 are returned to L level to disconnect the memory cell array from the addition operation circuit.
Then, after returning the control signals φ31, φ7, φ8 to the L level, the bit line pairs (BL1, BL1-), (BL2, B
L2-) and the sense amplifiers S / A1 and S / A2 are 0.5
Precharge to VDD. The control signals φ5 and φ10 are returned to the L level before the start of the subsequent subtraction operation.

Next, the subtraction operation of the least significant bit is started. That is, the least significant bit A0 of the minuend A and the least significant bit of the two's complement of the subtrahend B are added. 24, 25,
26 and 27 show a series of operations of this addition operation. The principle of the addition operation and the operation procedure are the same as those of the above-described addition operation, and a detailed description thereof will be omitted.

[1170] The subtraction of the bit next to the least significant bit (the second digit) is basically the same as the operation of the least significant bit. However, when generating the two's complement of the decrement, the data of "1" is stored in the temporary memory cell MC in the least significant bit.
However, since it is not necessary to add “1” to bits other than the least significant bit, the operation of writing “1” data to the temporary memory cell MC13 is not performed.

Also, as a result of the addition operation of the least significant bit A0 of the minuend A and the least significant bit of the 2's complement of the subtrahend B, both sense amplifiers S / A1, S / A
Binary carry information Co and sum (sum) information So are obtained from A2. Carry information Co is required for the next upper bit subtraction operation. Conveniently, as shown in FIG. 28, the temporary memory cell MC13 can be used as a temporary holding element of the carry information Co as in the case of the addition operation in the above embodiment.

In this embodiment, the parallel operation is not performed in the bit depth direction of the data, but the data is fetched into the DRAM collectively, and the 1-bit addition (subtraction) operation as described above is performed in all of the DRAM. Can be performed at the same time. For example, if there are 4000 sets of sense amplifiers (S / A1, S / A2) in the DRAM, 4000 1-bit full addition (subtraction) operations can be executed at a time.

Such a batch operation is advantageous for performing, for example, filtering, interpolation, and motion detection on image data for one frame in image processing.

In the embodiment described above, the addition operation unit is provided inside the transfer gates T16, T17, T26, and T27. These transfer gates are not required in principle. However, during the addition operation, these transfer gates can be turned off to electrically disconnect the bit lines in the memory cell array from the addition operation unit. Thereby, the bit lines BL1, BL1-, BL used in the addition operation
2, the length of the effective portion of BL2- can be shortened and the bit line capacitance load (parasitic capacitance CB) can be reduced, so that the arithmetic operation can be performed at a high speed and the power consumption required for charging the capacitance load can be reduced. There is.

In the above embodiment, the sense amplifier constituting the addition operation section is constituted by a pair of adjacent sense amplifiers S / A1 and S / A2 in a normal DRAM. For this reason, it is not necessary to increase the circuit area of the sense amplifier unit when adding the addition operation function, and the efficiency is good in terms of design / manufacturing and operation.

Also, as described above, when data (A, B) necessary for the operation is stored in the memory cell array, bits of the same digit are written into the memory cells connected to the same word line W. I can put it. And
By selecting the same word line W, those bits can be read out at the same time, and can be simultaneously copied to a predetermined temporary memory cell MC of the addition operation unit via both sense amplifiers S / A1 and S / A2.

Further, among the temporary memory cells MC in the addition operation unit in the above embodiment, MC11, MC1
2, MC13, MC21, MC22, and MC23 can be omitted, and their functions can be substituted for the memory cells in the memory cell array.

Although the area of the sense amplifier portion is doubled as compared with a normal DRAM, for example, as shown in FIG. 29, the four-value detection type sense amplifiers (S / A1, S / A2) to one bit line pair (BLi,
BLi-) can be assigned.

Also in the configuration of FIG. 29, MC11, MC12, MC out of temporary memory cells MC of the addition operation unit
13, MC21, MC22, and MC23 can be omitted, and their functions can be substituted for the memory cells in the memory cell array.

Also, the four-value detection type sense amplifiers (S / A1, S / A2) are connected to one bit line pair (BLi).
, BLi-) in the memory cell array, the bit of the binary data A of the augend (subtracted) and the bit of the binary data B of the augend (subtracted) are the same in the memory cell array. The charges are stored in the memory cells on the line, and the accumulated charges of the three memory cells MC are added on the same bit line BLi as shown in FIG. 5 during the addition operation.

The following is a description of a data address allocation method in this type of DRAM with reference to FIGS. For simplicity of explanation, it is assumed that both the augend data A and the addend data B have a 3-bit width, and each of them is a data group consisting of eight continuous data.

FIG. 30 shows the arrangement of each data bit stored in the memory before the addition operation. Here, in A (b, t), b indicates a bit position (numbered 0, 1, 2 from the lower bit to the upper bit), and t indicates the order in the data group. Is shown. The same applies to B (b, t). C (x, t) is used for the purpose of temporarily storing the carry information of the addition operation.

The X-decoder 30 normally selects (activates) one (row) word line specified by the row address information. The word line of a row can be selected (activated). The Y decoder 32 functions to connect one sense amplifier S / A (i) specified by the column address information to the data input / output line. The sense amplifier S / A (i) in each column is provided with a pair of sense amplifiers S / A as described above.
A1 and S / A2.

The addition operation is performed one bit at a time for each memory operation cycle sequentially from the least significant bit as described above. One memory operation cycle is basically the same as a normal DRAM 1-bit read cycle.

As in the above-described embodiment, A (b, t) and B (b, t) are previously written in the memory cell array in the normal DRAM write mode. C (x,
t) are all set to “0”.

First, the least significant bit is added in the first memory operation cycle. Therefore, as shown in FIG. 31, three rows of the least significant bits A (0, t) and B (0, t) and the carry bit C (x, t) are simultaneously selected, and the above-described addition operation is performed. Execute. The sum information So obtained as a result of this operation is A (0, t) and / or
Or B (0, t), carry information Co is C (x,
Each is written back at t).

In the second memory operation cycle, as shown in FIG. 32, the second lowest bit A
(1, t), B (1, t) and carry bit C
The three rows of (0, t) are simultaneously selected and the same addition operation as described above is executed. Then, the sum information S1 obtained by the operation is converted to A (1, t) and / or B (1, t).
Then, the carry information C1 is written back to C (0, t).

In the third memory operation cycle, the third (most significant) bit A as shown in FIG.
(2, t), B (2, t) and carry bit C
The three rows of (1, t) are simultaneously selected and the above-described addition operation is executed. Then, the sum information S2 obtained by the operation is converted to A (2, t) and / or B (2,2).
At t), the carry information C2 is written back to C (1, t).

Therefore, as shown in FIG. 34, the final addition operation result data (S2S1S0 + C2) is stored at each corresponding position in the memory array. These operation result data can be read in a read mode in a normal DRAM.

In this method, a plurality of words (rows) must be selected during the addition operation as described above. The word storing the carry information C (Wc) must be selected in every cycle. Further, when the carry information C and the sum information S are to be written back after the calculation result, the timings of the two must be shifted.

Therefore, a control circuit for controlling on / off of carry word line Wc independently of other word lines W may be provided. In addition, there are many examples of circuits that enable selection of two word lines only during an arithmetic operation.

FIG. 35 shows one of the simplest examples. In this method, the control signal SEL is multiplexed on the least significant bits X0 and X0- of the X address signal input to the X decoder. The X decoder 30 'operates as a normal decoder for designating one word line when SEL is "0", and as a decoder for simultaneously selecting two consecutive word lines when SEL is "1". Operate. The control signal Carry for selecting the word line Wc for carry C is separately provided.

In the above embodiment, the binary information (0/1)
Is performed by quaternary processing (binary → 4 → binary).

However, as understood from the above description, the principle of the present invention is not limited to four-value processing, for example, eight-value processing (binary → four-value → binary), 16-value processing ( (2 values → 16 values → 2 values) is also possible, or 10 values
It can also be realized by value processing (binary → 10 → binary). In the present invention, a binary addition operation is a performance target, and quaternary values, octal values, and the like are only treated as values during intermediate processing of the addition operation.

Hereinafter, the octal processing will be described. In the numerical representation, the weight of each digit is a power of two. Therefore, for example, in octal processing, a one-digit numerical value "7"
Is obtained as a calculation result, if this is converted into a binary number, it becomes "111" and becomes a three-digit numerical value. When viewed as a binary addition operation, "1" at the right end of "111"
Indicates the number of the digit, the middle "1" indicates that there is a carry to the next upper digit, and the leftmost "1" indicates that there is a carry to the next higher digit. I have.

[1430] As a specific example, binary numbers V, W, X,
There are Y and Z, V = 10, W = 11, X = 01, Y =
01, Z = 11.

It is assumed that the addition operation of these five numbers is performed through octal processing to obtain a binary number (binary number) result. First, the sum of the minimum digits of the given five numbers is obtained as follows. V (LSB) + W (LSB) + X (LSB) + Y (LSB) + Z (LSB) = 0 + 1 + 1 + 1 + 1 = 4 (octal number) = 100 (binary number) (7)

When the sum of the next digit is obtained ignoring the carry from the lower digit, the result is as follows. ^{V (2 nd LSB) + W} (2 nd LSB) + X (2 nd (LSB) + Y (2 nd (LSB) + Z (2 nd (LSB) = 1 + 1 + 0 + 0 + 1 = 3 (8 decimal) = 011 (binary) .... …… (8)

From the result of the above equation (7), the least significant digit of the result of addition of these five numerical values is "0" in binary notation. Since there is no carry to the next upper digit from the result of the above equation (7), the rightmost numerical value “1” in the result of the above equation (8) becomes the second lower digit of the addition operation result, Becomes "1" in decimal notation.

Since the leftmost value is "1" in the result of equation (7), there is a carry to the next upper digit (that is, the third lower digit). Considering these, the third and fourth lower digits of the addition operation result are "0" and "1", respectively.

Therefore, the finally obtained addition result is "1010" in binary notation.

[1490] As can be understood from the above description, when eight values (octal number) are used in the addition operation processing, carry propagation extends to the upper two digits of the next upper digit and the next (2nd) higher digit. . 16
In the case of a value, carry propagation extends to the upper three digits.

In the addition operation of binary information, when octal processing is employed in the intermediate processing of the operation, a maximum of five pieces of numerical information can be simultaneously added.

Since each piece of numerical information is given by a binary number, one digit takes a value of either “0” or “1”.
For example, in the addition operation of eight pieces of numerical information, the smallest possible value in each digit is 0 in decimal notation when all are "0", and the largest possible value is 8 in decimal notation when it is all "1". is there. When the intermediate values (1 to 7) are included, a nine-value state can be obtained. In octal processing, control in the octal state is most efficient, so the simultaneous operation is preferably performed with seven pieces of numerical information. In addition, since the carry information may propagate from the lower two digits as described above, the simultaneous calculation is ultimately performed by inputting five pieces of numerical information and two pieces of carry information.

As can be easily understood, the simultaneous operation in the case of 16 values is performed by inputting 12 numerical information and inputting 3 carry information.

FIG. 36 shows an algorithm for simultaneously adding five pieces of numerical information in 3-bit or 3-digit octal processing. a1, a2, a3, a4, and a5 are five numerical information inputs. Of the least significant digit co2 ₀ is a carry signal to the next significant digit, co1 ₁ is a carry signal to the next of the next significant digit. The third digit co1 ₃ is without the signal to the next next higher digit, while the signal to the next digit, use to become mathematically synonymous if weighting (x2) at the next digit input are doing.

FIG. 37 shows an algorithm of the addition operation when the same weighting as described above is applied to all the digits.

FIG. 38 shows a specific example of an 8-level detection type sense amplifier circuit. In this example, of the temporary memory cells, data in the memory cell array is copied,
A cell for temporarily holding carry information is omitted. The illustrated transfer gates T13, T14, T15, T23,
T24 and T25 can also be omitted. In the following description, control signals φ1 and φ12 are fixed in an active state (H level).

This eight-level detection type sense amplifier circuit comprises three adjacent sense amplifiers S / A in a normal DRAM.
1, S / A2 and S / A3.

The operation is basically the same as the four-value detection type of the above embodiment. From the seven memory cells in a memory cell array (not shown), binary charges of a quantization level corresponding to seven pieces of binary information (including carry information) are respectively stored on bit lines BL1, BL2, BL3. Read out. At this time, the control signals φ2 and φ3 are set to H level in advance, and the transistors T12 and T11 are turned on.

Thus, each bit line BL1, BL2,.
Each sense amplifier S / A1, S / A2, S
One of the eight potentials Vb8 (0) to Vb8 (7) of the preset quantization level is transmitted equally to one (left side) differential input terminal of / A3.

At this point, each of the sense amplifiers S / A1, S
The other (left side) differential input terminal of / A2 and S / A3 is supplied with a predetermined reference voltage of 0.5 VDD. The control signals φ10 and φ11 are also set to H level in advance, and the transistor T
Needless to say, the transistors 21 and T22 are kept conductive.
The control signals φ6 and φ7 are activated to H level, and the control signals φ4, φ5, φ8 and φ9 are set to L level.

Next, after setting φ3 and φ10 to L level, respectively, the sense amplifier S / A1 is activated to detect whether the eight-level potential Vb8 on the bit line BL1 is higher or lower than 0.5 VDD. . That is, the detection of the MSB (carry bit to the upper two digits) is performed.

By the sensing operation of the sense amplifier S / A1, the bit line pair BL1 and BL1- are complementarily driven to the level of VDD and the ground potential VGND. at this point,
The potentials on the bit lines BL2 and BL3 are maintained at the eight-level potential Vb8. Further, the potentials on the respective complementary bit lines BL2- and BL3- are also maintained at the reference voltage 0.5VDD.

The binary information (VDD / VGND) obtained by the sensing operation of the sense amplifier S / A1 is written to the temporary memory cell MC02 via the transistor T04.

Next, when φ8 is activated to the H level, the reference voltage Vref1 in the sense amplifiers S / A2 and S / A3 is set.
Is adjusted to a value Vref2 reflecting the sensing result of the sense amplifier S / A1. As shown in FIG.
ref2 is 1/4 or 3 of octal potential Vb8 (0) to Vb8 (7).
/ 4 position (level). To obtain this reference voltage Vref2, the capacitance of the capacitor cell C02 of the temporary memory cell MC02 is selected to a predetermined value.

Thereafter, φ2 and φ11 are set to the L level, and the sense amplifier S / A2 is activated to set the bit line BL.
2 to detect whether the upper potential Vb8 is higher or lower than the adjusted reference voltage Vref2. That is, the second MSB (1
The carry bit to the upper digit is detected.

In this case, the bit line pair BL2 and BL2- are driven complementarily to the levels of VDD and VGND by the sensing operation of the sense amplifier S / A2, but the potential on the bit line BL3 is changed to the octal potential Vb8. , And the potential on the bit line BL3- is maintained at the reference voltage (1/4 or 3/4 level of 8 values).

The binary information (VDD / VGND) obtained by the sensing operation of sense amplifier S / A2 is written to temporary memory cell MC06 via transistor T08.

Next, when φ9 is activated to the H level, the reference voltage Vref2 in the sense amplifier S / A3 is adjusted to a value Vref3 reflecting the sensing result of the sense amplifier S / A2. As shown in FIG. 39, Vref3 is an eight-level potential Vb8
(0) to 1/8, 3/8, 5/8 or 7 / of Vb8 (7)
8 (position). To obtain the reference voltage Vref3, the capacitance of the capacitor cell C06 of the temporary memory cell MC06 is selected to a predetermined value.

Thereafter, the sense amplifier S / A3 is activated to detect whether the potential Vb8 on the bit line BL3 is higher or lower than the adjusted reference voltage Vref3. As a result of this sensing operation, LSB (sum information S) is obtained.

[1690]

As described above, according to the present invention,
Simultaneous addition operation can be performed on large-scale data. It is also possible to implement the addition operation using the memory array itself, in which case the dynamic RA
Not only can data storage, which is the original function of M, be performed normally, but also a data addition operation can be realized with a configuration in which a few circuit elements are added.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic principle of a binary addition operation in the present invention.

FIG. 2 is a diagram illustrating a basic configuration example of an addition operation device that realizes an addition operation algorithm according to the present invention.

FIG. 3 is a diagram showing another basic configuration example of the addition operation device of the present invention.

FIG. 4 is a diagram showing a basic principle when the present invention is realized by a DRAM.

FIG. 5 is a diagram showing a basic principle when the present invention is realized by a DRAM.

FIG. 6 shows a DR with an addition operation function according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating a circuit configuration of a main part of an AM.

FIG. 7 is a circuit diagram showing a configuration example of a sense amplifier in the embodiment.

FIG. 8 is a circuit diagram showing a configuration example of a precharge circuit in the embodiment.

FIG. 9 is a block diagram illustrating a configuration example of a sequence control circuit according to the embodiment.

FIG. 10 is a diagram illustrating an algorithm of an addition operation in the embodiment.

FIG. 11 is a diagram showing one stage of an addition operation in the DRAM of the embodiment.

FIG. 12 is a diagram showing one stage of an addition operation in the DRAM of the embodiment.

FIG. 13 is a diagram showing one stage of an addition operation in the DRAM of the embodiment.

FIG. 14 is a diagram showing one stage of an addition operation in the DRAM of the embodiment.

FIG. 15 is a diagram showing one stage of an addition operation in the DRAM of the embodiment.

FIG. 16 is a diagram showing one stage of an addition operation in the DRAM of the embodiment by an equivalent electric network.

FIG. 17 is a diagram showing one stage of an addition operation in the DRAM of the embodiment.

FIG. 18 is a diagram showing one stage of an addition operation in the DRAM of the embodiment using an equivalent electric circuit network.

FIG. 19 is a diagram showing derivation of a reference voltage in the example.

FIG. 20 is a diagram showing one stage of an addition operation in the DRAM of the embodiment.

FIG. 21 is a diagram showing one stage of an addition operation in the DRAM of the embodiment.

FIG. 22 is a diagram showing a configuration of a main part of a DRAM according to another embodiment.

FIG. 23 is a diagram showing one stage of a subtraction operation in the DRAM of the embodiment.

FIG. 24 is a diagram showing one stage of a subtraction operation in the DRAM of the embodiment.

FIG. 25 is a diagram showing one stage of a subtraction operation in the DRAM of the embodiment.

FIG. 26 is a diagram showing one stage of a subtraction operation in the DRAM of the embodiment.

FIG. 27 is a diagram showing one stage of a subtraction operation in the DRAM of the embodiment.

FIG. 28 is a diagram showing one stage of a subtraction operation in the DRAM of the embodiment.

FIG. 29 is a diagram showing a configuration of a main part of a DRAM according to another embodiment.

FIG. 30 is a diagram for explaining a data allocation method in the method of FIG. 29;

FIG. 31 is a diagram for explaining a data allocation method in the method of FIG. 29;

32 is a diagram for explaining a data allocation method in the method of FIG. 29.

FIG. 33 is a diagram for explaining a data allocation method in the method of FIG. 29;

FIG. 34 is a diagram for explaining a data allocation method in the method of FIG. 29;

FIG. 35 is a diagram illustrating a configuration example of an X decoder that can be used in the method of FIG. 29;

FIG. 36 is a diagram showing an algorithm of octal processing of the present invention.

FIG. 37 is a diagram showing another algorithm of octal processing of the present invention.

FIG. 38 is a diagram showing the configuration of an 8-level detection type sense amplifier circuit according to an embodiment of the present invention.

FIG. 39 is a diagram for explaining the operation of octal processing according to the present invention.

FIG. 40 is a diagram showing a conventional binary addition operation method.

FIG. 41 is a diagram showing a conventional addition operation device.

[Explanation of symbols]

Ca, Cb, Cc Capacitor 10 4-value detection voltage detection circuit Pa, Pb, Pc Current path circuit 16 4-value detection current detection circuit S / A 4-value detection sense amplifier S / A1, S / A2, S / A3 Binary detection type sense amplifier BL1, BL1-Complementary bit line pair BL2, BL2- Complementary bit line pair BL3, BL3- Complementary bit line pair MC01, MC02 Temporary memory cells MC11, MC12, MC13 Temporary memory cells MC21, MC22 , MC23 Temporary memory cell T03, T04, T14, T24, T15, T25 Transistor 20 Sequence control unit 22 Precharge circuit 30 X decoder 32 Y decoder

Claims (13)

[Claims] 1. A binary data supply means for providing 1-bit binary data having any one of predetermined binary values, and N number of said binary data supplied from said binary data supply means. The binary data is added, and the sum thereof has one of the preset (N + 1) values (N +
1) first conversion means for converting into value data, detecting the value of the (N + 1) value data generated by the addition means, and converting the detected value to a predetermined bit number of 2
And a second conversion means for converting the data into binary data. 2. The method according to claim 2, wherein at least one of the N pieces of binary data to be added is carry data.
2. The addition arithmetic unit according to claim 1, wherein the least significant bit in said binary binary data obtained by said conversion means is output as a sum, and all remaining upper bits are output as carry. 3. A predetermined quantization level 2
A binary parameter supply element for providing a 1-bit first electrical parameter having any one of the values, and N (N is an integer of 2 or more) provided by the binary parameter supply element The first electric parameter is added, and the sum thereof is added to a second value having any one of (N + 1) values, which is a predetermined quantization level.
A first conversion unit that converts the value into the electrical parameter, and a value of the second electrical parameter generated by the adding unit, and converts the detected value into binary data having a predetermined number of bits. An addition operation device having a second conversion unit; 4. A plurality of memory cells connected to any one of the bit lines and storing a binary charge of a quantization level corresponding to binary information in bit units, and a pair of complementary bit lines. Are added to the sense amplifier connected to the memory cell and the selected N (N is an integer of 2 or more) memory cells on one or more common bit lines, and the amount of charge Adding means for generating, on the bit line, a bit line potential of a quantization level (N + 1) having a voltage value corresponding to the summation; and a number equal to the number of bits required for binary representation of N. Bit line potential supply means separately applied through the bit lines respectively corresponding to the sense amplifiers, and different preset comparison standards for detecting the bit line voltages to the plurality of sense amplifiers. A reference voltage supply means for applying a voltage to each of the plurality of sense amplifiers, and detecting the bit line potential based on the corresponding reference voltage at a predetermined timing. A semiconductor memory device with an addition operation function, comprising: a sense amplifier control unit that obtains binary data representing an addition value by combination. 5. The method according to claim 1, wherein the adding means adds one or more of the common bit lines to a predetermined reference potential before adding the charges respectively stored in the selected N memory cells. 5. The semiconductor memory device with an addition operation function according to claim 4, further comprising a precharge means for precharging the data. 6. The method according to claim 1, wherein the adding means adds the charge stored in each of the N memory cells before adding the charge stored in each of the selected N memory cells. 5. The semiconductor memory device with an addition operation function according to claim 4, further comprising an accumulated charge copy unit for copying the stored charge to a predetermined memory cell. 7. The method according to claim 1, wherein the adding means adds the charges stored in a part of the N memory cells before adding the charges stored in the selected N memory cells. 5. The semiconductor memory device with an addition operation function according to claim 4, further comprising an inversion copy unit that performs logical inversion and copies the data to another predetermined memory cell. 8. The semiconductor memory device with an addition operation function according to claim 4, wherein at least one of said selected N memory cells stores charges representing carry data. 9. The method according to claim 1, wherein the adding means calculates a sum of electric charges respectively stored in the selected N memory cells, respective capacitances, and a parasitic capacitance of the common one or more bit lines. 9. The semiconductor memory device with an addition operation function according to claim 4, wherein a bit line potential having a value according to the following is generated. 10. The semiconductor memory device with an addition operation function according to claim 4, wherein said bit line potential supply means includes a transistor connected between respective bit lines of said plurality of adjacent sense amplifiers. 11. The control circuit according to claim 2, wherein
5. The semiconductor memory device with an addition operation function according to claim 4, wherein the plurality of sense amplifiers perform a sensing operation by shifting a predetermined time in order from the highest digit of binary output constituting binary binary data. 12. The comparison reference voltage supply means determines a comparison reference potential for the sense amplifier of the next lower digit in accordance with a binary output obtained from the sense amplifier of each upper digit. A semiconductor memory device with the addition operation function according to the above. 13. A plurality of memory cells connected to any one of bit lines and storing binary charge of a quantization level corresponding to binary information in bit units, and a selected one of N memory cells (N (An integer of 2 or more) are added together on one common bit line, and the quantization level (N + 1) value having a voltage value corresponding to the sum of the charge amounts is added. An adder for generating a bit line potential on the bit line; and M (M is N) connected in parallel to each complementary bit line pair.
The number of bits required for binary representation of the sense amplifier), bit line potential supply means for separately applying the bit line potential to the M sense amplifiers via the bit line, Comparison reference voltage supply means for respectively providing different comparison reference voltages set in advance for detecting the bit line voltage, and the M number of sense amplifiers are respectively provided at predetermined timings based on the corresponding comparison reference voltages. A semiconductor memory device having an addition operation function, comprising: sense amplifier control means for detecting a bit line potential and combining respective binary outputs of the sense amplifiers to obtain M-bit binary data representing an addition value.