JP2000150826A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a conformal TiN film in a trench or hole having high aspect ratio by making a trench or hole in on a semiconductor substrate or an insulating film formed thereon and then setting the flow rate of titanium tetrachloride equal to or higher than a specified flow rate of ammonia. SOLUTION: At first, virgin gas is introduced into a chamber and unnecessary gas is purged and then a semiconductor substrate 1 is heated. Subsequently, virgin gas in the chamber is discharged and titanium tetrachloride is introduced along with ammonia and a TiN film 27 is deposited on a tantalum oxide film 26 through reaction of these gases. When the flow rate of titanium tetrachloride is set equal to or higher than 0.1 times that of ammonia, a conformal TiN film 27 can be formed even in a deep trench 24. Thereafter, TiN film 27 is deposited furthermore by sputtering in order to fill the trench 24 completely with the TiN film 27.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for manufacturing a semiconductor integrated circuit device, and more particularly to a CV using a source gas containing Ti (titanium) and a source gas containing nitrogen.
The present invention relates to a technique for forming a conformal TiN (titanium nitride) film on a semiconductor substrate by a D (Chemical Vapor Deposition) method.

[0002]

2. Description of the Related Art A TiN film formed by a CVD method is a TN film formed by a reactive sputtering method or the like.
Since the step coverage (step coverage) is better than the iN film, the aspect ratio (through-hole depth /
It is widely used as a plug material to be embedded in a through hole having a large diameter and an electrode wiring material.

[0003] For example, Japanese Patent Application Laid-Open No. 9-45770 discloses a CVD method in which a through hole formed in an interlayer insulating film is formed.
A technique is disclosed in which a TiN film is deposited by a method and a W (tungsten) film or a W compound is formed on the TiN film. Japanese Patent Application Laid-Open No. 8-204144 discloses a technique using a TiN film deposited by a CVD method as a barrier layer for preventing a reaction between a metal wiring layer in a miniaturized contact hole and its underlying film. It has been disclosed. Further, Japanese Unexamined Patent Publication Nos.
No. 501 discloses a DRAM (Dynamic Random Access M
emory) as an electrode material for a capacitive element (capacitor)
A technique using a TiN film deposited by a VD method is disclosed.

In order to form a TiN film by the CVD method, generally, a source gas obtained by mixing a gas containing Ti such as titanium tetrachloride (TiCl ₄ ) and a gas containing nitrogen such as ammonia (NH ₃ ) is used. Is used.
For example, in the above-mentioned Japanese Patent Application Laid-Open No. H3-132023, the flow rate of titanium tetrachloride is set to 0.01 to 0.
1, low pressure C with pressure set to 0.01 to 0.5 Torr
A technique for forming a TiN film by a VD method or a plasma CVD method is disclosed.

In recent years, large-capacity DRAMs have a stacked capacitor in which a capacitor is arranged above a memory cell selection MISFET in order to compensate for a decrease in the amount of charge stored in the capacitor due to miniaturization of a memory cell. capac
Itor) structure is adopted. Further, the surface area of the lower electrode (storage electrode) of the capacitive element is increased, and the capacitive insulating film is made of a material having a high dielectric constant. In particular, tantalum oxide (T
a ₂ O ₅ ) has a high dielectric constant of 20 to 25 and is highly compatible with a conventional DRAM process using a polycrystalline silicon film as a lower electrode material. Is being advanced.

When the capacitive insulating film of the capacitive element is made of the above-described tantalum oxide, it is necessary to select a material that does not deteriorate the film quality of the tantalum oxide as a material of the upper electrode (plate electrode) formed on the capacitive insulating film. is there. The TiN film described above is considered to be suitable as one of such upper electrode materials.

For example, the influence of the upper electrode material on the leakage current before and after annealing on the tantalum oxide film was examined. "Applied Physics (Jpn. J. Appl. Phys. Vol. 33 (1994) Pt. 1, N
o.3A) ”is based on experimental results that the work function of the upper electrode material and the stability of the upper electrode / tantalum oxide interface determine the electrical properties of the tantalum oxide film. (Approximately 400 ° C.), TiN, and Mo or MoN (molybdenum nitride) when performed at high temperatures (approximately 800 ° C.).

[0008]

SUMMARY OF THE INVENTION The present inventor has proposed a DRAM.
In order to increase the surface area of the lower electrode (storage electrode) of the capacitive element, deep trenches are dug in a thick insulating film deposited on a semiconductor substrate, and formation of a capacitive element inside the trench is being studied.

In order to form a capacitive element inside a groove, after forming a groove by etching an insulating film, a conductive film (polycrystalline silicon film) for a lower electrode and a capacitive insulating film (polycrystalline silicon film) are formed along the inner wall of the groove. Tantalum oxide film) and conductive film for upper electrode (TiN
Are sequentially deposited. In this case, by using a CVD method having good step coverage, a polycrystalline silicon film, a tantalum oxide film, and a T film that are conformal (ie, have a uniform film thickness that is faithful to the shape of the underlying step) are formed along the inner wall of the groove.
The formation of an iN film can be expected.

However, when the design rule of the DRAM becomes 0.25 μm or less and the aspect ratio of the groove becomes extremely large (especially, the area of the inner wall of the groove becomes 25 times or more of the opening area of the groove), the conventional film forming method becomes ineffective. The present inventor has clarified that it is difficult to form a conformal TiN film inside the groove if used. This is because when the area of the inner wall of the groove exceeds 25 times the opening area, T
This is considered to be because the supply amount of titanium tetrachloride gas used for forming the iN film is limited by the opening area of the groove, and a sufficient amount of titanium tetrachloride gas is not supplied to the bottom of the groove.

An object of the present invention is to provide a technique capable of forming a conformal TiN film inside a groove or a hole having a large aspect ratio.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

According to a method of manufacturing a semiconductor integrated circuit device of the present invention, after forming a groove or a hole in a semiconductor substrate or an insulating film formed on the semiconductor substrate, a source gas containing titanium tetrachloride and ammonia is used. A step of forming a titanium nitride film inside the groove or the hole by a CVD method in which the flow rate of the titanium tetrachloride is 0.1 or more of the flow rate of the ammonia.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

FIGS. 1 to 10 and FIGS. 12 and 13 are sectional views of a main part of a semiconductor substrate (wafer) showing a method of manufacturing a DRAM according to the present embodiment. FIG. It is the schematic of an apparatus.

In order to manufacture this DRAM, first, as shown in FIG. 1, an element isolation groove 2 is formed on a main surface of a semiconductor substrate (wafer) 1 made of, for example, single-crystal silicon having a specific resistance of about 10 .OMEGA.cm. After that, a p-type well 3 is formed. The element isolation groove 2 is formed by dry etching the semiconductor substrate 1 to form a groove, and then forming a trench on the semiconductor substrate 1 including the inside of the groove.
A silicon oxide film 4 is deposited by a VD method, and subsequently, the silicon oxide film 4 is subjected to chemical mechanical polishing (Chemical Mechanical Polishing).
(ng; CMP) method and leave only inside the groove. In addition, the p-type well 3 has n
The semiconductor substrate 1 is formed by ion-implanting a type impurity, for example, P (phosphorus), and then annealing the semiconductor substrate 1 to thermally diffuse the impurity.

Thereafter, the surface of the p-type well 3 is cleaned using a HF (hydrofluoric acid) -based cleaning solution, and the semiconductor substrate 1 is wet-oxidized to form a clean gate oxide film 5 on the surface of the p-type well 3. I do.

Next, as shown in FIG.
After forming a gate electrode 6 (word line) on the upper part of the gate electrode 6, an n-type semiconductor region 7 (source, drain) is formed in the p-type well 3 on both sides of the gate electrode 6, thereby forming a memory cell selecting MISFET Qs. .

The gate electrode 6 is formed, for example, by depositing a polycrystalline silicon film doped with an n-type impurity such as P (phosphorus) on the semiconductor substrate 1 by a CVD method, and then forming a WN (tungsten nitride) film and a W A (tungsten) film is deposited by a sputtering method, a silicon nitride film 8 is further deposited thereon by a CVD method, and these films are patterned by using a photoresist film as a mask. Further, the n-type semiconductor region 7 (source, drain) is provided with an n-type impurity such as P (phosphorus) in the p-type well 3.
Is formed by ion implantation.

Next, as shown in FIG. 3, the silicon nitride film 9 and the silicon oxide film 1 are formed on the semiconductor substrate 1 by CVD.
After depositing 0, the silicon oxide film 10 is polished by a CMP method to flatten the surface thereof, and then a silicon oxide film 11 is deposited thereon by a CVD method. Silicon oxide film 11
Is formed to protect the surface of the silicon oxide film 10 that has been finely scratched by the polishing by the CMP method.

Next, as shown in FIG. 4, the silicon oxide films 11, 10 and the silicon nitride film 9 above the n-type semiconductor region 7 (source and drain) are dry-etched using the photoresist film as a mask to make contact. Hall 1
After the formation of the plugs 3 and 14, a plug 15 made of a polycrystalline silicon film is formed inside the contact holes 13 and 14. The plugs 15 are, for example, contact holes 13 and 14
After a polycrystalline silicon film doped with an n-type impurity such as P (phosphorus) is deposited on the silicon oxide film 11 including the inside of the silicon oxide film by a CVD method, the polycrystalline silicon film on the silicon oxide film 11 is formed by a CMP method ( Alternatively, it is formed by removing it by an etch-back method and leaving it only inside the contact holes 13 and 14.

Next, as shown in FIG. 5, a silicon oxide film 16 is deposited on the silicon oxide film 11 by a CVD method.
Subsequently, the silicon oxide film 16 is dry-etched to form a through hole 17 above the contact hole 13, then a plug 18 is formed inside the through hole 17, and a bit line BL is formed above the plug 18.

The plug 18 is formed, for example, by depositing a Ti film, a TiN film, and a W film on the silicon oxide film 16 including the inside of the through hole 17 by a CVD method or a sputtering method. CMP membrane
It is formed by removing by a method. Also, the bit line BL
Is formed, for example, by depositing a W film on the silicon oxide film 16 by a sputtering method, and then patterning the W film by dry etching using a photoresist film as a mask.

Next, as shown in FIG. 6, a silicon oxide film 19 is deposited on the silicon oxide film 16 by the CVD method.
Subsequently, after the silicon oxide film 19 is dry-etched to form a through-hole 20 above the contact hole 14, a plug 21 is formed inside the through-hole 20.
The plug 21 is formed, for example, by depositing a polycrystalline silicon film doped with an n-type impurity such as P (phosphorus) on the silicon oxide film 19 including the inside of the through hole 20 by a CVD method.
CMP of the polycrystalline silicon film on top of the silicon oxide film 19
Through hole 2
It is formed by leaving only inside 0.

Next, as shown in FIG. 7, after a silicon nitride film 22 and a silicon oxide film 23 are deposited on the silicon oxide film 19 by the CVD method, the silicon oxide film 23 and the nitride Silicon film 22
Is dry etched to form a groove 24 above the plug 21. Since the lower electrode of the information storage capacitance element described later is formed along the inner wall of the groove 24,
In order to increase the surface area of the lower electrode and increase the amount of accumulated charges, the silicon oxide film 23 must have a large thickness (for example, 1.3 μm).
m) to form a deep groove 24.
Although not particularly limited, in the present embodiment, the area of the inner wall of the groove 24 is 25 times or more the area of the opening.

Next, as shown in FIG. 8, n (such as P (phosphorus)) is
After the amorphous silicon film 25A doped with the p-type impurity is deposited by the CVD method, the amorphous silicon film 25A on the silicon oxide film 23 is etched back and removed, thereby removing the amorphous silicon film 25A along the inner wall of the groove 24. leave.

Next, after cleaning the surface of the amorphous silicon film 25A remaining inside the groove 24 with a hydrofluoric acid-based etchant, the amorphous silicon film 25
By supplying monosilane to the surface of A and subsequently heat-treating the semiconductor substrate 1 to polycrystallize the amorphous silicon film 25A and grow silicon grains on the surface, the surface becomes rough as shown in FIG. A lower electrode 25 made of the converted polycrystalline silicon film is formed along the inner wall of the groove 24.

Next, as shown in FIG. 10, on the silicon oxide film 23 including the inside of the groove 24, a tantalum oxide film 26 constituting a capacitive insulating film of the information storage capacitor is deposited. The tantalum oxide film 26 is formed of, for example, C using pentaethoxy tantalum (Ta (OC ₂ H ₅ ) ₅ ) as a source gas.
Deposit by VD method.

Next, after the semiconductor substrate 1 is heat-treated in an oxidizing atmosphere to improve the film quality of the tantalum oxide film 26, the semiconductor substrate 1 is transferred to the chamber 4 of the CVD apparatus 40 shown in FIG.
Carry in 1.

The CVD apparatus 40 has a structure in which a purge gas composed of titanium tetrachloride, ammonia, and an inert gas (for example, nitrogen or argon) is individually introduced into the chamber 41. A stage 42 for mounting the semiconductor substrate 1 is provided inside the chamber 41, and a heater 43 for heating the semiconductor substrate 1 is provided above the stage 42. A vacuum pump 44 for adjusting the degree of vacuum in the chamber 41 is connected to the chamber 41.

In the present embodiment, the semiconductor substrate 1 is
After being carried into the chamber 41 of the VD device 40, first, a purge gas is introduced into the chamber 41 to exhaust unnecessary gas, and the semiconductor substrate 1 is heated to 400 ° C. using the heater 43.
Heat to about 600 ° C. At this time, the temperature of the semiconductor substrate 1 can be increased in a short time by introducing a large amount of the purge gas to maintain the inside of the chamber 41 at a high pressure and increase the heat conductivity using the purge gas as a medium.

Next, after evacuating the purge gas in the chamber 41, titanium tetrachloride and ammonia are introduced, and these gases are reacted, as shown in FIG.
On the tantalum oxide film 26, a TiN film 27 is deposited.

According to an experiment conducted by the present inventor, at this time, by setting the flow rate of titanium tetrachloride to 0.1 or more of the flow rate of ammonia, a conformal TiN film 27 is formed even in the deep groove 24. We were able to. If the ratio of the flow rate of titanium tetrachloride to the flow rate of ammonia becomes excessive, the amount of chlorine taken in as an impurity in the TiN film 27 increases, thereby corroding the Al wiring formed above the information storage capacitor. There is fear. Therefore,
From the viewpoint of preventing corrosion of the Al wiring, the flow rate ratio between titanium tetrachloride and ammonia is set as follows: titanium tetrachloride: ammonia = 0.1
It is preferably in the range of ４4: 1.

Also, the flow rate of the source gas is increased,
When the pressure increases, the Ti inside the groove 24 is reduced.
As the coverage of the N film 27 decreases, the amount of chlorine in the film increases. Accordingly, the flow rates of titanium tetrachloride and ammonia are preferably low flow rates of 50 sccm or less, respectively, and the pressure during film formation is also preferably low pressure (eg, 1333 Pa or less).

Further, if a reducing gas such as ammonia comes into contact with the tantalum oxide film 26 constituting the capacitive insulating film, the withstand voltage of the film may be deteriorated and the leak current may increase. Therefore, when introducing titanium tetrachloride and ammonia into the chamber 41, titanium tetrachloride is introduced slightly (for example, 20 seconds or less) earlier than ammonia to prevent the tantalum oxide film 26 from being deteriorated. desirable.

Next, after the TiN film 27 is deposited as described above, a TiN film 27 is further deposited by a sputtering method as shown in FIG.
It is completely buried with an N film 27. By the steps so far, T
An information storage capacitance element C is formed which includes an upper electrode made of an iN film 27, a capacitance insulating film made of a tantalum oxide film 26, and a lower electrode 25 made of a polycrystalline silicon film having a roughened surface. , MISFETQ for memory cell selection
A memory cell of the DRAM composed of the s and the information storage capacitor C connected in series to the s is completed.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

In the above embodiment, the TiN film is formed by using the low-pressure CVD method. However, the TiN film may be formed by using the plasma CVD method. Further, the present invention can be applied not only to the case where the upper electrode is formed only of the TiN film, but also to the case where the upper electrode is formed of a conductive film in which another conductive film (such as a W film) is stacked on the TiN film.

In the above-described embodiment, the present invention is applied to a DRAM having a stacked capacitor structure in which a capacitor is arranged above a memory cell selecting MISFET. However, a capacitor is arranged in a groove or a hole formed in a semiconductor substrate. The present invention can also be applied to a DRAM having a trench capacitor structure.

As a capacitive insulating film of the capacitive element, besides a tantalum oxide film, for example, BST, STO, BaTiO ₃
(Barium titanate), PbTiO ₃ (lead titanate),
PZT (PbZr _x Ti _1-x O ₃ ), PLT (PbLa
_A high (ferro) dielectric film made of a metal oxide such as _X Ti _1-X O ₃ ) or PLZT can also be used.

The present invention is applicable not only to the case where a CVD-TiN film is used as an electrode of a capacitive element, but also to a method of forming a plug or wiring inside a high aspect ratio groove or hole (through hole or contact hole) formed in an insulating film. The present invention can also be applied to a case where it is used as a barrier metal at the time of formation.

[0043]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

According to the present invention, it is possible to form a conformal TiN film inside a groove or a hole having a large aspect ratio. Thereby, for example, a capacitor element or a barrier metal formed inside a groove having a large aspect ratio is formed.
The reliability of the SI and the production yield can be improved.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a DRAM according to an embodiment of the present invention;

FIG. 2 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 11 is a schematic diagram of a CVD apparatus used in one embodiment of the present invention.

FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate (wafer) 2 element isolation groove 3 p-type well 4 silicon oxide film 5 gate oxide film 6 gate electrode 7 n-type semiconductor region (source, drain) 8 silicon nitride film 9 silicon nitride film 10 silicon oxide film 11 silicon oxide Film 13, 14 Contact hole 15 Plug 16 Silicon oxide film 17 Through hole 18 Plug 19 Silicon oxide film 20 Through hole 21 Plug 22 Silicon nitride film 23 Silicon oxide film 24 Groove 25A Amorphous silicon film 25 Lower electrode 26 Tantalum oxide film 27 TiN film Reference Signs List 40 CVD device 41 Chamber 42 Stage 43 Heater 44 Vacuum pump BL Bit line C Information storage capacitor Qs Memory cell selection MISFET

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Kentaro Yamada 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. (72) Inventor Masakazu Kono Kamisuihoncho, Kodaira-shi 5-22-1, Hitachi Super LSI Systems Co., Ltd. (72) Inventor Kenshi Sakai 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Semiconductor Company, Hitachi, Ltd. 72) Inventor Ryoichi Furukawa 6-16-16 Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. LSI Systems Inc. (72) Inventor Tsuyoshi Tamaru 3-16, Shinmachi, Omachi, Tokyo 3 Hitachi, Ltd. 4K030 AA03 AA13 BA18 BA38 BB12 BB14 CA12 DA01 HA04 JA05 JA09 LA02 LA15 5F083 AD24 AD48 AD49 AD62 JA06 JA14 JA15 JA39 JA40 MA06 MA17 MA20 PR21 PR39 PR40

Claims (9)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit device, comprising the following steps (a) and (b): (a) forming a groove or a hole in a semiconductor substrate or an insulating film formed on the semiconductor substrate; (B) using a source gas containing titanium tetrachloride and ammonia, and using a source gas containing titanium tetrachloride and a flow rate of the titanium tetrachloride of 0.1 or more of the flow rate of the ammonia, by a CVD method to form the inside of the groove or the hole; Forming a titanium nitride film; 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the area of the inner wall of the groove or the hole is at least 25 times the opening area thereof. Manufacturing method. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the flow rate ratio of said titanium tetrachloride and said ammonia is titanium tetrachloride: ammonia = 0.1 to 4: 1.
A method of manufacturing a semiconductor integrated circuit device. 4. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the flow rates of said titanium tetrachloride and said ammonia are each 50 sccm or less. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the pressure at which said titanium nitride film is formed is 1333 Pa or less. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said titanium nitride film forms one electrode of a capacitive element formed inside said groove or hole. Of manufacturing a semiconductor integrated circuit device. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein at least one conductive film is formed on the titanium nitride film after the step (b). Alternatively, a method for manufacturing a semiconductor integrated circuit device, comprising forming a plug made of the titanium nitride film and the conductive film inside a hole. 8. A DRAM in which a memory cell is constituted by a memory cell selecting MISFET and an information storing capacitive element connected in series thereto, and wherein said information storing capacitive element is arranged above said memory cell selecting MISFET. (A) forming a memory cell selecting MISFET on a main surface of a semiconductor substrate, and (b) forming an insulating film on the memory cell selecting MISFET. Forming a groove in the insulating film;
(C) forming a first conductive film inside the trench, and then forming a capacitive insulating film on the first conductive film; (d) using a source gas containing titanium tetrachloride and ammonia;
The flow rate of the titanium tetrachloride is set at 0.
Forming a titanium nitride film on the capacitor insulating film by a CVD method of at least one, so that a lower electrode made of the first conductive film, the capacitor insulating film, and the titanium nitride film are formed inside the trench; Forming an information storage capacitance element having a stacked structure composed of an upper electrode and a semiconductor integrated circuit device. 9. The method for manufacturing a semiconductor integrated circuit device according to claim 8, wherein said capacitance insulating film contains tantalum oxide.