JP2000163388A - Data processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate the processing speed of a data processor for asynchronously performing series of plural kinds of processing at plural processing parts. SOLUTION: An image input device 1, processing parts 2-6 and image output device 8 respectively asynchronously perform processing to inputted pixel data. The processing parts 2-6 respectively execute the processing of SH correction, Log conversion, MTF correction, gamma correction and binarization. A state register 10 stores the addresses of pixel data to be processed by the processing parts 2-6. A data flow control part 9 detects the processing part of large load from the addresses of pixel data, which are stored in the state register 10, to be executed by the respective processing parts and outputs a control signal to the processing parts 2-6 so as to change the processing to be executed when the processing part of large load is detected. The processing parts 2-6 load and execute the programs of the processing of large load from a ROM in the data flow control part 9 corresponding to the reception of the control signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing system, and more particularly to a data processing system in which a plurality of processing units execute a plurality of processes in a predetermined order.

[0002]

2. Description of the Related Art FIG. 30 is a block diagram schematically showing a synchronous pipeline data processing apparatus as a first prior art. A conventional data processing device includes an MPU 70,
The image output device 77 includes an image input device 71, processing units 72 to 76 that respectively perform five processes of SH correction, Log conversion, MTF correction, gamma correction, and binarization. The image input device 71 includes a photoelectric conversion element such as a CCD, a driving system for operating the photoelectric conversion element and an A / D converter, and generates a sampled analog signal by scanning a mixed original including, for example, a continuous tone image and a line drawing. Then, the A / D converter quantizes the sampled analog signal as continuous tone reflectance data in which one pixel has a value of, for example, 8 bits (256 tones),
Output digital signal.

[0003] A processing section 72 performs an SH correction process. S
The H correction processing is also referred to as shading correction, and is a correction processing for removing reading unevenness (shading unevenness) due to a variation in performance or the like of a photoelectric conversion element of a CCD of the image input device 71.

[0004] A processing unit 73 performs a Log conversion process.
The log conversion process is a process of calculating and outputting 8-bit continuous tone density data having a Log relationship with the continuous tone reflectance data subjected to the SH correction process.

[0005] A processing unit 74 performs an MTF correction process.
The MTF correction process is a sharpness correction, and the sharpness correction is performed on the 8-bit continuous tone density data obtained by performing the Log conversion process on the image data by the processing unit 73 using a digital filter such as a Laplacian filter. .

[0006] The processing unit 75 performs gamma correction processing.
The gamma correction process is a process of correcting a difference in a gradation curve between the image input device 71 and the image output device 77 in order to realize a gamma characteristic desired as a whole of the data processing device. For example, this is a process of outputting nonlinear gamma correction data using a 256-word 8-bit LUT (look-up table). Further, the gamma correction process can be performed by the operator to set his / her desired gamma characteristic.

The processing section 76 performs a binarization process. The binarization process is a process of converting gamma-corrected 8-bit continuous tone density data into 1-bit binary data corresponding to brightness. For the binarization processing, for example, an area gradation binarization method such as an error diffusion binarization method is used.

The image output device 77 is a printer such as an electrophotographic printer or an ink jet printer, and prints 1-bit binary data binarized by the processing unit 76 on an output medium such as paper.

[0009] An image input device 71 and processing units 72 to 76
And the image output device 77 are connected by an image data bus, and process data input in synchronization with a common pixel clock.

As described above, the data processing device of the synchronous pipeline system shown in the first prior art uses the image input device 7.
The image data input in 1 is sequentially processed by the processing units 72 to 76 for each piece of pixel data. In order to synchronize the input and output of pixel data among the image input device 71, the processing units 72 to 76, and the image output device 77, a pixel clock corresponding to each piece of pixel data is generated by a clock oscillator (not shown). The image input 71, the processing units 72 to 76, and the image output device 77 operate in synchronization with the pixel clock.

In the second prior art, there is a method in which the five processes shown in the first prior art are asynchronously processed by five processing units. FIG. 31 is a block diagram for explaining the asynchronous processing method. Referring to FIG. 31, processing blocks 81, 82, and 83 include unique clocks 85, 8 respectively.
6, 87 to perform processing. However, since the respective processing blocks operate without synchronization, data cannot be directly exchanged between the processing blocks. Therefore, it is necessary to provide buffer memories 83 and 84 having a predetermined capacity between blocks. Buffer memory 8
3, 84, the processing blocks 80, 81, 8
This is because a difference in processing speed between the two can be absorbed.

Further, there is a parallel processing system for performing the same processing in parallel as a third conventional technique. For example, a technique disclosed in Japanese Patent Application Laid-Open No. 61-28164 discloses a technique in which a pipeline processor in which a plurality of image pipeline processors that perform parallel processing are connected in a ring shape is a task (image data), an object program for each task, and a task. A technique is disclosed in which a table for each task is loaded from a memory and a predetermined task is processed in parallel.

[0013]

However, in the data processing device of the synchronous pipeline system shown in the first prior art, the image input device 71, the processing blocks 72 to 76,
Since each of the image output devices 77 operates in synchronization with the pixel clock, the pixel clock is output from the image input device 71, the processing blocks 72 to 76, and the image output device 77.
Of these, it had to be generated according to the slowest operating speed. For this reason, the circuit must be configured in accordance with the processing block (processing block having a low operation speed) that becomes a bottleneck, and circuit design is difficult.

In the data processing device of the asynchronous processing system shown in the second prior art, the processing block which becomes a bottleneck is smaller than that of the synchronous pipeline system shown in the first prior art. Although the speed is determined, the cost is increased because a buffer memory is required. In addition, since writing and reading of data from two processing blocks occur in the buffer memory, arbitration between the processing blocks so that any one processing block can access the buffer memory is performed. There is a problem that the processing must be performed in a processing block or a controller provided for each buffer memory.

Further, in the parallel processing method shown in the third prior art, processing with a large processing load is processed by a plurality of processing blocks connected in parallel, so that processing can be performed at high speed. Since the processing blocks to be executed are added in advance, if the load of the processing blocks fluctuates according to the input data, when the load is small, one of the processing blocks connected in parallel will not be used. However, there has been a problem that the performance of the device is deteriorated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and the control of the asynchronous processing is devised so that even if the load varies depending on the data to be processed, the data can be processed at high speed. It is an object of the present invention to provide a data processing system that enables the above.

[0017]

A data processing system according to one aspect of the present invention is a data processing system for asynchronously performing a series of a plurality of processes on a plurality of serially input data, and includes a plurality of processes. A plurality of processing units for executing each of the plurality of processes, a state monitoring unit for monitoring how far each of the plurality of processes has progressed to the plurality of input data, and detecting a delay process of which the progress is delayed among the plurality of processes; First operation control means for switching processing to be executed by the plurality of processing units in accordance with a detection result of the means.

Preferably, the first operation control means of the data processing system performs the processing to be executed by the processing unit which executes the immediately preceding processing immediately before the stagnation processing detected by the state monitoring means, by executing the immediately preceding processing and the delay processing. It is characterized by switching to the two processes

[0019] More preferably, the first operation control means of the data processing system performs a delay processing and an immediate processing on the processing unit which executes the processing immediately after the stagnation processing detected by the state monitoring means. It is characterized by switching to the two processes of

More preferably, the data processing system further includes storage means for storing a result of the processing performed by each of the plurality of processing units, and the first operation control means includes:
For a processing unit that executes processing subsequent to the delay processing detected by the state monitoring unit, the processing to be executed is switched to the stagnation processing.

More preferably, the plurality of processing units of the data processing system have more than the number of the plurality of processes, and the first operation control means includes a preliminary processing unit which does not execute any of the plurality of processes before switching the processes. At least one, the first
Operation control means, according to the detection result of the state monitoring means,
The processing is switched so as to execute the delay processing for the preliminary processing unit.

More preferably, the input data input to the data processing system has an address indicating the order of the input data, and the state monitoring means detects an address of the input data to be processed by each of the plurality of processing units. The processing unit detects the address difference between adjacent processing units, and when the detected address difference is smaller than a predetermined value, detects the processing executed by the processing unit preceding the adjacent processing unit as delay processing It is characterized by doing.

More preferably, the state monitoring means of the data processing system counts the number of input data processed by each of the plurality of processing units, and detects a difference in the count value between adjacent processing units in the plurality of processing units. When the difference between the detected count values is smaller than a predetermined value, a process executed by a processing unit preceding the adjacent processing unit is detected as a delay process.

A data processing system according to another aspect of the present invention is a data processing system for asynchronously performing a series of a plurality of processes on a plurality of serially input data, the plurality of processes executing each of the plurality of processes. Processing unit,
The plurality of processes include an attribute determining process for detecting an attribute of the input data, and include a second operation control unit that switches a process to be executed by the plurality of processing units according to a result of the attribute determining process.

Preferably, the second operation control means of the data processing system includes a prediction means for predicting a load of a plurality of processings, and executes the immediately preceding processing immediately before the load processing whose load is predicted to be large by the prediction means. The processing unit switches the processing to be executed to two processings of the immediately preceding processing and the load processing.

More preferably, the second operation control means of the data processing system includes a prediction means for predicting a load of a plurality of processings, and executes the processing immediately after the load processing whose load is predicted to be large by the prediction means. The processing to be performed is switched to two processings, a load processing and a processing immediately after, for a processing unit that performs the processing.

More preferably, the plurality of processing units of the data processing system have more than the number of the plurality of processes, and a spare processing unit that does not execute any of the plurality of processes before the switching of the process by the second operation control means. At least one, second
The operation control means includes a prediction means for predicting loads of a plurality of processes, and switches processing to a preliminary processing unit so as to execute a load process whose load is predicted to be large by the prediction means. I do.

More preferably, the data processing system comprises:
The apparatus further includes a storage unit that stores a result of the processing performed by each of the plurality of processing units, wherein the second operation control unit includes a prediction unit that predicts a load of the plurality of processes, and the prediction unit determines that the load is large. For a processing unit that executes processing subsequent to the performed load processing, processing to be executed is switched to load processing.

More preferably, the plurality of processing units of the data processing system transmit the input data after executing the self-processing to a processing unit that executes a process immediately after the self-processing executed by the self among the plurality of processes. It is characterized by being handed over.

A data processing system according to another aspect of the present invention is a data processing system for asynchronously performing a series of a plurality of processes on a plurality of serially input data, wherein the plurality of processes execute each of the plurality of processes. Processing unit,
There is no storage means for storing the result of the processing performed by each of the plurality of processing units, and there is no input data to be processed by the processing unit,
And a third operation control means for switching the processing executed by the processing unit to the immediately following processing when the input data after the processing is stored in the storage means.

According to these inventions, the processing to be executed by the processing unit is switched according to the load of the input data irrespective of the type of the input data, so that a data processing system capable of high-speed data processing is provided. Can be provided.

[0032]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding members.

[First Embodiment] FIG. 1 is a block diagram schematically showing a data processing apparatus according to a first embodiment of the present invention. Referring to the figure, a data processing apparatus according to the first embodiment includes an image input device 1 for inputting image data, MPUs 2 to 6 for performing various processes on the input image data for each pixel data, An image output device 8 for outputting the output image data to a recording medium such as paper;
A status register 10 for monitoring the operation status of the image input device 1, the MPUs 2 to 6, and the image output device 8 (hereinafter referred to as "MPUs 1 to 8"), and the operation of the MPUs 1 to 8 with reference to the status register 10. , An input buffer memory 11 for temporarily storing image data input by the image input device 1, and an output buffer memory 12 for temporarily storing image data output from the image output device. .

The MPUs 2 to 6 are microprocessing units, and the contents to be processed by the respective MPUs 2 to 6 are determined by instructions from the data flow control unit 9,
The processing to be executed by each of the MPUs 2 to 6 is determined by loading a processing program stored in a ROM provided inside the data flow control unit 9. In the initial state, for example, when the power of the data processing device is turned on, or when one page of image data is input,
The MPU 2 receives instructions from the data flow control unit 9 to perform SH correction processing, the MPU 3 performs Log conversion processing, the MPU 4 performs MTF correction processing, the MPU 5 performs gamma correction processing, and the MPU 6 performs binary processing. MPU2
At 6, each program is loaded. Note that the contents of the five processings of the SH correction processing, the Log conversion processing, the MTF correction processing, the gamma correction processing, and the binarization processing are the same as the processing described in the first related art of the related art. The description here will not be repeated.

Similarly, the image input device 1 and the image output device 8 are similarly used for the image input device 71 described in the prior art.
And image output device 77, respectively, and thus description thereof will not be repeated.

The MPUs 1 to 8 include a data flow control unit 9
And the status register 10
And a system bus 15. The MPUs 1 to 8 are connected to each other by an image data bus 13 so that pixel data can be transferred between the MPUs 1 to 8 and input / output to / from the input buffer memory 11 and the output buffer memory 12 can be performed. Has become.

In the data processing apparatus shown in FIG. 1, an original is read by the image input device 1, and the image data is stored in the input buffer memory 11 for each pixel data. MPU
In step 2, the pixel data stored in the input buffer memory 11 is read out in the order stored in the image input device 1, and SH
Perform correction processing. The pixel data subjected to the SH correction processing in the MPU 2 is transferred to the MPU 3. In MPU3, MPU
2 performs a log conversion process on the pixel data received from
The pixel data is transferred to U4. As described above, the pixel data is sequentially passed to the MPUs 2 to 6, and is subjected to the SH correction processing and the L
The pixel data subjected to the og conversion processing, the MTF correction processing, the gamma correction processing, the binarization processing, and the binarization processing by the MPU 6 are stored in the output buffer memory 12. The image output device 8 stores the processed pixel data in the output buffer memory, and at the same time, performs display output on a display or print output on a recording medium such as paper.

FIG. 2 is a diagram for explaining a procedure for transferring data between the MPU executing the preceding processing and the MPU executing the following processing. In FIG. 2, MPU3 and M
An example of a procedure for transferring data to and from the PU 4 will be described. MP
When the processing is completed in U3, a signal REQ for requesting the MPU 4 to deliver the pixel data DATA is transmitted. After receiving the signal REQ requesting the transfer from the MPU 3, the MPU 4 transmits a signal ACK to the MPU 3 to respond to the transfer of the data to the MPU 3 at the time when the processing currently being performed by the MPU 4 is completed.
When the MPU 3 receives the signal ACK corresponding to the transfer of the data from the MPU 4, the MPU 3 transmits the pixel data DATA to the MPU 4. In this way, the MPU
3 and the MPU 4 perform the processing asynchronously, and transfer the pixel data DATA.

The pixel data DATA is transferred between the MPUs 2 to 6 according to the above-described procedure.
The processing is sequentially performed in each of the MPUs 2 to 6. However, depending on the pixel data, the time required for processing in each of the MPUs 2 to 6 is not equal. For example, for certain pixel data, the MTF correction process takes time and M
The load on PU4 increases, and as a result, MPU
4 becomes a bottleneck, and the data processing speed of the entire data processing device is reduced.

In order to avoid this problem, the data processing device according to the present embodiment uses the MPU 2
6 are monitored, and the data flow control unit 9
Thus, an instruction is given to the MPU that executes the subsequent processing of the MPU with the increased processing load to execute the processing that is executed by the MPU with the increased load. This will be described in detail.

FIG. 3 is a flowchart showing the flow of processing performed by data flow control section 9. Referring to the figure, data flow control unit 9 monitors the processing load of each of MPUs 2 to 6 with reference to status register 10 (step S01). The status register 10 stores the processing time required for processing the pixel data sent from each of the MPUs 2 to 6 and the address of the processed pixel data. The data flow control unit checks the contents of the status register 10. Thus, the loads on the MPUs 2 to 6 can be grasped.

As a result, when there is an MPU with a large processing load (YES in step S02), the MPU with a large load is set.
The control signal ON is output to the MPU performing the processing of the preceding stage of the PU so that the processing executed by the MPU having a large load is continued in addition to the processing currently being performed (step S03). For example, referring to FIG. 1, when the load on MPU 4 performing the MTF correction processing increases, data flow control unit 9 determines the status of MPU 4 based on the status of status register 10.
, The MPU 3 that executes the log conversion process, which is the preceding process of the MTF correction process, continuously performs the MTF correction process in addition to the log conversion process currently performed by the MPU 3 Output the control signal as follows. As a result, the MPU 3 performs the MTF correction process in addition to the Log conversion process.

If there is no MPU with a large processing load (NO in step S02), a control signal OFF indicating that the initialization process is to be performed is output to each of the MPUs 2 to 6 (step S04).

Thereafter, it is determined whether or not processing has been completed for all pixel data (step S05). If there is unprocessed pixel data, the above processing is repeated.
If all the pixel data have been processed, the process ends.

As described above, the processing executed by the MPU having the increased load is performed in parallel with the MPU performing the processing at the preceding stage, so that the load can be distributed and the data processing apparatus as a whole can store the data. Processing speed can be increased.

In the data flow control unit 9, M with a large load
When judging the PU (Step S0 in FIG. 3)
2), by referring to the address of the data to be processed by each of the MPUs 2 to 6;

FIG. 4 is a diagram showing the difference between the address values of the pixel data executed by each MPU. The image data input to the image input device 1 has an address value for each pixel data, and the address values are assigned in the order of input to the image input device 1. This is because the image data input to the image input device 1 is obtained as an address value of the input buffer memory 11 when it is stored in the input buffer memory 11. Each time the processing of the pixel data is completed, each of the MPUs 2 to 6 transmits the address value of the pixel data to the status register 10. The data flow control unit 9 determines an address difference (dif_1, dif_2, dif_3) of pixel data executed by each of the MPUs 2 to 6 from an address value of pixel data executed by each MPU stored in the state register 10. , Dif_4)
Is calculated. If the calculated address difference is smaller than a predetermined set value, it is determined that the load on the MPU preceding the MPU with the reduced address difference has increased. For example, the address value to be executed by the MPU 5 that performs the gamma correction process and the MPU 4 that performs the MTF correction process
Address difference dif_ which is the difference with the address value executed in
When 2 is smaller than a preset threshold value reg_2, it is determined that the load on the MPU 4 that performs the MTF correction process, which is the preceding process, has increased.

Address difference dif_1 indicates an address difference between MPU 6 for performing binarization processing and MPU 5 for performing gamma correction, and dif_2 indicates an address difference between MPU 5 for performing gamma correction processing and MPU 4 for performing MTF correction processing. An address difference is shown, dif_3 is an address difference between MPU4 performing MTF correction processing and MPU3 performing Log conversion processing, and dif_4 is a difference between MPU3 performing Log conversion processing and MPU2 performing SH correction processing. Indicates the address difference. When this address difference is small, it indicates that the load of the preceding MPU is large. Further, when the address difference becomes smaller than the threshold value, the data flow control unit 9 determines that the load of the MPU at the preceding stage has increased. This threshold is determined by the address difference (dif_
1, dif_2, dif_3, dif_4), and are stored in advance in a ROM inside the data flow control unit.

The reason why the threshold value reg differs between MPUs is as follows. For example, when performing a matrix operation including a plurality of pixels in the MTF correction processing as in the processing using the Laplacian filter, a considerable address difference is required. FIG. 5 is a diagram for describing pixel data when performing MTF correction processing using a 3 × 3 filter. Referring to the figure, when the MTF correction processing is performed using a 3 × 3 filter, the Log conversion processing is completed for all the pixels surrounded by a 3 × 3 matrix centering on the pixel to be processed. Need to be. Therefore, in the MTF correction processing, data for one line before and after the pixel to be processed is necessary, and the Log conversion processing, which is the processing before the MTF correction processing, is performed by the address of the pixel to be subjected to the MTF correction processing. And an address difference of (the number of pixels for one line + 1). In consideration of this, the MP that performs the MTF correction process
It is necessary to set a threshold value for an address difference between U4 and the MPU 3 that performs the log conversion process.

Therefore, threshold value reg_1 corresponding to address difference dif_1, threshold value reg_2 corresponding to dif_2, and threshold value reg corresponding to dif_3
_3 and the threshold reg_4 corresponding to dif_4 are 1
As described above, preferably, the threshold value is set to 1.
The threshold value reg_2 corresponding to 2 is equal to or more than (the number of pixels for one line + 1), preferably (the number of pixels for one line + 1).
May be set as the threshold value.

FIG. 6 is a flowchart showing the flow of processing performed in each of MPUs 2 to 6. Referring to the figure,
The MPUs 2 to 6 capture pixel data (step S11). The MPU 2 has an input buffer memory 11
The MPUs 3 to 6 receive the pixel data from the MPUs that perform the preceding processes. For example, MPU3 receives pixel data from MPU2.

Next, it is determined whether a control signal has been received from the data flow control unit 9 (step S1).
2). The control signal received here is either the control signal ON or the control signal OFF. If the received control signal is the control signal ON (YES in step S12),
The program of the subsequent process is loaded from the ROM in the data flow control unit 9, and two processes of the current process (initial setting process) and the subsequent process are executed (step S14).

When the control signal ON is not received, that is, when the control signal OFF is received (step S1).
(NO at 2), currently executing process (initial setting process)
Is executed (step S13). After that, the processed pixel data is output (step S15). The MPUs 2 to 5 deliver the processed pixel data to the MPUs 3 to 6, which execute the subsequent processes. For example, MPU2 is MPU
Then, the processed pixel data is delivered to No. 3. The MPU 6 transfers the processed pixel data to the image output device 7.

Thereafter, the address of the pixel data and the processing time or processing speed of the pixel data are written in the state register 10 (step S16).

Then, it is determined whether or not the processing of all the pixel data has been completed (step S17). If the processing has not been completed, the process proceeds from step S10 to step S10.
The processing up to 16 is repeated, and when the processing of all the pixel data is completed, the processing is completed.

The initial setting process and the subsequent process here are, for example, in the MPU 3, the initial setting process is a Log conversion process, and the subsequent process is an MTF correction process.

FIG. 7 is a diagram showing processing performed by each of the MPUs 2 to 6 when the data flow control unit 9 determines that the load on the MPU 4 is large in the data processing apparatus according to the present embodiment. Referring to FIG.
In 3, the MTF correction process is executed in addition to the Log conversion process. The flow of the pixel data in this state is a first flow in which the MPU 2 performs the SH correction processing on the pixel data, and the MPU 3 performs the log conversion processing and the MTF processing.
A correction process is performed, and then the data is transferred to the MPU 5 and subjected to a gamma correction process. As a second flow, MPU2
The pixel data that has been subjected to the SH correction processing at L
After only the OG conversion process is performed, the MTF is transferred to the MPU 4 and subjected to the MTF correction process. Thereafter, the MTF is transferred to the MPU 5 and subjected to the gamma correction process.

As described above, the data processing device according to the present embodiment uses
2 to 6 are constantly monitored, and the processing performed by the MPU with the large load is executed in parallel in addition to the processing currently performed on the MPU preceding the MPU determined to have the large load. Therefore, the load is distributed among the MPUs 2 to 6, and as a result, the data processing speed of the entire data processing device can be increased.

In the present embodiment, the data flow control unit 9 constantly monitors the load of each of the MPUs 2 to 6, and the MPU executes the processing preceding the processing executed by the MPU determined to have a large load. On the other hand, in addition to the processing currently being performed, the processing executed by the MPU having a large load is also executed in parallel.
The processing executed by the MPU with a large load may be executed in parallel with the processing currently executed for the MPU executing the processing at the later stage of the processing executed by the MPU. As described above, by changing the processing executed by the MPUs 2 to 6 in the data flow control unit 9, the load can be distributed among the MPUs 2 to 6, and the data processing speed of the entire data processing apparatus can be increased. it can.

In this case, the processing of the data flow control unit 9 is performed in step S03 of FIG.
A control signal ON is output to the MPU performing the subsequent processing of the PU so that the processing executed by the MPU having a large load is continued in addition to the processing currently being performed (step S03). For example, referring to FIG. 1, when the load on MPU 4 performing the MTF correction processing increases, data flow control unit 9 determines the status of MPU 4 based on the status of status register 10.
When the MPU 5 detects that the load on the MPU 5 has increased, and performs the gamma correction process that is the latter stage of the MTF correction process, the MPU 5 performs the MTF correction process in addition to the gamma correction process currently performed by the MPU 5. Outputs control signal. Thus, the MPU 3 performs the MTF correction processing and the gamma correction processing.

On the other hand, in the processing of MUP3 to MUP6, in step S13 of FIG.
In the case of (1), the program of the preceding stage is loaded from the ROM in the data flow control unit 9 in step 14, and the process of the present stage (initial setting process) and the preceding stage is executed.
Two processes are executed (step S14).

FIG. 8 shows the state of the processing executed by the MPUs 2 to 6 when the data flow controller 9 determines that the load on the MPU 4 is large in the data processing apparatus in this case. Referring to FIG. 8, in MPU 5, MT
The F correction processing and the gamma correction processing are performed. Also,
The flow of pixel data in this state is as a first flow,
The pixel data subjected to the log conversion processing by the MPU 3 is M
The PU 4 performs an MTF correction process, and then is delivered to the MPU 5 to perform a gamma correction process. As a second flow, the pixel data that has been subjected to the Log conversion processing in the MPU 3 is transferred to the MPU 5 and subjected to the MTF correction processing and the gamma correction processing.

[Second Embodiment] FIG. 9 is a block diagram schematically showing a data processing apparatus according to a second embodiment. Referring to the figure, a data processing device according to a second embodiment is an image input device 1 for inputting image data.
MPUs 21 to 26 for performing various processes on the input image data for each pixel data, an image output device 8 for outputting the processed image data to a recording medium such as paper, an image input device 1, and an MPU 21 to 26. , A status register 10 for monitoring the operation status of the image output device 8, and a status register 10
, A data flow control unit 20 for controlling the operation of the MPUs 21 to 26, an input buffer memory 11 for temporarily storing the image data input by the image input device 1, and a temporary storage for the image data output from the image output device. And an output buffer memory 12 for storing.

The MPUs 21 to 25 perform SH correction processing, Log conversion processing, MTF correction processing, gamma correction processing, and binarization processing in the initial setting state. MPU2
No. 6 performs no processing in the initial setting state.

The data processing apparatus according to the second embodiment performs the processing executed by the data flow control unit 20 on the MPU of which the load is large among the MPUs 21 to 25.
26 is executed in parallel.

FIG. 10 is a flowchart showing a flow of processing performed by data flow control unit 20 in the second embodiment. Referring to the figure, the data flow control unit 20
Acquires the address of the pixel data to be executed by each MPU stored in the status register 10 (step S3).
1). An address difference is obtained from the address value of the pixel data executed by each MPU obtained from the status register, and an MPU having a large load is detected from the obtained address difference (step S32). If it is determined that there is an MPU having a large load (YES in step S32), the control signal is set to M to perform processing to be executed by the MPU determined to have a large load.
Output to the PU 26 (step S33).

On the other hand, when it is determined that there is no MPU having a large load (NO in step S32), a control signal is output to MPU 26 to reset (step S3).
4).

Thereafter, it is determined whether or not all pixel data has been processed (step S35). If there is unprocessed pixel data, the above processing is repeated. To end.

FIG. 11 is a flowchart showing the flow of processing performed by MPU 26. Referring to FIG.
Then, a control signal output from the data flow control unit is received (step S41). The control signal received here is
The control signal is either a control signal indicating that processing with a large load is performed or a control signal indicating resetting.

Next, it is determined whether or not the received control signal is a reset signal (step S42). If the received control signal is a reset signal, reset processing is performed so that no processing is performed (step S42). S44), and proceed to step S47.

On the other hand, if it is determined that the signal is not a reset signal, that is, if a control signal indicating that processing with a heavy load is to be performed is received (NO in step S42), the program of the processing with the heavy load is loaded into the data. The data is loaded from the ROM in the flow control unit 20, and the processing is executed (step S43).

Then, the processed pixel data is output (step S45). In this case, for example, when the processing determined to have a large load is the binarization processing, the processed pixel data is output to the image output device 8. In the case of other processing, the data is delivered to the MPU executing the subsequent processing. For example, when the processing determined to have a large load is the MTF correction processing, the data is transferred to the MPU 5 that executes the gamma correction processing, which is the subsequent processing. FIG. 12 shows that the data flow control unit 20 uses the MTF
FIG. 7 is a diagram illustrating processing performed by each of the MPUs 21 to 26 when the load on the MPU 23 that performs the correction processing is determined to be large. Referring to the drawing, MPU 26 receives a control signal output from data flow control unit 20 indicating that an MTF correction process is to be performed, and outputs an RO in data flow control unit 20.
The MTF correction processing program is loaded from M
Correction processing is performed. In this case, the flow of the pixel data includes the flow in which the pixel data subjected to the log conversion processing in the MPU 22 is transferred to the MPU 23 and the flow of the MPU 26.
There are two of the flows handed over to. MPU23 or MP
The pixel data transferred to U26 is subjected to MTF correction processing and then transferred to MPU24.

As described above, the data processing apparatus according to the second embodiment is provided with the MPU 26 that performs no processing in the initial setting state,
The processing executed by the MPU determined to have a large load is executed in parallel by the MPU 26 that does not perform any processing.
Since data can be distributed between 1 and 26, the speed of data processing can be increased as a whole of the data processing apparatus.

[Third Embodiment] FIG. 13 is a block diagram schematically showing a data processing apparatus according to the third embodiment. The data processing device according to the third embodiment includes an image input device 1 that inputs image data, and an M that performs various processes on the input image data for each pixel data.
PU 31 to 35, an image output device 8 for outputting processed image data to a recording medium such as paper, an image input device 1,
MPUs 31 to 35, a status register 10 for monitoring the operation status of the image output device 8, and M
Data flow control unit 3 for controlling operations of PUs 31 to 35
0, an input buffer memory 11 for temporarily storing image data input by the image input device 1, an output buffer memory 12 for temporarily storing image data output from the image output device, and pixel data processed by each MPU 31. And intermediate buffer memories 13 to 17 for storing.

The data processing device according to the third embodiment can temporarily store the pixel data processed by the MPUs 31 to 35 in the corresponding intermediate buffer memories 13 to 17, respectively. In the initial setting state, the MPU 31 performs SH correction processing, the MPU 32 performs Log conversion processing,
U33 is set to perform MTF correction processing, MPU34 is to perform gamma correction processing, and MPU35 is to be set to perform binarization processing. The intermediate buffer memory 13 stores the pixel data subjected to the SH correction processing, the intermediate buffer memory 14 stores the pixel data subjected to the Log conversion processing, and the intermediate buffer memory 15 stores the pixel data subjected to the MTF correction processing. The memory 16 stores pixel data subjected to gamma correction processing, and the intermediate buffer memory 17 stores pixel data subjected to binarization processing.

FIG. 14 is a flowchart showing a flow of processing performed by data flow control unit 30 in the third embodiment. Referring to the figure, data flow control unit 30 has MPUs 31 to 35 stored in status register 10.
From the address value of the pixel data processed in
The loads of U2 to U6 are monitored (step S51). It is determined from the acquired address values of the pixel data to be executed by the MPUs 2 to 6 whether there is an MPU having a large load (step S52).

When it is determined that there is an MPU having a large load, a control signal is output to an MPU executing a process subsequent to the process having the large load so as to perform the process having the large load. Is performed (step S53). On the other hand, when it is determined that there is no MPU with a large load (NO in step S52), a control signal is output to reset all MPUs (step S5).
4).

Then, it is determined whether or not processing has been completed for all pixel data (step S55). If there is unprocessed pixel data, the above processing is repeated.
When the processing of all the pixel data ends, the processing ends.

FIG. 15 shows the MP according to the third embodiment.
It is a flowchart which shows the flow of a process performed in U31-35. Referring to the figure, MPUs 31 to 35 receive a control signal output by data flow control unit 30 (step S61). The control signal received here is either a control signal indicating that the process determined to have a large load is performed or a control signal indicating reset.

It is determined whether or not the control signal received in step S70 is a control signal for instructing reset (step S62). If the control signal is not a control signal for instructing reset, the control signal is for instructing execution of a process with a large load. Therefore, a program for a process with a large load is loaded from the ROM in the data flow control unit 30, and the loaded program is executed. (Step S64).

If the received control signal is a control signal for instructing reset (YES in step S62), an initial setting process is executed (step S63). here,
Once the control signal instructing the execution of the heavy load process has been received and the heavy load process has already been executed, when the control signal indicating the reset is received, the execution of the heavy load process is stopped, Resume execution of the initialization process. For example, M
When it is determined that the load on the MPU 33 that performs the TF correction process is large, and a control signal is output to the MPU 34 to perform the MTF correction process, the MPU 34 stops performing the gamma correction process, which is the initial setting process. Execute MTF correction processing. Thereafter, when the load on the MPU 33 is reduced, the data flow control unit 30 outputs a control signal for instructing the MPU 34 to reset. MPU3
4 receives the control signal instructing the reset,
The F correction processing is stopped and the gamma correction processing, which is the initial setting processing, is restarted.

Next, the processed pixel data is output (step S65). The output of the pixel data is performed to the intermediate buffer memories 13 to 17. In each of the intermediate buffer memories 13 to 17, the pixel data to be stored is determined.
When performing the TF correction processing, the pixel data subjected to the MTF correction processing is output to the intermediate buffer memory 15.

Next, the address of the pixel data processed by the MPUs 31 to 35 and the processing time or processing speed required for processing the pixel data are written to the status register 10 (step S66). Thereafter, it is determined whether or not processing has been completed for all pixel data (step S67). If there is unprocessed pixel data, the above processing is repeated, and processing has been completed for all pixel data. If so, the process ends.

FIG. 16 shows that the data flow control unit 30
MPUs 31 to 35 when the load of U33 is determined to be large
It is a figure which shows the state of the process performed in. Referring to FIG. 16, MPU 34 loads an MTF correction processing program from the ROM in data flow control unit 30 by receiving a control signal instructing execution of a preceding process output from data flow control unit 30 and loads the MTF correction program. Correction processing is performed. Similarly, the MPU 35 loads the gamma correction processing program from the ROM in the data flow control unit 9 by receiving the control signal instructing to execute the preceding process output from the data flow control unit, and executes the gamma correction processing. You. At this time, the MPU 34 uses the intermediate buffer memory 1
4, the MTF correction processing is performed by reading the pixel data subjected to the Log conversion processing, and the pixel data after the MTF correction processing is written to the intermediate buffer memory 15. Also, MPU3
In step 5, the pixel data subjected to the MTF correction processing is read from the intermediate buffer memory 15 and subjected to the gamma correction processing.
The pixel data after the gamma correction processing is stored in the intermediate buffer memory 1
Write to 6.

As described above, the data processing device according to the third embodiment includes an intermediate buffer memory 1 for storing processed pixel data in each of MPUs 31 to 35.
3 to 17 are provided, and when the data flow control unit 20 determines that there is an MPU having a large load, the MPU executing the subsequent processing of the heavy load processing executes the preceding processing. In the data processing apparatus, the speed of data processing can be increased as a whole. In addition, since the processing can be completed earlier in the earlier processing, new image data, for example, image data of the next page can be input faster.

Further, since the intermediate buffer memories 13 to 18 for storing the results of the processing executed by each MPU are provided,
It is possible to absorb a difference in processing speed between the MPUs 31 to 35 that execute processing asynchronously, and
Even if there is a change in the content of the process executed in ~ 35,
Since the types of pixel data stored in the intermediate buffer memories 13 to 18 do not change, the contents of the processing executed by the MPUs 31 to 35 can be easily changed.

[Fourth Embodiment] FIG. 17 is a block diagram schematically showing a data processing apparatus according to a fourth embodiment. Referring to the figure, a data processing device according to a fourth embodiment is an image input device 1 for inputting image data.
MPUs 41 to 46 for performing various processes on the input image data for each pixel data, an image output device 8 for outputting the processed image data to a recording medium such as paper, an image input device 1, and MPUs 41 to 46. , A status register 10 for monitoring the operation status of the image output device 8, and a status register 10
, A data flow control unit 40 for controlling the operation of the MPUs 41 to 46, an input buffer memory 11 for temporarily storing image data input by the image input device 1, and a temporary storage for image data output from the image output device. And an output buffer memory 12 for storing.

The MPUs 41 to 45 perform SH correction processing, area discrimination processing, color conversion processing,
MTF correction processing and gamma correction processing are performed. MPU46
Performs no processing in the initial setting state.

The data processing apparatus according to the fourth embodiment performs the processing executed by the data flow control unit 40 on the MPU whose load is large among the MPUs 41 to 45.
46 is executed in parallel. In addition,
The data processing device according to the fourth embodiment is different from the data processing devices according to the above-described embodiments in that color image data is handled, and that a region determination process is added to a process performed on pixel data.

The area discrimination processing is to perform a predetermined processing on a plurality of pixel data included in a predetermined area including image data to be processed, thereby to determine an attribute of the predetermined area and to determine a pixel to be processed. This is a process of determining the attribute of the area to which the data belongs. The attribute of the predetermined area is, for example,
There are a character area, a line drawing area, a base area, and the like. This area determination processing is performed by a known method, for example, by using a 3 × 3 matrix and comparing pixel data existing in the matrix.

Then, the time required for the subsequent processing, for example, the MTF correction processing, changes for the pixel data whose attribute has been determined by the area determination processing. For example, when the attribute of the pixel data is determined to be the character attribute or the line drawing attribute by the region determination process, the time required for the MTF correction process is longer than that when the attribute is determined to be the background attribute. As a result, the load on the MPU that executes the MTF correction processing increases. Therefore, the subsequent processing (Log conversion, MTF correction, gamma correction, binarization) is performed based on the result of the area determination processing.
Can be predicted.

In the data processing apparatus according to the fourth embodiment, the processing executed by the MPUs 41 to 46 is changed according to the attribute of pixel data determined by the area determination processing.

FIG. 18 is a flowchart showing a flow of processing performed by data flow control section 40 in the fourth embodiment. Referring to the figure, the data flow control unit 40
Acquires the result of the area determination process executed by the MPU 42 (step S71). It is determined whether or not the pixel data has a character attribute or a line drawing attribute from the result of the area determination processing of the obtained pixel data (step S72). If it is determined that the attribute is a character attribute or a line drawing attribute, a control signal is output to the MPU 46 to perform the MTF correction process (step S73). On the other hand, if the character attribute or the line drawing attribute is not determined (NO in step S72), the MPU 4
Then, a control signal is output to reset the control signal No. 6 (step S74). Thereafter, it is determined whether or not processing of all pixel data has been completed (step S75). If there is unprocessed pixel data, the above processing is repeated, and processing has been completed for all pixel data. In this case, the process ends.

FIG. 19 shows the MP in the fourth embodiment.
It is a flowchart which shows the flow of the process performed by U46.
Referring to the figure, in the MPU 46, the data flow control unit 4
0 is received (step S8).
1). The control signal received here is either a control signal indicating execution of the MTF correction process or a control signal indicating resetting.

Next, it is determined whether or not the received control signal is a reset signal (step S82). If the received control signal is a reset signal, reset processing is performed so that no processing is performed (step S82). S84), and proceed to step S87.

On the other hand, if it is determined that the received signal is not a reset signal, that is, if a control signal indicating that processing with a large load is to be performed is received (NO in step S82), M
The program for the TF correction processing is loaded from the ROM in the data flow control unit 40, and the processing is executed (step S83). Then, the processed pixel data is output (step S85). In this case, the pixel data is transferred to the MPU 45 that executes the latter stage of the MTF correction process. Next, the address of the pixel data processed by the MPU 46 and the processing time or processing speed required for processing the pixel data are written into the status register 10 (step S8).
6).

Thereafter, it is determined whether or not the processing has been completed for all pixel data (step S8).
7) If there is unprocessed pixel data, the above process is repeated, and if the process has been completed for all pixel data, the process ends.

FIG. 20 shows an MPU 4 for performing the area determination processing.
FIG. 6 is a diagram illustrating a process performed by the MPU when it is determined that the pixel data to be processed in step 2 is a character attribute or a line drawing attribute. Referring to the figure, MPU 46 receives a control signal output from data flow control unit 40 and indicating the execution of MTF correction processing, and executes MTF correction processing.
In this case, there are two flows of the pixel data: a flow in which the pixel data subjected to the color conversion in the MPU 43 is transferred to the MPU 44 and a flow in which the pixel data is transferred to the MPU 46.
The pixel data transferred to the MPU 44 or MPU 46 is subjected to MTF correction processing, and then transferred to the MPU 45 that executes gamma correction processing.

When the pixel data is determined to have the character attribute or the line drawing attribute in the area determination processing, the pixel data near the pixel data usually have the same attribute. Therefore, the processing executed by the MPUs 41 to 46 shown in FIG. 20 continues while the pixel data processed by the MPU 42 executing the area determination processing is determined to have the character attribute or the line drawing attribute. When the pixel data is determined not to have the character attribute or the line drawing attribute by the area determination processing, the MPUs 41 to 46 execute the processing of the initial setting. That is, the MPU 46 does not perform any processing.

As described above, the data processing apparatus according to the fourth embodiment performs the MP
If it is determined in U42 that the pixel data has the character attribute or the line drawing attribute, no processing is performed in the initial setting state.
Since the PU 46 performs the MTF correction processing in which the load is predicted to be large, the loads in the MPUs 41 to 45 can be distributed among the MPUs 41 to 46. As a result, depending on the attribute of the data input to the data processing device,
Data processing can be performed at high speed by dynamically changing the processing executed by the MPUs 41 to 46.

[Fifth Embodiment] FIG. 21 is a block diagram schematically showing a data processing apparatus according to a fifth embodiment. Referring to the figure, a data processing device according to a fifth embodiment is an image input device 1 for inputting image data.
MPUs 51 to 56 for performing various processes on the input image data for each pixel data, an image output device 8 for outputting the processed image data to a recording medium such as paper, an image input device 1, and MPUs 51 to 56 , A status register 10 for monitoring the operation status of the image output device 8, and a status register 10
, A data flow control unit 50 for controlling the operations of the MPUs 51 to 56, an input buffer memory 11 for temporarily storing image data input by the image input device 1, and a temporary storage for image data output from the image output device. An output buffer memory 12 for storing the image data and intermediate buffer memories 13 to 18 for storing the pixel data processed by the MPUs 51 to 56 are included.

The data processing device according to the fifth embodiment can temporarily store pixel data processed by the MPUs 51 to 56 in the corresponding intermediate buffer memories 13 to 18. In the initial setting state, the MPU 51 performs the SH correction process, the MPU 52 performs the region determination process,
53 is set to perform Log conversion processing, MPU 54 to perform MTF correction processing, MPU 55 to perform gamma correction processing, and MPU 56 to perform binarization processing.

The intermediate buffer memory 13 stores the pixel data subjected to the SH correction processing, the intermediate buffer memory 14 stores the pixel data subjected to the area determination processing, and the intermediate buffer memory 15 stores the pixel data subjected to the Log conversion processing. ,
The intermediate buffer memory 16 stores the pixel data subjected to the MTF correction processing, the intermediate buffer memory 17 stores the pixel data subjected to the gamma correction processing, and the intermediate buffer memory 18.
Stores pixel data subjected to the binarization processing.

Since the area discrimination processing has been described in the fourth embodiment, the description will not be repeated here.
The data processing device according to the fifth embodiment determines the subsequent processing (Log conversion, MTF
The processing executed by the MPUs 51 to 56 is dynamically changed by predicting the load of the MPU that executes the correction, the gamma correction, and the binarization.

FIG. 22 is a flowchart showing a flow of processing performed by data flow control unit 50 according to the fifth embodiment. Referring to the figure, the data flow control unit 9
The result of the area determination processing executed in U52 is obtained (step S90). As a result of the region determination processing acquired in step S90, it is determined whether the processed pixel data has a character attribute or a line drawing attribute (step S91). If it is determined that the pixel data has the character attribute or the line drawing attribute (YES in step S91), a process subsequent to the MTF correction process (gamma correction process, binarization process) is executed.
A control signal is output to the PUs 55 and 56 so as to execute the preceding process. That is, a control signal is output to the MPU 55 that executes the gamma correction process so as to execute the MTF correction process that is the preceding stage of the gamma correction process, and the MPU 56 that executes the binarization process is binary. A control signal is output so as to perform a gamma correction process, which is a process preceding the conversion process.

On the other hand, if the pixel data is not determined to have the character attribute or the line drawing attribute (N in step S91)
O), a control signal is output to the MPUs 55 and 56 to reset them (step S93).

Thereafter, it is determined whether or not processing of all pixel data has been completed (step S94). If there is unprocessed pixel data, the above processing is repeated, and processing has been completed for all pixel data. If so, the process ends.

FIG. 23 shows the MP in the fifth embodiment.
It is a flowchart which shows the flow of a process performed by U51-56. Referring to the figure, the MPUs 55 and 56 receive a control signal output by the data flow control unit 40 (Step S101). The control signal received here is either a control signal indicating execution of the preceding process or a control signal indicating reset.

If the received control signal is not a control signal indicating reset (NO in step S102), the received control signal is a control signal indicating execution of the preceding process, so that MPUs 55 and 56 perform data flow control. R in 50
The processing program of the preceding stage is loaded from the OM, and the MTF correction processing is executed (step S84). MPU55 is MT
The F correction processing program is loaded, and the MPU 56 loads the gamma correction processing program. On the other hand, if the received control signal is a control signal indicating reset (step S
If YES in step 102, a reset process is performed to execute the process of the initial setting (step S103).

When the processing is completed, the processed pixel data is output (step S106). MPU 55, 56
Indicates that the pixel data is written into the intermediate buffer memory 16 when the MTF correction processing is being executed, and the pixel data is written into the intermediate buffer memory 1 when the gamma correction processing is being executed.
7 and the pixel data is written to the intermediate buffer memory 18 when the binarization process is executed.

Next, the address of the pixel data processed by the MPUs 55 and 56 and the processing time or processing speed required for processing the pixel data are written in the status register 10 (step S106). Thereafter, it is determined whether or not the processing has been completed for all pixel data (step S107). If there is unprocessed pixel data, the above processing is repeated, and the processing is completed for all pixel data. If so, the process ends.

The data processing device according to the present embodiment
The MPUs 51 to 56 load an initial setting processing program and execute processing for each pixel data. MPU5
5 and the MPU 56, initially, the processing program of the initial setting is loaded from the ROM in the data flow control unit 50 and executed, but the control signal instructing the execution of the processing at the preceding stage is received from the data flow control unit 50. in case of,
The program for the preceding process is loaded from the ROM in the data flow control unit 50, and the program is executed.

FIG. 24 shows that the data flow control unit 50
FIG. 19 is a diagram illustrating processing performed by MPUs 51 to 56 when pixel data is determined to be a character attribute or a line drawing attribute from U52. Referring to the figure, MPU 55 executes MTF correction processing, and MPU 56 executes gamma correction processing. At this time, in the MPU 55, the pixel data to be processed is read out from the intermediate buffer memory 15, and the MTF 55
The data after the correction processing is written to the intermediate buffer memory 16. In the MPU 56, the pixel data to be processed is read from the intermediate buffer memory 16, and the pixel data after the gamma correction processing is written to the intermediate buffer memory 17.

As described above, in the data processing apparatus according to the fifth embodiment, the MPU 52 that performs the area determination processing determines whether the pixel data has the character attribute or the line drawing attribute, and the determination result is the data flow control unit 50. Sent to When the pixel data is determined to be a character or a line drawing attribute based on the determination result sent from the MPU 52, the data flow control unit 50 executes the MTF correction processing by the MPU 55 and the gamma correction processing by the MPU 56. To M
A control signal is output to the PU 55 and the MPU 56. If it is determined that the pixel data is not a character attribute or a line drawing attribute, a signal indicating reset is output to the MPU 55 and the MPU 56, and the MPU 55 performs gamma correction processing and the MPU 56 performs binarization processing.

As described above, the data processing device according to the fifth embodiment determines the attribute of the pixel data to be processed, and executes the subsequent processing.
PU load is predicted, and each MPU according to the predicted load.
Since the processing to be executed is dynamically changed, the data processing speed of the entire data processing apparatus can be improved.

Further, since the intermediate buffer memories 13 to 18 for storing the results of the processing executed by each MPU are provided, it is possible to absorb the difference in the different processing speed among the MPUs 51 to 56 which execute the processing asynchronously. , And MPU51-
Even if there is a change in the content of the process executed in 56, the type of pixel data stored in the intermediate buffer memories 13 to 18 does not change, so that the content of the process executed in the MPUs 51 to 56 can be easily changed. it can.

[Sixth Embodiment] FIG. 25 is a block diagram schematically showing a data processing apparatus according to a sixth embodiment. Referring to the figure, a data processing device according to a sixth embodiment is an image input device 1 for inputting image data.
MPUs 61 to 65 for performing various processes on the input image data for each pixel data, an image output device 8 for outputting the processed image data to a recording medium such as paper, an image input device 1, and MPUs 61 to 65 , A status register 10 for monitoring the operation status of the image output device 8, and a status register 10
, A data flow control unit 60 for controlling the operation of the MPUs 61 to 65, an input buffer memory 11 for temporarily storing image data input by the image input device 1, and a temporary storage for image data output from the image output device. An output buffer memory 12 for storing the image data and intermediate buffer memories 13 to 17 for storing the pixel data processed by the MPUs 61 to 65 are included.

The data processing device according to the sixth embodiment can temporarily store the pixel data processed by the MPUs 61 to 65 in the corresponding intermediate buffer memories 13 to 17, respectively. In the initial setting state, the MPU 61 performs SH correction processing, the MPU 62 performs Log conversion processing,
U63 is set to perform MTF correction processing, MPU64 is to perform gamma correction processing, and MPU65 is to be set to perform binarization processing.

The intermediate buffer memory 13 stores the pixel data subjected to the SH correction processing, the intermediate buffer memory 14 stores the pixel data subjected to the Log conversion processing, and the intermediate buffer memory 15 stores the pixel data subjected to the MTF correction processing. The intermediate buffer memory 16 stores gamma-corrected pixel data, and the intermediate buffer memory 17 stores binarized pixel data.

FIG. 26 shows the MP in the sixth embodiment.
It is a flowchart which shows the flow of a process performed in U61-65. MPU that passes data to simplify explanation
The processing in the MPU 61 and the MPU 62 is shown in a form for simultaneous explanation. Actually, the MPU 61 and the MPU 62 execute processing asynchronously.

Referring to FIG. 26, MPU 61 executes SH correction processing (processing A) for each pixel data (step S111). At this time, the data flow control unit 60 monitors the load on the MPU 61 and the MPU 62,
The load of the SH correction processing performed by the MPU 61 and the MPU 62
The load of the log conversion processing (processing B) performed in step (S112) is compared (step S112). Is determined (step S113). If the memory capacity is left in the intermediate buffer memory 13 (YES in step S113), M
The pixel data subjected to the SH correction processing executed by the PU 61 is written in the intermediate buffer memory 13 (step S11).
4). The pixel data stored in the intermediate buffer memory 13 is read by the MPU 62 which performs the next log conversion process (step S115), and the MPU 62 performs the log conversion process (step S116).

On the other hand, when the load of the SH correction processing is not smaller than the load of the Log conversion processing (N in step S112)
In O), the pixel data after the SH correction processing executed by the MPU 61 is directly delivered to the MPU 62 and
An og conversion process is performed (step S116).

Next, it is determined whether all the pixel data for one page has been processed (step S117). If there is any unprocessed pixel data, the above processing is repeated.
When the processing of all the pixel data is completed, it is determined whether or not the pixel data subjected to the SH correction processing executed by the MPU 61 is stored in the intermediate buffer memory 13 (step S118). S in the intermediate buffer memory 13
If the H-corrected pixel data is stored (NO in step S118), the data flow control unit 60
The MPU 2 outputs a control signal instructing the MPU 61 to execute the log conversion process, and the MPU 2 loads the log conversion process program from the ROM in the data flow control unit 60 in response to the reception of the control signal to execute the log conversion process. Execute (Steps S119 and S120). At this time,
The same Log conversion processing is performed in parallel by the MPU 61 and the MPU 62.

In the MPU 61, the intermediate buffer memory 13
The pixel data is read out (step S119), and the
After executing the conversion process (Step S120), the pixel data after the Log conversion process is stored in the intermediate buffer memory 14 (Step S121).

In parallel with the Log conversion processing performed by the MPU 61, the MPU 62 reads pixel data from the intermediate buffer memory 13 (Step S122), performs the Log conversion processing (Step S123), and executes the pixel data after the Log conversion processing. Is written into the intermediate buffer memory 14 (step S124).

As described above, the same Log conversion processing is executed in parallel by the MPU 61 and the MPU 62, and this parallel processing is repeated until there is no more pixel data stored in the intermediate buffer memory 13.

FIG. 27 shows that the load of the MPU 61 is
61 and MP when the load is equal to or greater than
FIG. 14 is a diagram for explaining data transfer with U62. Referring to the figure, pixel data subjected to SH correction processing by MPU 61 is directly delivered to MPU 2 without being stored in intermediate buffer memory 13. This is MPU61
This is because the load is greater, and when the processing for one pixel data is completed in the MPU 61, the processing is completed in the MPU 62 and the MPU 62 is in a waiting state.

FIG. 28 shows that the load of the MPU 61 is
FIG. 6 is a diagram for explaining data transfer between MPU1 and MPU2 when the load is smaller than the load of FIG. S by MPU1
The pixel data subjected to the H correction processing is stored in the intermediate buffer memory 13 without being directly delivered to the MPU 2. By doing so, the MPU 61 that performs the SH correction processing with a small load can execute the SH correction processing without synchronizing with the processing of the MPU 62.

FIG. 29 shows the MPU 61 and the MPU 6 when the SH correction processing is completed in the MPU 61 and the pixel data after the SH correction processing is stored in the intermediate buffer memory 13.
FIG. 3 is a diagram for explaining a process executed in Step 2 and a flow of pixel data. Referring to the figure, as described above, the MPU 61 completes the SH correction processing, and stores the SH in the intermediate buffer memory 13.
If the pixel data after the correction processing is stored, M
The PU 61 and the MPU 62 execute the same Log conversion processing in parallel. In the MPU 61, the intermediate buffer memory 1
3, the pixel data after the processing is written into the intermediate buffer memory 14 after the data is read out and subjected to the log conversion processing. In the MPU 2, data is read from the intermediate buffer memory 13, subjected to Log conversion processing, and then the processed data is transferred to the next MPU.

As described above, in the data processing device according to the sixth embodiment, the intermediate buffer memories 13 to 13 that store the processed pixel data for each of the MPUs 61 to 65
17 is provided, and when the load of the MPU executing the subsequent processing is heavy, the processed pixel data is stored in the intermediate buffer memories 13 to 17 without being directly transferred to the subsequent processing. If the pixel data still exists in the intermediate buffer memories 13 to 17 even if the preceding process is completed for all the pixel data, the intermediate buffer memory 1
2 to the pixel data stored in 3 to 17
Since the subsequent processing is executed in parallel by PU,
The earlier the processing, the faster the processing can be completed, and the speed of data processing as a whole of the data processing apparatus can be increased. In addition, since the processing can be completed earlier in the earlier processing, new image data, for example, image data of the next page can be input faster.

Further, the intermediate buffer memories 13 to 17 for storing the results of the processing executed by each MPU are provided.
The difference in processing speed between the MPUs 2 to 7 that execute processing asynchronously can be absorbed, and even if the content of the processing to be executed by the MPUs 2 to 7 is changed, the intermediate buffer memories 13 to 18 can be used. Since the type of the stored pixel data does not change, the contents of the processing executed by the MPUs 61 to 65 can be easily changed.

It is to be noted that the above-described MPU may be replaced with a plurality of devices. Further, the processing performed by the data flow control unit, the status register, and each MPU described above,
For example, the data flow control unit is shown in FIGS.
0, the processing procedure shown in FIG. 14, FIG. 18, and FIG.
Can be described by a program for causing a computer to execute the processing procedures shown in FIGS. 6, 11, 15, 19, 23, and 26. When the processing performed by the data flow control unit, the status register, and each MPU is described by a program for causing a computer to execute the invention, the invention can be regarded as a computer-readable recording medium on which the program is recorded. .

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically illustrating a data processing device according to a first embodiment.

FIG. 2 is a diagram for explaining a procedure of transferring pixel data between an MPU executing a preceding process and an MPU executing a subsequent process.

FIG. 3 is a flowchart showing a flow of processing performed by a data flow control unit 9 according to the first embodiment.

FIG. 4 is a diagram for explaining addresses of pixel data processed by the MPU and differences between the addresses.

FIG. 5 is a diagram for explaining pixel data used for MTF correction processing.

FIG. 6 is a flowchart showing a flow of processing performed by MPUs 2 to 6 in the first embodiment.

FIG. 7 is a first block diagram illustrating processing performed by MPUs 2 to 6 when an MPU having a large load is detected by data flow control unit 9;

FIG. 8 is a second block diagram illustrating processing performed by MPUs 2 to 6 when an MPU having a large load is detected by data flow control unit 9;

FIG. 9 is a block diagram schematically illustrating a data processing device according to a second embodiment.

FIG. 10 is a flowchart showing a flow of processing performed by a data flow control unit 20 according to the second embodiment.

FIG. 11 is a flowchart showing a flow of processing performed by an MPU 26 according to the second embodiment.

FIG. 12 is a diagram illustrating an MPU when a large load MPU is detected by the data flow control unit 20 according to the second embodiment;
It is a block diagram which shows the process performed in 21-26.

FIG. 13 is a block diagram schematically illustrating a data processing device according to a third embodiment.

FIG. 14 is a flowchart showing a flow of processing performed by a data flow control unit 30 according to the third embodiment.

FIG. 15 illustrates MPUs 31 to 35 according to the third embodiment.
FIG. 6 is a flowchart showing a flow of processing performed in step S1.

FIG. 16 is a diagram illustrating an MPU when a large load MPU is detected by the data flow control unit 30 according to the third embodiment.
It is a block diagram which shows the content of the process performed in 31-35.

FIG. 17 is a block diagram schematically illustrating a data processing device according to a fourth embodiment.

FIG. 18 is a flowchart showing a flow of processing performed by a data flow control unit 40 according to the fourth embodiment.

FIG. 19 is a flowchart showing the flow of processing performed by MPU in the fourth embodiment.

FIG. 20 is a diagram illustrating an MPU when an MPU having a large load is detected by the data flow control unit 40 according to the fourth embodiment;
It is a block diagram which shows the process performed in 46.

FIG. 21 is a block diagram schematically illustrating a data processing device according to a fifth embodiment.

FIG. 22 is a flowchart showing a flow of processing performed by a data flow control unit 50 according to the fifth embodiment.

FIG. 23 shows MPUs 51 to 56 according to the fifth embodiment.
FIG. 6 is a flowchart showing a flow of processing performed in step S1.

FIG. 24 is a diagram illustrating an MPU when a large load MPU is detected by the data flow control unit 50 according to the fifth embodiment.
It is a block diagram which shows the process performed in 51-56.

FIG. 25 is a block diagram schematically illustrating a data processing device according to a sixth embodiment.

FIG. 26 shows MPUs 61 to 65 in the sixth embodiment.
FIG. 5 is a flowchart for explaining the processing performed in step (1) and the transfer of data.

FIG. 27 is a block diagram for explaining data transfer when the load on the MPU 61 is equal to or greater than the load on the MPU 62 according to the sixth embodiment.

FIG. 28 is a block diagram for explaining data transfer when the load on the MPU 61 is smaller than the load on the MPU 62 in the sixth embodiment.

FIG. 29 shows how the MPU 61 according to the sixth embodiment performs SH operation.
After the correction process is completed, the intermediate buffer memory 13
MPU when corrected pixel data is stored
FIG. 6 is a block diagram for explaining processing performed by the MPU 61 and MPU 62 and data transfer.

FIG. 30 is a block diagram schematically showing a conventional data processing device.

FIG. 31 is a block diagram for explaining asynchronous processing performed by a plurality of processing blocks.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Image input device 2-6 MPU 8 Image output device 9 Data flow control part 10 Status register 11 Input buffer memory 12 Output buffer memory 13 Image data bus 14, 15 System bus

Claims (14)

[Claims] 1. A data processing system for asynchronously performing a series of a plurality of processes on a plurality of serially input data, a plurality of processing units executing each of the plurality of processes, and the plurality of processes. State monitoring means for monitoring how far each of the plurality of input data has progressed, and detecting a delay processing of which progress is delayed among the plurality of processing; and And a first operation control means for switching a process to be executed by the processing unit. 2. The method according to claim 1, wherein the first operation control means executes processing immediately before the stagnation processing detected by the state monitoring means and executes the processing immediately before the stagnation processing. 2. The data processing system according to claim 1, wherein the processing is switched to two processings. 3. The method according to claim 1, wherein the first operation control means performs the processing to be executed by the delay processing and the immediately after processing on the processing unit which executes the processing immediately after the stagnation processing detected by the state monitoring means. 2. The data processing system according to claim 1, wherein the processing is switched to two processings. 4. A storage unit for storing a result of the processing executed by each of the plurality of processing units, wherein the first operation control unit is provided at a stage subsequent to the delay processing detected by the state monitoring unit. The data processing system according to claim 1, wherein the processing to be executed is switched to the stagnation processing for the processing unit that executes the processing. 5. The plurality of processing units are more than the number of the plurality of processes, and at least a preliminary processing unit that does not execute any of the plurality of processes before the switching of the process by the first operation control unit. Wherein the first operation control means switches the pre-processing unit to execute the delay processing in accordance with a detection result of the state monitoring means. Item 2. The data processing system according to Item 1. 6. The input data has an address indicating an order of the input data, the state monitoring means detects an address of the input data to be processed by each of the plurality of processing units, and Detecting a difference in the address between adjacent processing units in a unit, and, when the detected difference in the address becomes smaller than a predetermined value, performing a process to be executed by a processing unit in a preceding stage of the adjacent processing unit; The data processing system according to any one of claims 1 to 5, wherein the data is detected as: 7. The state monitoring means counts the number of the input data processed by each of the plurality of processing units,
The plurality of processing units detect a difference in the count value between adjacent processing units, and when the detected difference in the count values is smaller than a predetermined value, the difference is executed by a processing unit preceding the adjacent processing unit. Detecting a process as the delay process,
The data processing system according to claim 1. 8. A data processing system for asynchronously performing a series of a plurality of processes on a plurality of serially input data, a plurality of processing units executing each of the plurality of processes, and the plurality of processes. Includes an attribute determination process of detecting an attribute of the input data, and a second operation control unit that switches a process to be executed by the plurality of processing units in accordance with a result of the attribute determination process. system. 9. The second operation control unit includes a prediction unit that predicts a load of the plurality of processes, and executes a process immediately before a load process whose load is predicted to be large by the prediction unit. 9. The data processing system according to claim 8, wherein a process to be executed by the unit is switched to two processes of the immediately preceding process and the load process. 10. The second operation control unit includes a prediction unit that predicts a load of the plurality of processes, and executes a process immediately after the load process whose load is predicted to be large by the prediction unit. 9. The data processing system according to claim 8, wherein a process to be executed by the unit is switched to two processes of the load process and the immediately after process. 11. The plurality of processing units are more than the number of the plurality of processes, and at least a preliminary processing unit that does not execute any of the plurality of processes before switching the processes by the second operation control unit. The second operation control means includes a prediction means for predicting a load of the plurality of processes, and executes the load processing predicted to be large by the prediction means on the preliminary processing unit. 9. The data processing system according to claim 8, wherein the processing is switched to perform the processing. 12. The storage device according to claim 1, further comprising: a storage unit configured to store a result of the processing performed by each of the plurality of processing units; 9. The data processing system according to claim 8, wherein the processing to be executed is switched to the load processing for a processing unit that executes processing subsequent to the load processing whose load is predicted to be large by the prediction unit. . 13. The plurality of processing units deliver the input data after executing the self-process to a processing unit that executes a process immediately after the self-process executed by the self among the plurality of processes. The data processing system according to any one of claims 1 to 3, and 5 to 11, wherein: 14. A data processing system for asynchronously performing a series of a plurality of processes on a plurality of serially input data, a plurality of processing units each executing the plurality of processes, and the plurality of processes. A storage unit for storing a result of the processing performed by each of the units, and the input data to be processed by the processing unit is not present, and
A data processing system comprising: a third operation control unit configured to, when the input data after the execution of the process is stored in the storage unit, switch a process executed by the processing unit to a process immediately after the input unit.