JP2000114097A - Multilayer ceramic capacitors - Google Patents

Abstract

(57) [Problem] To provide a multilayer ceramic capacitor capable of preventing a plating solution from infiltrating into an internal electrode, and preventing a crack from being generated in a wet / medium voltage test and a thermal shock test. SOLUTION: In the multilayer ceramic capacitor 10, the radius of curvature r of the ridge portion of the multilayer body 1 and the thickness t of the dielectric layer 2a (2z) of the outermost layer of the multilayer body 1 are 1 of the radius of curvature r of the roundness of the ridge portion. It is a multilayer ceramic capacitor characterized in that the ratio is 0.2 to 3.3 times.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer ceramic capacitor.

[0002]

2. Description of the Related Art As shown in the sectional view of FIG. 4, a multilayer ceramic capacitor has a first dielectric layer 52.
Laminate 51 on which second internal electrodes 53 and 54 are arranged
And external electrodes 55 and 56 formed on a pair of ends of the laminate 51. The external electrodes 55,
Reference numeral 56 denotes base conductor films 55a and 56a and plating layers 55b and 56b covering the surfaces thereof.

[0003] Out of the laminated body 51, particularly, outermost dielectric layers 52a and 52z serving as upper and lower margins which do not contribute to the generation of the capacitance of the outermost layer (upper and lower surfaces) are arranged. The outermost dielectric layers 52a and 52z are provided to suppress warpage during sintering of the multilayer body 51 and to withstand external stress during handling.

In order to prevent the corners of the laminated body 51 from being chipped or broken due to vibration during transportation or mounting, the ridges are rounded, that is, curved. Have been. This curved surface processing, during the manufacturing process,
By completely exposing the internal electrodes 53 and 54 from predetermined end faces,
They are formed at the same time in a polishing step for stable connection with the external electrodes 55 and 56.

[0005] Then, a pair of ends of the above-mentioned laminated body 51,
That is, as a method of forming the external electrodes on the end faces and on a part of the four faces adjacent to the end faces, the internal electrodes 53 and 54 are stably exposed on the pair of end faces of the laminate 51, and then on both ends, A conductive paste formed by mixing a glass frit, an organic binder, a solvent, and the like is applied to a metal powder (conductive component) such as Ag, Ag-Pd, or Cu, and baked to form underlying conductive films 55a and 56a, and then solder Plating layers 55b and 56b are formed to improve heat resistance.

Here, the glass frit contained in the conductive paste enhances the adhesion between the underlying conductor films 55a and 56a and the interface between the dielectric layers 52 after baking, and the plating solution used in the plating process is Prevents intrusion into the interior.

[0007]

However, in the conventional multilayer ceramic capacitor, as shown in FIGS. 5A and 5B, when the external electrodes 55 are formed on the end face of the laminate 51 and four faces adjacent thereto, Base conductor films 55a, 56a
Has a certain thickness in the plane part,
The thickness varies depending on the end face and the vicinity of the adjacent ridge line.

[0008] Generally, the infiltration of the plating solution is caused by the laminate 51 and the external electrodes 55, 5 on four faces adjacent to the end face of the laminate 51.
6 and the external electrodes 55, 5
It is conceivable that the infiltration directly from the base conductor films 55a and 56a of No. 6 may occur. In the base conductor films 55a and 56a,
There is a hollow hole in the conductor film, and the hole penetrates through the hole.

Accordingly, the underlying conductor films 55a, 56a of the internal electrodes 53, 54 and the external electrodes 55, 56 to which the plating solution is applied.
The smaller the shortest distance between them, the easier it is for the plating solution to enter the internal electrodes 53 and 54.

Further, the thickness of the underlying conductor films 55a and 56a attached to the end face regions of the laminated body 51 varies depending on the surface tension of the conductive paste. The tendency is that the laminate 51 is formed to have a considerable thickness at the center of the end face, but the thickness is reduced in a region outside the end face.

For example, when the thickness t of the dielectric layer 52a located at the outermost layer is small, for example, as shown in FIG. 5B, the base conductor film 55a and the internal electrode 5
3 the distance between the d ₁ is shortened. Thus, becomes easy plating solution infiltrates in this portion d _1, as a result, the insulation resistance characteristic is deteriorated, greatly decreases the reliability of a medium pressure test humidity.

Further, since the internal electrode 53 is simultaneously shaved during barrel polishing after firing, there is also a problem that variations in barrel polishing cause variations in equivalent series resistance (ESR).

On the other hand, when the thickness t of the outermost dielectric layer 2a is large, the distance d ₂ between the underlying conductor film 55a and the internal electrode 53 at the end face of the laminate 1 is increased as shown in FIG. Becomes shorter. When the dielectric layer 2a is thick, the difference in the thermal shrinkage between the outer surface of the dielectric layer 2a and the interface between the internal electrode 53 becomes remarkable. As a result, a thermal shock (ΔT) test (for example, 3
(Soaked in a solder bath at 40 ° C.), there is a problem that cracks are easily generated in the laminate 51.

The present invention has been devised in view of the above-mentioned problems, and has as its object to prevent the plating solution from invading the laminate, suppress fluctuations in characteristics due to variations in barrel polishing,
An object of the present invention is to provide a multilayer ceramic capacitor capable of preventing a crack during a thermal shock test due to a difference in thermal shrinkage.

[0015]

According to the present invention, there is provided a laminated ceramic comprising an outer electrode connected to the internal electrode at a pair of ends of a laminated body in which dielectric layers and internal electrodes are alternately laminated. In the capacitor, the ridge of the laminate is curved, and the thickness t of the outermost dielectric layer of the laminate is 1.2 to 1.2 times the radius of curvature r of the ridge.
It is a multilayer ceramic capacitor characterized by a factor of 3.3.

[0016]

According to the present invention, the ridge portion is rounded due to the curved surface processing of the laminate, and the ridge portion of the outermost dielectric layer of the laminate is also rounded. Then, the thickness t of the outermost dielectric layer of the laminate is equal to the radius of curvature r of the roundness of the ridge line portion.
1.2 to 3.3 times.

As a result, the distance between the internal electrode and the underlying conductive film of the external electrode to which the plating solution is applied can be optimized, so that the plating solution can be prevented from entering the internal electrode, and the impact of barrel polishing can be reduced. As a result, fluctuations in characteristics due to variations in barrel polishing processing are suppressed, and reliability in a thermal shock test and a humidity and pressure resistance test is greatly improved.

This is because the thickness of the outermost dielectric layer of the laminated body, t, and the relationship between the radius of curvature of the ridge portion of the dielectric layer by the curved surface processing are defined, so that the function as the outermost dielectric layer is sufficiently achieved. It can be demonstrated.

It is assumed that the thickness t of the outermost dielectric layer of the laminate is t
However, when the radius of curvature r of the ridge portion is less than 1.2 times, the thickness of the dielectric layer t as the outermost layer of the laminate becomes relatively too thin,
The distance between the internal electrode and the underlying conductive film of the external electrode at the ridgeline portion of the laminate becomes shorter, and the infiltration of the plating solution is more likely to occur. In addition, mechanical stress generated by barrel polishing tends to concentrate on the interface between the dielectric layer and the internal electrode, and the interlayer adhesion decreases. In addition, variations in equivalent series resistance (ESR) also occur due to variations in barrel polishing. In addition, when soldering is performed on a printed wiring board, the thermal stress reaches the internal electrodes, and interlayer delamination or cracking of the multilayer ceramic capacitor occurs.

Conversely, the thickness t of the outermost dielectric layer of the laminate
However, if the radius of curvature exceeds 3.3 times the radius of curvature r, the thickness of the outermost dielectric layer becomes relatively too thick, and the heat between the outer surface of the outermost dielectric layer and the interface between the internal electrode and the internal electrode is relatively large. Since the difference in the shrinkage ratio becomes remarkable, cracks tend to occur in the thermal shock (ΔT) test.

That is, by setting the thickness of the outermost dielectric layer to be 3.3 times or less the radius of curvature of the ridge, the difference in the thermal shrinkage can be reduced, and the thermal shock (ΔT) test Thus, the occurrence of cracks can be suppressed.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a multilayer ceramic capacitor according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is an external perspective view of a multilayer ceramic capacitor 10 of the present invention, FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor of FIG. 1, and FIG. , (B) are cross-sectional views.

In the figure, 10 is a multilayer ceramic capacitor, 1 is a laminate, 2 is a dielectric layer, 3 is a first internal electrode, 4 is a second internal electrode, and 5 is a first internal electrode 3. The first external electrode 6 to be connected is a second external electrode connected to the second internal electrode 4.

The laminate 1 is formed by laminating a plurality of dielectric layers 2 made of a dielectric ceramic material such as barium titanate and strontium titanate. And
The first internal electrodes 3 or the second internal electrodes 4 are alternately arranged between the stacked layers 2. The first and second internal electrodes 3 and 4 are made of a noble metal material such as Pd or an Ag-Pd alloy or a base metal material such as Ni.
The first internal electrode 3 extends from, for example, one end face of the multilayer body 1, that is, the left end face in the drawing.

The second internal electrode 4 is disposed between a dielectric layer on which the first internal electrode 3 is formed and an adjacent layer. For example, the second internal electrode 4 extends from the other end face of the multilayer body 1, that is, the right end face in the figure. Has been issued.

The base conductor film 5 is provided on both end surfaces of the laminate 1.
The first external electrode 5 and the second external electrode 6 are formed of a, 6a and plating layers 5b, 6b. The first external electrode 5 is connected to one end face of the multilayer body 1, that is, the left end face, in order to connect to the plurality of first internal electrodes 3.
It is formed from the ends of four faces adjacent to the end face.

The second external electrode 6 is connected to the plurality of second internal electrodes 4, and is connected to the other end face of the multilayer body 1, that is, the four end faces adjacent to the end face, centering on the right end face. It is formed from the end.

In the present invention, the thickness of the outermost dielectric layers 2a and 2z among the dielectric layers 2... Constituting the laminate 1 is determined by the radius of curvature r of the ridge portion of the laminate 1. It is determined as appropriate. That is, assuming that the thickness of the outermost dielectric layer 2a (dielectric layer after firing) is the radius of curvature r of the ridge line portion of the laminate 1, the thickness is 1.2 to 3.3 times the radius of curvature r. Have.

The multilayer ceramic capacitor 10 having the above structure
Is prepared as follows.

First, two types of ceramic green sheets made of a dielectric material are prepared. One ceramic green sheet is a green sheet that becomes the outermost dielectric layers 2a and 2z, and another ceramic green sheet is a ceramic green sheet that becomes the dielectric layer 2 sandwiched between the outermost dielectric layers. is there.

In each ceramic green sheet, a plurality of element regions to be a multilayer ceramic capacitor are arranged vertically and horizontally. One element region will be described.

Next, for example, except for the ceramic green sheet to be the outermost dielectric layer 2a, a conductor film to be the first internal electrode 3 or a second internal electrode 4 The conductive film is formed by printing a conductive paste having metal powder. Note that the first internal electrode 3 and the second internal electrode 4 are each rectangular, and their extending directions are different from each other.

Next, green sheets to be the first and second internal electrodes 3 and 4 are laminated according to the lamination order. At this time, on the lowermost surface, a green sheet on which a conductive film serving as the first internal electrode 3 is formed from a green sheet serving as the dielectric layer 2z serving as the outermost layer, and a conductive film serving as the second internal electrode 4 are formed. The green sheets are alternately stacked, and a green sheet serving as the dielectric layer 2a is stacked on the uppermost layer, and the whole is pressed.

Next, the green sheet laminate is cut into a predetermined size in accordance with a predetermined element region to form an unfired chip-like laminate to be a laminate.

Next, the unfired chip-like laminate is fired in a predetermined atmosphere and temperature. As a result, a green sheet serving as the dielectric layer 2 constituting the unfired chip-shaped laminate,
The conductor films serving as the internal electrodes 3 and 4 are subjected to a baking treatment to form an integrally sintered laminate in which the conductor films are firmly adhered to each other.

Thereafter, the fired integral sintered laminate is subjected to barrel polishing. In this barrel polishing, the barrel polishing conditions are set in consideration of the thickness of the dielectric layers 2a and 2z located at the outermost layers of the integrated sintered laminate, and the edge of the integrated sintered laminate is rounded ( (Curved surface) processing. As a result, the ridge portion of the laminate 1 becomes a curved surface and the first internal electrode 3
Then, the second internal electrode 4 is completely exposed from the end face of the multilayer body 1.

In this barrel polishing, the radius of curvature is set at the ridge of the laminate 1 and the outermost dielectric layer 2 of the laminate 1 is formed.
Assuming that the thickness of a (2z) is t, the thickness t = 1.2r ~
3.3r.

Next, the external electrode 5 is formed on the end face of the multilayer body 1 where the first internal electrode 3 is exposed, and the external electrode 6 is formed on the end face where the second internal electrode 4 is exposed. Specifically, the end face portion of the laminate 1 is dipped (dipped) into a conductive paste tank made of Ag or an Ag-Pd alloy, and a conductive paste is applied to the vicinity of the end face of the laminate 1. Then, the applied conductive paste is baked to form underlying conductive films 5a and 6a. Thereafter, on the surfaces of the base conductor films 5a and 6a, a Ni plating layer made of a material that is unlikely to suffer from solder erosion and a plating layer made of a material such as Sn or Sn—Pb alloy (together with the plating layers 5b and 6b) are formed. .

Thus, according to the multilayer ceramic capacitor 10 of the present invention, the predetermined radius of curvature r
Is given. Outermost dielectric layer 2a of laminate 1
The thickness t of (2z) is 1.2 to 3.3 times the radius of curvature r.

Therefore, the distance between the internal electrodes 3 and 4 and the external electrodes 5 and 6 to which the plating solution is applied can be made sufficiently long. Accordingly, it is possible to prevent the plating solution from intruding into the internal electrodes 3 and 4 from the interface between the external electrodes 5 and 6 and the stacked body 1 or directly from the external electrodes 5 and 6.

Further, it is possible to prevent a decrease in the adhesion between the dielectric layers at the ridge portion due to mechanical stress generated during barrel polishing. In addition, the internal electrodes 3 and 4 are not deleted due to variations in barrel polishing, and the equivalent series resistance (ESR) is reduced.
Variations can be eliminated. Further, when the multilayer ceramic capacitor is soldered to a printed wiring board or the like, solder fillets are formed on the external electrodes 5 and 6. However, even if mechanical stress is applied from the outside, the stress does not concentrate on the interface between the internal electrodes 3 and 4 and the dielectric layers 2... Or the dielectric layers 2. Thus, peeling and cracking between layers of the multilayer ceramic capacitor mounted on the like are prevented.

Further, in the outermost dielectric layer 2a (2z), the difference in the heat shrinkage between the outer surface side portion, the inner side internal electrode and the interface portion can be reduced, so that the thermal shock (Δ
T) Cracks are less likely to occur in the test.

[0044]

[Experimental Example] Next, the inventor of the present invention has proposed a model 2012 (length = 2.0
mm, width = 1.25 mm, thickness = 1.25 mm), the radius of curvature of the ridgeline portion of the multilayer body 1 is kept constant, and the thickness of the outermost dielectric layer 2a is 6 mm.
A sample having a thickness of 0 to 300 μm was prepared, and the rate of occurrence of insulation failure (IR failure) of the dielectric layer due to intrusion of the plating solution (IR failure) (p
pm), occurrence of cracks in the laminate due to solder bonding (Δ
T failure) and the number of insulation resistance failure (SP failure) when an alternating voltage of 125 V was applied in 85% humidity.

Specifically, a water-soluble slurry is prepared by dispersing a ceramic powder containing barium titanate as a main component, a sintering aid, pure water and a dispersant for 10 hours using an attorter. 20 wt% of this slurry
% Binder aqueous solution (8 wt% binder solid content)
Is added and agitated to perform a filter pass to obtain a slip.

Using this slip, a ceramic raw sheet having a thickness of several tens of μm is prepared by a normal sheet preparation method, and an internal electrode (palladium paste) having a thickness of 2 to 5 μm is formed on this green sheet by screen printing. It is formed by a conventionally known thin film forming method. 70 to 80 layers of the raw sheet on which the internal electrodes are formed are laminated, thermocompression-bonded and cut to obtain an unfired chip-shaped laminate. Here, several raw sheets on which no internal electrodes are formed are laminated above and below in the laminating direction to form a top margin portion which is the outermost dielectric layer.

Next, the chip-shaped laminate in the unfired state is degreased at 300 ° C. × 2 hr, and then degreased at 1100 to 1400 ° C.
And fired together. Several sheets that do not print any internal electrodes during firing are integrated.

Next, the ridge portion of the sintered laminate is subjected to barrel polishing by barrel polishing so as to have a radius of curvature shown in Table 2. Thereafter, printing and baking of an external electrode (silver paste) was performed on the end face portion of the laminate, and plating was applied by a normal electrolytic plating method.

In the multilayer ceramic capacitor, the rate of occurrence of defects after plating when the thickness t of the outermost dielectric layer 2a (2z) is changed while keeping the capacitance and the thickness of the porcelain constant is maintained. For example, those having an insulation resistance of 10 ⁴ Ω or more are regarded as defective, and the occurrence rate is shown in ppm.

The ΔT failure was defined as failure such as cracking after immersion in a solder bath at 340 ° C. for a predetermined time.

The SP failure is 125 V at 85% humidity.
, And the insulation resistance at that time, whose insulation resistance was deteriorated from the insulation resistance in the initial state, was regarded as defective.

[0052]

[Table 1]

As described above, the outermost dielectric layer 2a (2
By properly adjusting z), the thickness of the outermost dielectric layer can be reduced to 1.2 times or more the radius of curvature, while preventing an increase in the thickness dimension of the chip-shaped laminate 1 and a decrease in reliability. Is 1.25 times or more and 3.3 times or less, preferably 3.times.
By setting it to 25 times or less, it is possible to prevent the occurrence rate of defects due to the infiltration of the plating solution while keeping the initial characteristics such as the capacitance within the standard, and to prevent the thermal shock when soldering on the printed wiring board. Separation of the dielectric layer and the internal electrode can be prevented, and SP failure can be prevented.

For example, as shown in Sample Nos. 1 and 2, when the radius of curvature is less than 1.2 times, insulation resistance failure occurs in 50 or more samples, and ΔT failure and SP failure occur. Would. This is because the thickness t of the outermost dielectric layer is
This is because the thickness becomes relatively thinner than the radius of curvature r, and the distance d ₁ between the internal electrodes 3 and 4 and the external electrodes 5 and 6 at the ridgeline portion of the multilayer body 1 becomes short.

As shown in sample numbers 12 and 13,
If it exceeds 3.3 times the radius of curvature, a ΔT failure occurs. This is because the thickness t of the outermost dielectric layer is relatively thicker than the radius of curvature r, and the thicknesses of the underlying conductor films 5a and 6a at the end surfaces of the multilayer body 1 tend to be smaller. This is due to the fact that the distance d ₂ between the external electrodes 5 and 6 and the internal electrodes 3 and 4 at the end face portion 1 is short.

The present inventor similarly examined the relationship between the thickness of the outermost layer and the radius of curvature r of the laminate for other dimensions of the laminate.

[0057]

[Table 2]

As a result, the dimensions (1005 length, width, and thickness of the laminate were 1.0 mm, 0.5 mm, 0.5 mm,
Type 1608 Length, width, thickness 1.6mm, 0.8m
m, 0.8 mm), the outermost dielectric layer 2a
If the relationship between the thickness t of (2Z) and the radius of curvature r of the ridgeline portion of the laminate 1 is also 1.2 to 3.3 times, no failure occurs at all in the insulation resistance, heat shock, and humidity and pressure resistance test. It was confirmed.

It should be noted that the present invention is not limited to the above embodiment, and various changes and improvements may be made without departing from the scope of the present invention.

[0060]

As described above, according to the present invention, the ridge of the laminate is curved, and the thickness t of the outermost dielectric layer of the laminate is smaller than the radius of curvature r of the ridge. 1.2 ~
3.3 times.

For this reason, the plating solution does not penetrate from the shortest distance between the internal electrode and the external electrode, does not reach the internal electrode, and does not cause any failure even in the insulation resistance, heat shock, and humidity and pressure resistance test. It becomes a multilayer ceramic capacitor.

Further, there is no fear that the interlayer adhesion at the ridgeline portion is reduced due to mechanical stress applied during barrel polishing. In addition, variations in equivalent series resistance (ESR) are eliminated due to variations in barrel polishing.

[Brief description of the drawings]

FIG. 1 is an external perspective view of a multilayer ceramic capacitor according to the present invention.

FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor of the present invention.

FIGS. 3A and 3B are cross-sectional views of a laminate of the present invention, wherein FIG. 3A is a vertical cross-sectional view and FIG.

FIG. 4 is a sectional view of a conventional ceramic capacitor.

FIGS. 5A and 5B are partial cross-sectional views.

[Explanation of symbols]

 10, 50: multilayer ceramic capacitor 1, 51: multilayer body 2, 52: dielectric layer 3, 4, 53, 54: internal electrode 5, 6, 55, 56: external electrode 7, 8, 57, 58 Plating portion r: radius of curvature of ridge line portion of laminated body t: thickness of outermost dielectric layer

Claims (1)

[Claims] 1. A multilayer ceramic capacitor comprising a pair of end portions of a laminated body in which dielectric layers and internal electrodes are alternately laminated, and external electrodes connected to the internal electrodes are formed. The ridge line is curved and
A multilayer ceramic capacitor, wherein the thickness of the outermost dielectric layer of the multilayer body is 1.2 to 3.3 times the radius of curvature of the ridge portion.