JP2000124313A - Semiconductor device, manufacturing method thereof, and liquid crystal device and liquid crystal display device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of forming fine through-holes, realizing miniaturization and high detail of a pixel size, a manufacturing method thereof, and a liquid crystal device and a liquid crystal display device using the same. I do. SOLUTION: An insulating layer is coated on a semiconductor substrate on which a main electrode of a semiconductor element is formed, and a conductive film formed on the insulating layer is connected to the main electrode via a contact hole formed in the insulating layer. A second insulating layer formed on the first insulating layer, the second insulating layer being formed on the first insulating layer and having a region where the contact hole is formed removed. And a third insulating layer made of the same material as the first insulating layer formed in a desired shape using the second insulating layer as an etching stopper layer, and the first insulating layer is formed of the second insulating layer. In the region where the insulating layer is removed, the opening is processed in a self-aligned manner.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a method of manufacturing the same, and a liquid crystal device and a liquid crystal display device using the same, and more particularly, to a lower conductive layer formed on a semiconductor substrate with an insulating layer interposed therebetween. The present invention relates to a semiconductor device having a structure in which a film (main electrode) and an upper conductive film are electrically connected to each other via a contact hole, a manufacturing method thereof, and a liquid crystal device and a liquid crystal display device using the same.

[0002]

2. Description of the Related Art In today's multimedia age,
The importance of devices that communicate with image information
Increasingly. Above all, liquid crystal display devices have attracted public attention because of their thinness and low power consumption.
It has grown into a key industry alongside semiconductors. This liquid crystal display device is currently mainly used for notebook type personal computers having a screen such as a 10-inch size, but in the future, not only personal computers but also workstations and home televisions, It is considered to be used for large screen sizes.

[0003] However, as the size of the screen increases, the manufacturing apparatus increases in size and cost. In addition, in order to drive a large screen, electrically strict characteristics are required. As the size of the screen increases, there is a problem that the manufacturing cost sharply increases in proportion to the second to third powers of the screen size.

Therefore, recently, a projection (projection) system in which a small liquid crystal display panel is prepared and a liquid crystal image displayed by the liquid crystal display panel is optically enlarged and displayed has attracted attention. This is because, as the density and miniaturization of semiconductor devices increase, similar to the scaling law for performance improvement and cost reduction, the size is reduced and the characteristics are improved.
At the same time, cost can be reduced.

In recent years, an active matrix circuit including a peripheral driving circuit has been formed on a semiconductor substrate such as Si.
2. Description of the Related Art A reflection type liquid crystal panel (liquid crystal display device) that uses a pixel electrode for driving liquid crystal as a reflecting mirror for reflecting light for each pixel has attracted attention in terms of low cost and high image quality.

FIGS. 16 to 27 show a manufacturing process of a pixel electrode structure on a semiconductor substrate in a conventional reflection type liquid crystal panel in the order of steps. Here, the same configuration as the configuration of the present invention described below is described using the same reference numeral.

FIG. 16 shows a state where the processing of the drain electrode 11 has been completed on the insulating layer 8 'of the semiconductor substrate. In FIG. 17, PS indicated by reference numeral 18-1
An iO layer is deposited to a thickness of 5000 angstroms by a plasma CVD method, on which an 18-2
The SOG layer, denoted by, is also coated twice, with a thickness of 2200 Å. Here, the reason why SOG18-2 is coated twice is to improve the flatness.

Subsequently, in FIG. 18, SOG18-2
On top, a P-SiO layer as an insulating layer 8 is formed by plasma CVD.
It is deposited to a thickness of 4000 angstroms by the method. Note that the insulating layer 8 may be P-SiN deposited by a plasma CVD method.

In FIG. 19, a Ti layer is deposited as a light-shielding layer 7 to a thickness of 3000 Å by a sputtering method, and a region for forming a through-hole portion serving as a contact hole between the pixel electrode and the drain electrode 11 is removed. And processing into a desired shape. The processing of this Ti layer is performed after patterning with a photoresist.
Cl ₂ / BCl ₃ using a mixed gas system ECR plasma etching apparatus, to implement.

In FIG. 20, an insulating layer 21 serving as a capacitance film is formed.
A P-SiN layer, which is to be
Deposition is performed to a thickness of 0 Å, and subsequently, an insulating layer 9 for separating pixel electrodes is deposited. The insulating layer 9 is made of P-SiO
And formed with a thickness of 14000 angstroms by a plasma CVD method.

Referring to FIG. 21, the insulating layer 9 is processed into a shape for separating the pixel electrode. Processing is performed by using a CF ₄ / Ar mixed gas type parallel plate type plasma etching apparatus after patterning with a photoresist, and using a CF ₄ / Ar
= 60/800 ccm, processing pressure: 1.0 torr, 3
Using a high frequency power supply of 80 kHz, power supply power is 750 W
Use the condition Under the etching conditions, the etching rate of P-SiO, which is the film to be etched, is about 6500 Å / min, while the etching rate of P-SiN of the base is 250,
A selection ratio of about 0 Å / min and about 2.5 is secured, and the P-SiN layer serves as an etching stopper layer.

In the steps shown in FIGS. 22 to 25, a through hole for connecting the drain electrode 11 to the pixel electrode is formed. Also, in FIG.
0 is applied. This photoresist needs to have a sufficient thickness to cover the insulating layer 9 and, at the same time, the resist is simultaneously etched during the etching for forming the through-hole, so that the upper portion of the insulating layer 9 is not exposed. Need to be secured. For this purpose, a thickness of about 2 to 3 μm from the surface of the insulating layer 21 is required.

[0013] In FIG. 23, by exposure and development,
After performing resist patterning, in FIG.
Etching is performed using an F ₄ / CHF ₃ / Ar mixed gas type parallel plate type plasma etching apparatus, and in FIG. 25, the photoresist is removed. Next, in FIG. 26, the pixel electrode film 12 is deposited, and in FIG.
Using the P method, separation between pixel electrodes and surface flattening are performed.

[0014]

In the above prior art, as described above, when forming a through hole,
The resist 500 becomes thick. Therefore, FIG.
24, it is difficult to perform resist patterning of fine holes, and the etching in FIG.
Due to the large aspect ratio, it was difficult to etch fine holes.

[0015] For these reasons, it is difficult to form a fine through-hole, and the size of the through-hole is inevitably increased.
This hindered high definition LCD panels.

The present invention has been made based on the above circumstances, and an object of the present invention is to provide a semiconductor device capable of forming a fine through hole and realizing a reduction in the size and the detail of a pixel, and a method of manufacturing the same. And a liquid crystal device and a liquid crystal display device using the same.

[0017]

According to the present invention, an insulating layer is coated on a semiconductor substrate on which a main electrode of a semiconductor device is formed, and a conductive film formed on the insulating layer is formed on the semiconductor substrate. A semiconductor device in contact with the main electrode via a contact hole formed in the insulating layer,
The insulating layer includes a first insulating layer on the semiconductor substrate;
A second insulating layer formed on the first insulating layer and having a region where the contact hole is formed removed, and a third insulating layer formed in a desired shape using the second insulating layer as an etching stopper layer. And the first insulating layer comprises:
In the region where the second insulating layer is removed, the opening shape is processed in a self-aligned manner.

In this case, the first insulating layer is made of SOG (Sp
It is preferable to have a laminated structure including “in On Glass”.

An insulating layer is formed on a semiconductor substrate on which a main electrode of a semiconductor device is formed, and a contact hole for contacting a conductive film formed on the insulating layer with the main electrode is formed on the insulating layer. In the method of manufacturing a semiconductor device to be formed in the first step, the processing steps include a step of covering and forming a first insulating layer, and a step of forming a second insulating layer on the first insulating layer and forming the contact hole. Removing the second insulating layer in the region, coating the third insulating layer thereon, processing the second insulating layer as an etching stopper layer into a desired shape, and simultaneously removing the second insulating layer Forming the contact hole by processing the first insulating layer in a self-aligned manner with the opening shape in the formed region, and thereafter, covering the conductive film to form the desired shape. Characterized in that it includes a step of processing.

The above-described semiconductor device has a plurality of pixel electrodes in which switching elements are arranged for each pixel in an active matrix form, and is provided between a common electrode arranged opposite to the semiconductor device. Is adopted as a liquid crystal device sandwiching liquid crystal, and furthermore, this liquid crystal device constitutes a projection type liquid crystal display device, has at least three liquid crystal panels for three colors, and has a high reflection mirror. And a blue reflective dichroic mirror to separate blue light, and further separate red and green by a red reflective dichroic mirror and a green / blue reflective dichroic mirror and project each liquid crystal panel. It is good that it is composition.

Therefore, according to the present invention, fine through holes can be formed, the pixel size can be reduced, and a high-definition liquid crystal panel can be manufactured.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below.
A liquid crystal panel including a display area and a peripheral area will be described as an example. Note that the present invention is not limited to application to a liquid crystal panel, but is also used as a wiring forming step of a general semiconductor device. Further, the production method of the present invention
It is also effective for forming a contact hole including a fine through hole (via hole) at the time of performing the dual damascene method using the MP method.

(First Embodiment) FIG. 1 shows a cross section of a liquid crystal panel portion using a semiconductor device of the present invention, wherein reference numeral 1 denotes a semiconductor substrate, and 2 and 2 'denote, respectively. The p-type and n-type wells, 3 and 3 'are source regions of the transistor, 4 is a gate region, and 5 and 5' are drain regions.

As shown in FIG. 1, since a high voltage of 20 to 35 V is applied to the transistor in the display region, the source and drain layers are not formed in a self-aligned manner with respect to the gate 4 and an offset is provided. , during which the source region 3 ', the drain region 5' as shown in a low concentration in the p-well n ^- layer of low concentration in the n-well p ^- layer is provided. Incidentally, the offset amount is preferably 0.5 to 2.0 μm.

On the other hand, a part of the peripheral region of the peripheral circuit is shown in FIG.
As shown in the left side of the figure, in some circuits in the peripheral region, source and drain regions are formed in a self-aligned manner with respect to the gate electrode. The reason why a part of the peripheral circuit has a self-aligned structure is that a part of the peripheral circuit is a logic circuit, which can be driven by a 1.5 to 5 V system. This is because a self-aligned structure is desirable in order to improve the driving force.

Although the offset of the source and the drain has been described here, it is effective to change not only the presence / absence of the offset but also the offset amount in accordance with the withstand voltage and to optimize the gate length. .

The above-mentioned semiconductor substrate 1 is made of a p-type semiconductor, and the potential of the substrate is the lowest potential (usually a ground potential).
In the display region, a voltage applied to the pixel, that is, 20 to 35 V, is applied to the n-type well. On the other hand, a part of the peripheral circuit generally has a logic drive voltage of 1. 5-5V is applied. With the above structure,
In each case, an optimum device can be configured according to the voltage, and not only a reduction in chip size but also a high pixel display can be realized by improving a driving speed.

In FIG. 1, 6 is a field oxide film, 8 'is an insulating layer of PSG (phosphor glass), NSG (non-doped glass), BPSG, etc., 10 is a source electrode connected to data wiring, and 11 is a pixel electrode. The connected drain electrode 12 is a pixel electrode also serving as a reflecting mirror. Also,
Reference numeral 7 denotes a light-shielding layer that covers the display area and the peripheral area.
N, W, Mo, and a laminated film combining them are suitable, and are formed not only in the display region but also in the peripheral circuit region by the same process using a vacuum deposition method or a sputtering method. Is formed by patterning. Since the light-shielding layer 7 covers almost the entire surface of the chip, the light-shielding property of the irradiation light is improved, and the transistor has an effect of preventing malfunction of the transistor due to leaked light.

As shown in FIG. 1, the light-shielding layer 7 covers a transistor and the like in the display region except for a connection portion between the pixel electrode 12 (conductive film) and the drain electrode 11 (main electrode). Video lines of the light shielding layer 7 in the peripheral circuit area,
The light-shielding layer 7 itself is removed in a region such as a clock line where it is inconvenient to increase the wiring capacitance. Since the illumination light may be mixed in the portion where the light-shielding layer 7 is removed and a malfunction of the circuit may occur, the layer of the pixel electrode 12 is devised so as to cover the region other than the light-shielding layer 7. ing.

Reference numeral 8 denotes an insulating layer below the light shielding layer 7 (first insulating layer).
SOG (Spi) made of SiO on a P-SiO (SiO formed by plasma CVD method) layer
The P-SiO layer 18 is further covered with a P-SiO layer to ensure the flatness of the insulating layer 8. In addition to the planarization by SOG, P-TEOS (Plasma-Te
(Traoxy-Silane) film is formed, and the P-SiO layer is covered.
A method of performing planarization by processing with the P method may be used.

Reference numeral 9 denotes an insulating layer (third insulating layer) provided between the pixel electrodes. The insulating layer 9 separates the pixel electrodes. P-SiO or the like is suitable for the insulating layer 9. Reference numeral 21 denotes an insulating layer (second insulating layer) provided between the reflective electrode 12 and the light shielding layer 7 for each pixel, and the pixel electrode 12 and the light shielding layer 7 are held through the insulating layer 21. Capacity. The insulating layer 21 has P-Si
A high dielectric constant material such as N is effective.

As for the light-shielding layer 7, the insulating layer 9, the insulating layer 21, and the reflective electrode 12, the peripheral region and the display region 19 are formed simultaneously in the same step. Further, 14 is a liquid crystal material such as PNLC or PDLC which is a polymer network liquid crystal,
Reference numeral 15 denotes a common transparent electrode facing the reflection electrode (pixel electrode) 12, 16 denotes a transparent counter substrate, 19 denotes a display area, and 20 denotes an antireflection film. Reference numeral 22 denotes a sealing material for holding the semiconductor substrate and the opposing substrate, and the gap between the substrates is controlled by this. Further, 17 and 17 'are high concentration impurity regions.

Reference numeral 13 denotes the common transparent electrode 15 and the opposing substrate 1.
And an anti-reflection film provided between the first and second films 6 and 6 so as to reduce the interface reflectance in consideration of the refractive index of the liquid crystal at the interface. In this case, an insulating layer having a smaller refractive index than the counter substrate 16 and the transparent electrode 15 is preferable.

As shown in FIG. 1, a high-concentration impurity layer 1 having the same polarity as wells 2 and 2 'formed under the transistor.
7, 17 'are formed around and inside the wells 2, 2', and even if a high-amplitude signal is applied to the source,
Since the well potential is fixed at a desired potential by the low resistance layer, stable and high-quality image display can be realized. Further, the high-concentration impurity layers 17 and 17 'are provided between the n-type well 2' and the p-type well 2 with the field oxide film 6 interposed therebetween, and are usually used for MOS transistors. The channel stop layer immediately below the field oxide film 6 is not required. Since these high-concentration impurity layers 17 and 17 'can be formed simultaneously in the source and drain layer forming process, the number of masks and man-hours in the forming process are reduced, and the cost can be reduced.

As shown in FIG. 1, the well region 2 'has the opposite conductivity type to the semiconductor substrate 1. Therefore, here, the well region 2 is p-type. It is desirable that the p-type well region 2 and the n-type well region 2 'have an impurity implanted at a higher concentration than the semiconductor substrate 1, and the impurity concentration of the semiconductor substrate 1 is 10 ¹⁴ to 10 ¹⁵ (cm ^−3). ), The well region 2 has an impurity concentration of 10 ¹⁵ to 10 ¹⁷ (cm).
^-3 ) is desirable.

The source electrode 10 is connected to a data line through which a display signal is sent, and the drain electrode 11 is connected to the pixel electrode 1.
2 respectively. These electrodes 10 and 11 have
Usually Al, AlSi, AlSiCu, AlGeCu, A
Wiring of a material such as lCu is used. If a barrier metal layer made of Ti and TiN is used on the contact surface between the lower part of these electrodes 10 and 11 and the semiconductor, the contact can be stably realized. Also, the contact resistance can be reduced.

The pixel electrode 12 has a flat surface and is desirably a high-reflection material.
In addition to materials such as i, AlSiCu, AlGeCu, and AlCu, it is also possible to use materials such as Cr, Au, and Ag. Further, by forming a film with high-temperature Al having reflow properties, The pixel electrode 12 can be created.

In the final step of manufacturing the semiconductor device, the surface of the pixel electrode 12 is treated by the CMP method, thereby simultaneously improving the flatness and separating the pixel electrodes 12 from each other.

Next, a method of forming a pixel electrode structure including the formation of a through-hole (generally referred to as a via hole) 23, which is a point of the present invention, will be specifically described. FIG. 2 shows that the drain electrode 11 is formed on the insulating layer 8 '.
(Main electrode) has been processed. In FIG. 3, a P-SiO layer indicated by reference numeral 18-1 is deposited to a thickness of 5000 angstroms by a plasma CVD method, and an SOG layer indicated by reference numeral 18-2 is deposited thereon by a plasma CVD method. Coated twice in thickness. Here, the SOG layer is coated twice for the purpose of improving flatness.

In this embodiment, the SOG (Spi) of 18-2 is used.
n On Glass) layer is called inorganic SOG,
Silanol (Si (OH) containing no P (phosphorus)
4) A material is used (P-containing SOG is generally called organic SOG).

Since this inorganic SOG does not contain P, it can prevent corrosion of metal wiring and cracks due to SOG film stress, and can form a thick SOG film without using complicated steps such as SOG etch back. , A material that facilitates planarization.

Specifically, the SOG of 18-2 (Spin
The formation of the (On Glass) layer is performed as follows.

By the spin coating method, the first SOG film is
00A is applied. The rotation speed at that time is 2800 (rpm)
m). After that, if the second layer of SOG is continuously applied, the first layer of SOG has poor wettability, repels the second layer of SOG, and causes a loss or the like, so that coating cannot be performed. Therefore, the first layer of SOG is irradiated with 172 nm UV light for the purpose of improving wettability by surface modification. UV light has a wavelength of 185 nm and 254 nm,
The effect of surface modification is seen. Subsequent to the irradiation of the UV light, the second layer of the SOG film was formed by the spin coating method again for 2200 hours.
A is applied. Finally, heat treatment is performed at 400 ° C. for 30 minutes to obtain 18-2.

The reason why the application is performed twice is that if the application of 4400 A is performed at a time, problems such as cracks are generated by the heat treatment.

Subsequently, in FIG. 4, the SOG layer 18-2
A plasma CV is formed thereon as an insulating layer 8 (first insulating layer).
A P-SiO layer is deposited to a thickness of 4000 angstroms by the D method. In FIG. 5, a Ti layer is deposited as a light shielding layer 7 to a thickness of 3000 angstroms by a sputtering method, and processed into a desired shape by removing a region where a portion of the through hole 23 is formed. Machining of Ti, after patterning by a photoresist, carried by Cl ₂ / BCl ₃ gas mixture based ECR plasma etching apparatus.

In FIG. 6, the pixel electrode 12 (conductive film) and the light shielding layer 7 are composed of an insulating layer 21 for forming a capacitor.
(Second insulating layer). Reference numeral 21 denotes P-Si
The N layer is deposited to a thickness of 4000 angstroms by the plasma CVD method, and a suitable thickness can be selected in consideration of the switching characteristics of the device and the withstand voltage of the film. However, the present invention is not limited to this.

7 to 10, the insulating layer 21 in the portion of the through hole 23 is removed. Specifically, in FIG. 7, a photoresist is applied for resist patterning. In this step, it is not necessary to apply a very thick resist as in the conventional example in order to cover the step, and the P-SiN layer, which is the insulating layer 21, is replaced by 4000.
A required thickness is sufficient as a mask (etching stopper) when processing with a thickness of Å.

In the present invention, an i-line resist is used as the resist, and its thickness is set to about 1 μm. However, a so-called BARC (B
OTTO Anti Reflective Coa
Assuming that t) is employed or that an excimer stepper is used, fine and high-precision resist patterning is possible by using an excimer resist and exposing with an excimer stepper.

In FIG. 8, exposure is performed and developed by an i-line stepper. In this step, as described above, the resist thickness can be made much thinner than in the past, and therefore, fine resist patterning can be formed.
In FIG. 9, the insulating layer 21 is processed by etching. This processing is performed by a parallel plate type plasma etching apparatus using a CF ₄ / Ar mixed gas and a high frequency power supply of 380 KHz. . In addition, PS
For processing the iN layer, it is also possible to use an ECR plasma etching apparatus using SF ₆ as an etching gas. In this case, a high selectivity with the underlying P-SiO layer can be ensured. Control becomes simple.

In FIG. 10, after ashing with oxygen plasma, the resist and the polymer generated during the etching are removed by performing a treatment with an organic alkali solution to completely remove the resist and the polymer.
Further, in FIG. 11, an insulating layer 9 (third insulating layer) for separating pixel electrodes is deposited. P-SiO as the insulating layer 9
The layer is deposited to a thickness of 14000 Å by plasma CVD.

In FIG. 12, the insulating layer 9 is processed into a shape for separating the pixel electrode. At this time, the insulating layer 21
Acts as an etching stopper layer. After the processing of the insulating layer 9, the etching is continuously performed to obtain FIG.
Through holes are formed in a self-aligned manner in the openings of the insulating layer 21 processed in the steps of FIGS. The planar shape of the through hole is circular, and the through hole diameter is 1.0μ.
m. In this processing, after patterning with a photoresist, an ECR plasma etching apparatus (C ₄ F ₈
(Using a mixed gas of / O ₂ or a mixed gas of C ₄ F ₈ / O ₂ / CO), the etching is sufficient for the through hole to reach the drain electrode 11. According to this etching, the P-SiO / P-SiN selectivity is 10 to 20.
Depending on the degree and conditions, infinity can be secured, and through holes can be formed using the insulating layer 21 as a mask.

The detailed etching conditions are described below.

C4F8 / O2 / Ar = 30/9/200
(Sccm), processing pressure = 4 (mTorr), microwave power = 1500 (W), RF power = 500
(W) ECR plasma etching.

In addition, the following etching conditions may be used.

In a CF4 / CHF3 gas parallel plate type plasma etching apparatus, CF4 / CHF3 / Ar =
35/15/400 (sccm), processing pressure = 300
(MTorr), power (300 kHz power supply) = 900
Use of condition (W) is also possible.

The process flow from the state shown in FIG. 11 to the state shown in FIG. 12 is as follows. To process the insulating layer 9 into a shape for separating pixel electrodes,
Resist patterning is performed using a novolak-based resist for i-line exposure. The insulating layer 9 is processed under the above-described etching conditions. Processing of the insulating layer 9 stops at the insulating layer 21 serving as an etching stopper layer. By continuously performing the etching, the P-SiN removal region formed in the steps of FIGS. Etching is performed until the number reaches 11, and a through hole is formed.

In FIG. 13, a pixel electrode film 12 is deposited. The pixel electrode film 12 uses high-temperature Al having reflow properties. The configuration of the pixel electrode film 12 will be described in detail.
First, in order to prevent the reaction between the insulating layer 21 and Al and improve the reflow property of the high-temperature Al deposited thereon, the TiN layer is formed to a thickness of 2000 Å by sputtering, The layer is deposited to a thickness of 300 Å. Subsequently, when high-temperature Al is deposited directly on the above-mentioned film, the Al is deposited in an island shape.
1 is deposited at a thickness of 7000 Å. Finally, the wafer is heated to 425 ° C., and high-temperature Al is deposited at 17000 Å by a sputtering method. After the deposition, the temperature is maintained at 425 ° C. for several minutes, so-called Al reflow is performed.

In this embodiment, the pixel electrode film 12 deposited by the above-described method is used. However, the film configuration of the pixel electrode film 12, each film thickness, the high Al wafer temperature, and the holding time after the deposition are used. Is an important factor that determines the reflow property, and the filling property of the through hole due to the reflow depends on the shape of the through hole and the diameter of the through hole. Since suitable conditions can be selected according to the diameter, the present invention is not limited to the pixel electrode film 12 in the present embodiment. As a material of the pixel electrode 12, as described above, A is used by a normal sputtering method or a vacuum evaporation method.
1, AlSi, AlSiCu, AlGeCu, AlC
u, Cr, Au, Ag, etc. can also be selected.

In FIG. 14, the pixel electrode film is polished by the CMP method until the pixel electrode film reaches the insulating layer 9 for separating the pixel electrode.
The surface is flattened.

The conditions for the CMP were as follows: an EPO-114 CMP apparatus manufactured by Ebara Co., Ltd.
PREME RN-H (D51), using Fujimi PLANERLITE 5102 as slurry, slurry flow rate 200 ml / min, PLATEN SPEED /
Polishing was performed under conditions of CARRIER SPEED = 50/49 rpm and a wafer pressing pressure of 200 g / cm 2.

As described above, according to the present invention, fine through-holes can be formed, and therefore the pixel size can be reduced, so that the definition of the liquid crystal panel can be increased.

FIG. 15 shows an optical system in which a reflection type liquid crystal panel (liquid crystal display device) using a semiconductor device having a characteristic configuration of the present invention is applied to a project type display device. Here, at least three for three colors
Having a liquid crystal panel, separating blue light with a high reflection mirror and a blue reflection dichroic mirror, further separating red and green with a red reflection dichroic mirror and a green / blue reflection dichroic mirror, Each liquid crystal panel is projected.

That is, reference numeral 71 denotes a light source such as a halogen lamp, 72 denotes a condenser lens for narrowing down the light source image, and 73 and 75.
Is a flat convex Fresnel lens, and 74 is a color separation optical element for separating into R, G, and B, and a dichroic mirror, a diffraction grating or the like is effective.

Reference numeral 76 designates R, G, and B separated lights as R, G, and B.
Each of the mirrors, which leads to the three panels G and B, 77 is a field lens for illuminating the condensed beam on the reflective liquid crystal panel with parallel light, and 78 is a reflective liquid crystal element. is there. Reference numeral 80 denotes a projection lens, 8
Reference numeral 1 denotes a screen, which usually comprises a Fresnel lens that converts projection light into parallel light and a lenticular lens that displays a wide viewing angle vertically and horizontally to obtain a clear, high-contrast, bright image. Can be. Although only one color panel is displayed in the configuration of FIG. 15, the space between the color separation optical element 74 and the squeezing section 79 is
Three panels are arranged for each of the three colors.

As a result, a voltage is applied to the liquid crystal layer of the liquid crystal element, and the light that has been specularly reflected at each pixel is transmitted through the squeezed portion 79 and projected on the screen. On the other hand, when no voltage is applied and the liquid crystal layer is a scatterer, the light incident on the reflective liquid crystal element is scattered isotropically, and the scattered light within the angle of view of the aperture of the aperture portion. Other than that, you do not need a projection lens. Thereby, black is displayed.

As understood from the above optical system, no polarizing plate is required, and the signal light enters the projection lens with high reflectivity from the entire surface of the pixel electrode. realizable. Moreover, anti-reflection measures are taken on the surface and interface of the counter substrate, the noise light component is extremely small, and high contrast display can be realized. Further, since the panel size can be reduced, all the optical elements (lenses, mirrors, etc.) have been reduced in size, and low cost and light weight have been achieved. Also, the color unevenness, luminance unevenness, and fluctuation of the light source are as follows.
By inserting an integrator (fly-eye lens type rod type) between the light source and the optical system, on the screen,
I was able to solve it.

[0067]

As described in detail above, according to the present invention,
Since fine through holes can be formed, the pixel electrode size can be reduced, and a high-definition liquid crystal panel can be realized.
Further, by incorporating this liquid crystal panel into a system of a liquid crystal display device such as a projection type liquid crystal display device having a peripheral circuit, an optical system, etc., a high-definition display becomes possible.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view illustrating an embodiment of a reflective liquid crystal display device in a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a first diagram illustrating a manufacturing process of the semiconductor device of the present invention.
It is a typical sectional view of a stage.

FIG. 3 is a schematic sectional view showing a second stage.

FIG. 4 is a schematic sectional view showing a third stage.

FIG. 5 is a schematic sectional view showing a fourth stage.

FIG. 6 is a schematic sectional view showing a fifth stage.

FIG. 7 is a schematic sectional view showing a sixth step.

FIG. 8 is a schematic sectional view showing a seventh stage.

FIG. 9 is a schematic sectional view showing an eighth stage.

FIG. 10 is a schematic sectional view showing a ninth stage.

FIG. 11 is a schematic sectional view showing a tenth stage.

FIG. 12 is a schematic sectional view showing an eleventh stage.

FIG. 13 is a schematic sectional view showing a twelfth stage.

FIG. 14 is a schematic sectional view showing a thirteenth stage.

FIG. 15 is a schematic configuration diagram of an optical system in which the liquid crystal display device of the present invention is applied to a liquid crystal projector.

FIG. 16 is a schematic cross-sectional view showing a first stage of a manufacturing process of a semiconductor device according to a conventional technique.

FIG. 17 is also a schematic sectional view showing a second stage.

FIG. 18 is a schematic sectional view showing a third stage.

FIG. 19 is a schematic sectional view showing a fourth stage.

FIG. 20 is a schematic sectional view showing a fifth step.

FIG. 21 is a schematic sectional view showing a sixth step.

FIG. 22 is a schematic sectional view showing a seventh step.

FIG. 23 is also a schematic sectional view showing an eighth stage.

FIG. 24 is a schematic sectional view showing a ninth stage.

FIG. 25 is a schematic sectional view showing a tenth stage.

FIG. 26 is a schematic sectional view showing an eleventh stage.

FIG. 27 is a schematic sectional view showing a twelfth stage.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 p-type well 2 'n-type well 3, 3' transistor source region 4 gate region 5, 5 'transistor drain region 6 field oxide film 7 light-shielding layer 8, 8' insulating layer 9 insulating layer 10 source electrode Reference Signs List 11 drain electrode 12 pixel electrode 13 antireflection film 14 liquid crystal material 15 common transparent electrode 16 counter substrate 17, 17 ′ high concentration impurity layer 18 P-SiO layer 19 display area 20 antireflection film 21 insulating layer 22 sealing material 23 through hole 24 Semiconductor device part 18-1 P-SiO layer 18-2 SOG layer 500 Photoresist 71 Light source 72 Condensing lens 73, 75 Convex Fresnel lens 74 Color separation optical element 76 Mirror 77 Field lens 78 Reflective liquid crystal element 79 Position 80 Projection lens 81 Screen

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Claims (5)

[Claims] An insulating layer is coated on a semiconductor substrate on which a main electrode of a semiconductor element is formed, and a conductive film formed on the insulating layer is formed on the semiconductor substrate via a contact hole formed in the insulating layer. In a semiconductor device in contact with an electrode, the insulating layer is a first insulating layer on the semiconductor substrate and a second insulating layer formed on the first insulating layer and having a region where the contact hole is formed removed. And a third insulating layer formed in a desired shape using the second insulating layer as an etching stopper layer. The first insulating layer has an opening in a region where the second insulating layer is removed. A semiconductor device characterized by being processed into a shape in a self-aligned manner. 2. The method according to claim 1, wherein the first insulating layer is formed of SO.
A semiconductor device having a stacked structure including G (Spin On Glass). 3. An insulating layer is formed on a semiconductor substrate on which a main electrode of a semiconductor element is formed, and a contact hole for contacting a conductive film formed on the insulating layer with the main electrode is formed in the insulating layer. In the method of manufacturing a semiconductor device to be formed in the first step, the processing steps include a step of covering and forming a first insulating layer, and a step of forming a second insulating layer on the first insulating layer and forming the contact hole. Removing the second insulating layer in the region, coating the third insulating layer thereon, processing the second insulating layer as an etching stopper layer into a desired shape, and simultaneously removing the second insulating layer Forming the contact hole by processing the first insulating layer in a self-aligned manner with the opening shape in the formed region, and then forming and coating the conductive film to a desired shape. A method of manufacturing a semiconductor device. 4. The semiconductor device according to claim 1, further comprising a plurality of pixel electrodes in which a switching element is arranged for each pixel in an active matrix, and is arranged to face the semiconductor device. A liquid crystal device having a liquid crystal sandwiched between the common electrode and the common electrode. 5. The liquid crystal device according to claim 4, which constitutes a projection type liquid crystal display device, wherein at least three liquid crystal devices for three colors are used.
Having a liquid crystal panel, separating blue light with a high reflection mirror and a blue reflection dichroic mirror, further separating red and green with a red reflection dichroic mirror and a green / blue reflection dichroic mirror, A liquid crystal display device characterized by projecting each liquid crystal panel.