JP2000132914A - Data processor and data recorder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable determining of the frequency of an operation clock of a main processing section independent of the operation clock of an input processing section. SOLUTION: In this data processor, a video input processing section operates by a clock ckv synchronous with an input video data and an audio input processing section operates by a clock cka synchronous with an input audio data. A main processing section performs a coding processing and a shuffling processing of an external code with external code encoders 109 and 116 and shuffling parts 110 and 117. An output processing section operates by an operation clock ckrf to form a synchblock with an ID adding part 118 and a synchronous addition part 120. The frequency of an operation clock ckm is set to adapt to a format of a recording video data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus and a data recording apparatus which are used for, for example, recording compressed image data on a recording medium and reproducing the image data from the recording medium.

[0002]

2. Description of the Related Art Digital VCR (VIdeo Cassette Reco)
A data recording / reproducing apparatus which records a digital image signal on a recording medium and reproduces the digital image signal from the recording medium, as typified by rder), is known. A recording processing unit in a digital image recording device can be roughly divided into an input processing unit, a main processing unit, and an output processing unit. The input processing unit stores video and audio digital data in packets of a predetermined length. The main processing unit encodes information indicating data contents and an error correction code in packet units. The main processing unit involves an operation of accessing a relatively large-capacity memory. The output processing unit configures a sync block by adding a synchronization pattern and an ID to the packetized data, the parity of the error correction code, and the like, groups the sync blocks according to the type of data, and Convert to serial data. A rotary head for recording on a tape as a recording medium is connected to the output processing unit.

FIG. 14 shows an example of the configuration on the recording side of a digital VCR. The video input processing unit includes a packing and shuffling unit 107. The input video data is, for example, MPEG2 (Moving Picture Experts Group
p This is an elementary stream generated in the encoding of Phase 2). Therefore, although the wording of the video data is used, the video data is not a baseband signal, but means coded video data, more specifically, variable-length coded DCT coefficient data. The elementary stream is composed of an I (Intra-coded picture) picture generated by encoding one GOP (Group Of Picture) in one frame. An I picture uses information that is closed only in one image when it is encoded. Therefore, at the time of decoding, decoding can be performed using only the information of the I picture itself. The elementary stream is variable-length data in which the amount of generated data differs for each macroblock. The packing and shuffling unit 107 performs a packing process for dividing variable-length input data into a predetermined length and a shuffling process. The shuffling process disperses the recording positions of the macroblocks in one frame on a tape.

[0004] In addition to the shuffling process, shuffling of video data includes a plurality of ECCs (Error Correction).
ig Code) blocks are shuffled to change the order in sync block units. The latter shuffling is intended to substantially improve the error correction capability by preventing errors from concentrating in one ECC block, and is sometimes referred to as interleaving.

[0005] Input audio data is supplied to a delay section 113 of an audio input processing section, and an output of the delay section 113 is supplied to an AUX adding section 114. The delay unit 113 is provided for time alignment with video data. A
UX is auxiliary data and is data having information related to audio data such as the sampling frequency of audio data. Audio AUX is treated the same as audio data.

[0006] Input video data and audio data have transfer rates required for transmission due to their properties. For example, when transmitting video data encoded by MPEG in real time, a clock frequency of 27 MHz is the transfer rate. The above-described input processing unit operates at the same operation clock as the transfer rate. That is, the video input processing unit operates with the clock ckv synchronized with the input video data, and the audio input processing unit operates with the clock cka synchronized with the input audio data.

The main processing unit includes an outer code encoder 109 for encoding an outer code for video data, and a shuffling unit 1 to which an output of the outer code encoder 109 is supplied.
10, an outer code encoder 116 for encoding an outer code for audio data, and an outer code encoder 116
And a main memory (SDRAM (Synchronous Dynamic Random Access).
Memory)) 160. The main processing unit involves an access operation to the main memory 160.
The main processing unit operates the clock ck of the video input processing unit.
v or a clock related thereto (for example, a clock having a double frequency).

A product code is used as an error correction code for video data and audio data. The product code encodes an outer code in a vertical direction of a two-dimensional array of video data or audio data, encodes an inner code in a horizontal direction thereof, and encodes data symbols doubly. The video data is stored in the shuffling unit 110
Accordingly, the rearrangement processing is performed in units of sync blocks, and errors are prevented from being concentrated on a specific ECC block. The audio data undergoes shuffling processing in shuffling 117. As audio shuffling, shuffling in sync block units and shuffling in channel units are performed. SDRAM 160
To the output processing unit, the video data and the audio data subjected to the outer coding and shuffled are output.

The output processing unit includes a FIFO (First-In) as a buffer in a portion for receiving output data of the main processing unit.
First-Out) 161. I to FIFO 161
The D adding unit 118 is connected, and the ID adding unit 118 adds an ID having information indicating a sync block number or the like. The output of the ID addition unit 118 is the inner code encoder 119
, And the inner code is encoded. Further, the output of the inner code encoder 119 is supplied to the synchronization adding section 120, and a synchronization signal for each sync block is added.

The output data from the output processing section is supplied to a recording rotary head via a recording amplifier 121 and is recorded on a magnetic tape. The output processing unit is a data rate (RF head rate) in a recording circuit such as a rotary head.
It operates with the clock ckrf synchronized with the clock.

[0011]

As described above, in the conventional digital VCR, the main processing unit operates at the same clock as the operation clock of the input processing unit or a clock related thereto. As a result, the processing time of the main signal processing unit is restricted by the transfer rate of the input data. When the data rates of the input video and audio data change, it becomes necessary to design the IC of the main processing unit again. In particular, in an environment including the development of digital broadcasting, there are many types of video and audio formats (field frequency, number of lines, interlace / progressive, screen size, aspect ratio, etc.). Therefore, it is desirable that the main processing unit supports a plurality of formats of video and audio, and the fact that the operating clock of the main processing unit depends on the rates of the input video and audio data as in the related art is difficult for a plurality of formats. There is a problem that impairs the corresponding flexibility.

Accordingly, an object of the present invention is to provide a data processing device and a data recording device in which a main processing unit can operate with a clock independent of the rate of input data.

[0013]

According to a first aspect of the present invention, there is provided a data processing apparatus for converting video data into a signal form for transmitting video data, an input processing unit for packing video data into a data area of a predetermined length, and an input processing unit. A main processing unit for encoding an error correction code with respect to data from the input unit; and an output processing unit for forming a sync block by adding a synchronization pattern and an ID to the data from the main processing unit. Is synchronized with video data
And a main processing unit that operates with a second clock having a frequency independent of the first clock.

According to a second aspect of the present invention, there is provided a data recording apparatus for recording video data on a recording medium, an input processing unit for packing the video data into a data area of a predetermined length, and an error correction for the data from the input processing unit. A main processing unit that encodes a code, an output processing unit that forms a sync block by adding a synchronization pattern and an ID to data from the main processing unit, and a recording unit that records an output of the output processing unit on a recording medium Wherein the input processing unit is operated by a first clock synchronized with the video data, and the main processing unit is operated by a second clock having a frequency independent of the first clock. is there.

[0015] Preferably, the video data is data that has been subjected to DCT and variable-length coding, such as MPEG. Also, audio data is processed together with video data. While the input processing unit operates with an operation clock synchronized with the video data, the main processing unit can operate with an operation clock independent of the operation clock of the input processing unit. Therefore, it is not necessary to separately design a main processing unit for a plurality of video data having different frame frequencies, and it is also possible to adjust a delay time caused by the processing of the main processing unit, and further to process the main processing unit. Concentration can prevent the load on the power supply from becoming momentarily heavy.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described with reference to digital VC.
An embodiment applied to R will be described. This embodiment is suitable for use in a broadcast station environment,
Recording and recording of video signals of multiple different formats
It enables playback. For example, a signal (480i signal) having 480 effective lines in the interlaced scanning based on the NTSC system and a signal (576 signals) having 576 effective lines in the interlaced scanning based on the PAL system.
i) are recorded with almost no hardware changes.
It is possible to reproduce. Furthermore, a signal having 1080 lines (1080i signal) in interlaced scanning,
In progressive scanning (non-interlace), the number of lines is 480, 720, and 1080, respectively.
Recording / reproduction such as 0p signal, 720p signal, and 1080p signal) can also be performed.

In this embodiment, the video signal and the audio signal are compression-coded based on the MPEG2 system. As is well known, MPEG2 is a combination of motion compensated prediction coding and compression coding by DCT. The data structure of MPEG2 has a hierarchical structure, and includes a block layer, a macroblock layer,
A slice layer, a picture layer, a GOP layer, and a sequence layer are provided.

The block layer is a unit for performing DCT, D
It consists of a CT block. The macroblock layer includes a plurality of D
It is composed of CT blocks. The slice layer is composed of a header section and any number of macroblocks that do not extend between rows. The picture layer includes a header section and a plurality of slices. A picture corresponds to one screen. G
The OP (Group Of Picture) layer includes a header portion, an I picture that is a picture based on intra-frame coding, and P and B pictures that are pictures based on predictive coding.

An I-picture (Intra-coded picture) uses information that is closed only in one picture when it is coded. Therefore, at the time of decoding, decoding can be performed using only the information of the I picture itself. A P-picture (Predictive-coded picture: a forward predictive coded picture) uses a previously decoded I-picture or P-picture which is temporally previous as a predicted picture (a reference picture for taking a difference). . Whether to encode the difference from the motion-compensated predicted image, to encode without taking the difference,
The more efficient one is selected for each macroblock. A B picture (Bidirectionally predictive-coded picture) is a temporally previous I-picture or P-picture which is temporally preceding, and a temporally backward I-picture, We use three types of I-pictures or P-pictures already decoded, as well as interpolated pictures made from both. Among the three types of difference coding after motion compensation and intra coding, the most efficient one is selected for each macroblock.

Therefore, as the macroblock type,
Intra-frame coding (Intra) macroblock, forward (Fward) inter-frame prediction macroblock that predicts the future from the past, and backward (Backward) interframe prediction macroblock that predicts the past from the future, There is a bidirectional macroblock to be predicted. All macroblocks in an I picture are intra-coded macroblocks. The P picture includes an intra-frame coded macro block and a forward inter-frame predicted macro block. The B picture includes all four types of macroblocks described above.

A GOP contains at least one I picture, and P and B pictures are allowed even if they do not exist. The top sequence layer is composed of a header section and multiple GOPs.
It is composed of

In the MPEG format, a slice is one variable-length code sequence. A variable-length code sequence is a sequence in which a data boundary cannot be detected unless a variable-length code is decoded.

At the head of each of the sequence layer, GOP layer, picture layer, slice layer and macroblock layer, an identification code (referred to as a start code) having a predetermined bit pattern arranged in byte units is provided. Be placed. Note that the header section of each layer described above collectively describes a header, extension data, or user data. In the header of the sequence layer, the size of the image (picture) (the number of vertical and horizontal pixels) and the like are described. The time code, the number of pictures constituting the GOP, and the like are described in the header of the GOP layer.

The macro blocks included in the slice layer are:
It is a set of a plurality of DCT blocks, and the encoded sequence of the DCT block is a variable of a sequence of quantized DCT coefficients, with the number of consecutive 0 coefficients (run) and a non-zero sequence (level) immediately after it as one unit. It is a long code. The macroblock and the DCT block in the macroblock are not added with the identification codes arranged in byte units.
That is, they are not one variable-length code sequence.

A macroblock is a screen (picture) of 1
It is divided into a grid of 6 pixels × 16 lines. A slice is formed by connecting these macroblocks in the horizontal direction, for example. The last macroblock of the previous slice of a continuous slice and the first macroblock of the next slice are continuous, and it is not allowed to form a macroblock overlap between slices. When the size of the screen is determined, the number of macroblocks per screen is uniquely determined.

On the other hand, in order to avoid signal degradation due to decoding and encoding, it is desirable to edit the encoded data. At this time, the P picture and the B picture require a temporally preceding picture or a preceding and succeeding picture for decoding. Therefore, the editing unit cannot be set to one frame unit. In consideration of this point, in this embodiment, one GOP is made up of one I picture.

For example, a recording area in which recording data for one frame is recorded is a predetermined area. MPEG2
Since the variable length coding is used, the amount of generated data for one frame is controlled so that data generated during one frame period can be recorded in a predetermined recording area. Further, in this embodiment, one slice is composed of one macroblock so as to be suitable for recording on a magnetic tape, and one macroblock is applied to a fixed frame having a predetermined length.

FIG. 1 shows an example of the configuration of the recording side of the recording / reproducing apparatus according to this embodiment. At the time of recording, a predetermined interface, for example, SDI (Serial Data Interface)
The digital video signal is input from the terminal 101 via the receiving unit of the above. SDI is an interface defined by SMPTE for transmitting (4: 2: 2) component video signals, digital audio signals, and additional data. An input video signal is converted by a video encoder 102 into a DCT (Discrete Cosine Transform).
form), is converted into coefficient data, and the coefficient data is subjected to variable length coding. The variable length coded (VLC) data from the video encoder 102 is an elementary stream compliant with MPEG2. This output is supplied to one input terminal of the selector 103.

On the other hand, through the input terminal 104, the ANSI
SDTI (Serial Data Transport Inter), which is an interface defined by / SMPTE 305M
face) format data is input. This signal is synchronously detected by SDTI receiving section 105. And
Once stored in the buffer, the elementary stream is extracted. The extracted elementary stream is supplied to the other input terminal of the selector 103.

The elementary stream selected and output by the selector 103 is supplied to a stream converter 106. In the stream converter 106, the MPE
The DCT coefficients arranged for each DCT block based on the G2 rule are replaced with a plurality of DCTs constituting one macroblock.
Through the T block, frequency components are grouped, and the grouped frequency components are rearranged. The rearranged converted elementary stream is stored in the packing and shuffling unit 1.
07.

Since the video data of the elementary stream is variable-length coded, the data length of each macroblock is not uniform. In the packing and shuffling unit 107, macro blocks are packed in a fixed frame. At this time, the portion that protrudes from the fixed frame is sequentially packed into a surplus portion with respect to the size of the fixed frame. Also, system data such as time code is input to the input terminal 108.
Is supplied to the packing and shuffling unit 107, and the system data is subjected to a recording process similarly to the picture data. Also, shuffling is performed in which the macroblocks of one frame generated in the scanning order are rearranged and the recording positions of the macroblocks on the tape are dispersed. Shuffling can improve the image update rate even when data is reproduced in pieces during variable speed reproduction.

The video data and system data from the packing and shuffling unit 107 (hereinafter, also referred to as video data even when system data is included unless otherwise required) are supplied to the outer code encoder 109. A product code is used as an error correction code for video data and audio data. The product code encodes an outer code in a vertical direction of a two-dimensional array of video data or audio data, encodes an inner code in a horizontal direction thereof, and encodes data symbols doubly. As the outer code and the inner code, a Reed-Solomon code can be used.

The output of the outer code encoder 109 is supplied to the shuffling unit 110 and a plurality of ECCs (Error Correction
ig Code) blocks are shuffled to change the order in sync block units. The shuffling in sync block units prevents errors from concentrating on a specific ECC block. Shuffling part 1
Shuffling performed at 10 may be referred to as interleaving. The output of the shuffling unit 110 is
1 and mixed with audio data. In addition,
The mixing unit 111 includes a main memory, as described later.

Audio data is supplied from an input terminal 112. In this embodiment, an uncompressed digital audio signal is handled. The digital audio signal is supplied to an input SDI receiver (not shown)
These are separated by the DTI receiving unit 105 or input through an audio interface. The input digital audio signal is supplied to A
It is supplied to the UX adding unit 114. The delay unit 113 is for time alignment of the audio signal and the video signal.
The audio AUX supplied from the input terminal 115 is auxiliary data, and is data having information related to audio data such as the sampling frequency of audio data. The audio AUX is added to the audio data by the AUX adding unit 114, and is treated the same as the audio data.

The audio data and AUX from the AUX adding unit 114 (hereinafter, AUX unless otherwise necessary)
Is also simply referred to as audio data. ) Is supplied to the outer code encoder 116. Outer code encoder 11
No. 6 encodes an outer code for audio data. The output of the outer code encoder 116 is the shuffling unit 1
17 and undergoes a shuffling process. As audio shuffling, shuffling in sync block units and shuffling in channel units are performed.

The output of the shuffling unit 117 is
1 and the video data and the audio data are converted into data of one channel. The output of the mixing unit 111 is ID
The adding unit 118 is supplied, and the ID adding unit 118 adds an ID including information indicating a sync block number. The output of the ID addition unit 118 is the inner code encoder 119
, And the inner code is encoded. Further, the output of the inner code encoder 119 is supplied to the synchronization adding section 120, and a synchronization signal for each sync block is added. By adding the synchronization signal, recording data in which the sync blocks are continuous is configured. This recording data is supplied to the rotary head 122 via the recording amplifier 121, and is recorded on the magnetic tape 123. In practice, the rotary head 122 is configured such that a plurality of magnetic heads having different azimuths of heads forming adjacent tracks are attached to the rotary drum.

The recording data may be scrambled as required. Further, digital modulation may be performed at the time of recording, and a partial response class 4 and Viterbi code may be used.

FIG. 2 shows an example of the configuration on the reproducing side according to an embodiment of the present invention. Rotating head 1 from magnetic tape 123
The reproduction signal reproduced at 22 is supplied to the synchronization detection unit 132 via the reproduction amplifier 131. Equalization and waveform shaping are performed on the reproduced signal. Further, demodulation of digital modulation, Viterbi decoding, and the like are performed as necessary. The synchronization detection unit 132 detects a synchronization signal added to the head of the sync block. The sync block is cut out by the synchronization detection.

The output of the synchronization detection block 132 is supplied to the inner code encoder 133, where the error of the inner code is corrected. The output of the inner code encoder 133 is the ID interpolation unit 13
The ID of the sync block, which has been supplied to the block No. 4 and made an error by the inner code, for example, a sync block number is interpolated. I
The output of the D interpolation unit 134 is supplied to a separation unit 135, where the video data and the audio data are separated. As described above, video data means DCT coefficient data and system data generated by MPEG intra coding, and audio data is PCM (Pulse Code Modulati
on) means data and AUX.

The video data from the separation unit 135 is subjected to the reverse processing of the shuffling in the deshuffling unit 136. The deshuffling unit 136 performs a process of restoring the shuffling in sync block units performed by the shuffling unit 110 on the recording side. Deshuffling part 136
Is supplied to the outer code decoder 137, and error correction by the outer code is performed. When an error that cannot be corrected occurs, an error flag indicating the presence or absence of the error is set to indicate the presence of the error.

The output of the outer code decoder 137 is supplied to a deshuffling and depacking unit 138. The deshuffling and depacking unit 138 performs processing for restoring shuffling in macroblock units performed by the packing and shuffling unit 107 on the recording side. In the deshuffling and depacking unit 138,
Disassemble the packing applied during recording. That is, the length of the data is returned in units of macroblocks, and the original variable length code is restored. Further, in the deshuffling and depacking unit 138, the system data is separated,
It is taken out to the output terminal 139.

Deshuffling and depacking unit 13
The output of No. 8 is supplied to the interpolation unit 140, and the data for which the error flag is set (that is, there is an error) is corrected. That is, if it is determined that there is an error in the macroblock data before the conversion, the DCT coefficients of the frequency components after the error location cannot be restored. Therefore, for example, the data at the error location is replaced with a block end code (EOB), and the DCT coefficients of the subsequent frequency components are set to zero. Similarly, at the time of high-speed reproduction, only DCT coefficients up to the length corresponding to the sync block length are restored, and the coefficients thereafter are replaced with zero data. Further, the interpolation unit 1
In 40, when the header added to the head of the video data is an error, the header (sequence header, GOP
Header, picture header, user data, etc.) are also recovered.

Since the DCT coefficients are arranged from the DC component and the low-frequency component to the high-frequency component over the DCT block, even if the DCT coefficients are ignored from a certain point onward, the macro block , DCT coefficients from DC and low-frequency components can be distributed evenly to each of the DCT blocks constituting.

The output of the interpolation section 140 is supplied to the stream converter 141. In the stream converter 141, the reverse process to that of the stream converter 106 on the recording side is performed. That is, the DCT coefficients arranged for each frequency component across the DCT blocks are rearranged for each DCT block. Thereby, the reproduced signal is converted into an elementary stream conforming to MPEG2.

As with the recording side, a sufficient transfer rate (bandwidth) is secured for the input and output of the stream converter 141 in accordance with the maximum length of the macroblock. When the length of the macroblock is not limited, it is preferable to secure a bandwidth three times the pixel rate.

The output of the stream converter 141 is supplied to the video decoder 142. Video decoder 142
Decodes the elementary stream and outputs video data. That is, the video decoder 142 performs an inverse quantization process and an inverse DCT process. The decoded video data is taken out to the output terminal 143. For the interface with the outside, for example, SDI is used. In addition, the elementary stream from the stream converter 141 is supplied to the SDTI transmitting unit 144. Although illustration of the path is omitted, the SDTI transmission unit 144 is also supplied with system data, reproduced audio data, and AUX, and
It is converted into a stream having a data structure of the TI format. The stream from the SDTI transmission unit 144 is output to the outside through the output terminal 145.

The audio data separated by the separation unit 135 is supplied to the deshuffling unit 151. The deshuffling unit 151 performs a process opposite to the shuffling performed by the shuffling unit 117 on the recording side. The output of the deshuffling unit 117 is supplied to the outer code decoder 152, and error correction by the outer code is performed. Outer code decoder 152
Output the error-corrected audio data. An error flag is set for data having an uncorrectable error.

The output of the outer code decoder 152 is supplied to an AUX separation section 153, where the audio AUX is separated.
The separated audio AUX is taken out to the output terminal 154. The audio data is supplied to the interpolation unit 155. The interpolating unit 155 interpolates a sample having an error. As the interpolation method, it is possible to use an average value interpolation for interpolating with the average value of correct data before and after in time, a previous value hold for holding a previous correct sample value, and the like. The output of the interpolation unit 155 is supplied to the output unit 156. The output unit 156 performs a mute process for inhibiting the output of an audio signal that is in error and cannot be interpolated, and performs a delay amount adjustment process for time alignment with a video signal. The reproduced audio signal is extracted from the output unit 156 to the output terminal 157.

Although not shown in FIGS. 1 and 2, a timing generator for generating a timing signal synchronized with input data, a system controller (microcomputer) for controlling the overall operation of the recording / reproducing apparatus, and the like are provided. Have been.

In this embodiment, recording of a signal on a magnetic tape is performed by a helical scan method in which an oblique track is formed by a magnetic head provided on a rotating rotary head. A plurality of magnetic heads are provided on the rotating drum at positions facing each other. That is, when the magnetic tape is wound around the rotary head at a winding angle of about 180 °, a plurality of tracks can be simultaneously formed by rotating the rotary head by 180 °. The magnetic heads are formed as a set of two magnetic heads having different azimuths. The plurality of magnetic heads are arranged such that azimuths of adjacent tracks are different from each other.

FIG. 3 shows an example of a track format formed on a magnetic tape by the rotary head described above. This is an example in which video and audio data per frame are recorded on eight tracks. For example, the frame frequency is 29.97 Hz, and the rate is 50 Mbp
s, the number of effective lines is 480, and the number of effective horizontal pixels is 720
A pixel interlace signal (480i signal) and an audio signal are recorded. When the frame frequency is 25H
z, the rate is 50 Mbps, the number of effective lines is 576, and the number of effective horizontal pixels is 720.
6i signal) and audio signal can also be recorded in the same tape format as in FIG.

One segment is constituted by two tracks having different azimuths. That is, eight tracks are composed of four segments. Track number corresponding to azimuth for a set of tracks constituting a segment

[0] and a track number [1] are assigned. In the example shown in FIG. 3, track numbers are exchanged between the first eight tracks and the second eight tracks, and different track sequences are assigned to each frame. Thus, even if one of the set of magnetic heads having different azimuths becomes unreadable due to clogging or the like, the influence of an error can be reduced by using the data of the previous frame.

In each of the tracks, a video sector in which video data is recorded is arranged on both ends, and an audio sector in which audio data is recorded is arranged between the video sectors. 3 and FIG. 4, which will be described later, show the arrangement of audio sectors on the tape.

In the track format shown in FIG. 3, eight channels of audio data can be handled. A1 to A8 indicate sectors of channels 1 to 8 of the audio data, respectively. The audio data is recorded with its arrangement changed in segment units. For audio data, audio samples generated in one field period (for example, when the field frequency is 29.97 Hz and the sampling frequency is 48 kHz, 800 or 801 samples) are divided into even-numbered samples and odd-numbered samples. Each sample group and AUX form one ECC block of a product code.

In FIG. 3, since data for one field is recorded on four tracks, two ECC blocks per channel of audio data are recorded on four tracks. The data of two ECC blocks (including the outer code parity) is divided into four sectors, and as shown in FIG. 3, the data is dispersedly recorded on four tracks. Two ECCs
A plurality of sync blocks included in the block are shuffled. For example, two ECC blocks of channel 1 are constituted by four sectors to which reference numbers A1 are assigned.

In this example, video data of 4 ECC blocks is shuffled (interleaved) with respect to one track, divided into upper sectors and lower sides, and recorded. In the lower sector video sector, a system area is provided at a predetermined position.

In FIG. 3, SAT1 (Tr) and SAT2 (Tm) are areas where servo lock signals are recorded. In addition, a gap of a predetermined size (Vg1, Sg1, Ag, Sg) is provided between the recording areas.
2, Sg3 and Vg2).

FIG. 3 shows an example in which data per frame is recorded on eight tracks, but depending on the format of the data to be recorded / reproduced, data per frame is recorded in four tracks.
Recording can be performed on tracks, six tracks, and the like.
FIG. 4A shows a format in which one frame has six tracks. In this example, the track sequence is

Only [0] is set.

As shown in FIG. 4B, data recorded on the tape is composed of a plurality of equally-spaced blocks called sync blocks. FIG. 4C schematically shows a configuration of the sync block. As will be described later in detail, the sync block is composed of a SYNC pattern for detecting synchronization, an ID for identifying each sync block, a DID indicating the content of subsequent data, a data packet, and an inner code parity for error correction. Is done. Data is,
It is treated as a packet in sync block units. That is, the smallest data unit to be recorded or reproduced is one sync block. A number of sync blocks are arranged (FIG. 4B) to form, for example, a video sector (FIG. 4A).

FIG. 5 more specifically shows the data structure of a sync block of video data, which is the minimum unit of recording / reproduction. In this embodiment, one or two macroblocks of data (VLC data) are stored for one sync block according to the format of video data to be recorded, and the size of one sync block is reduced. The length is changed according to the format of the video signal to be handled. As shown in FIG. 5A, one sync block is
From the beginning, a 2-byte SYNC pattern, a 2-byte I
D, a 1-byte DID, for example, a data area variably defined between 112 bytes and 206 bytes, and a 12-byte parity (inner code parity). Note that the data area is also called a payload.

The first two bytes of the SYNC pattern are used for synchronization detection and have a predetermined bit pattern. Synchronization detection is performed by detecting a SYNC pattern that matches the unique pattern.

FIG. 6A shows an example of the bit assignment of ID0 and ID1. The ID has important information inherent to the sync block, and each ID has 2 bytes (ID
0 and ID1). ID0 is 1
The identification information (SYNC ID) for identifying each of the sync blocks in the track is stored. SYNC
The ID is, for example, a serial number assigned to a sync block in each sector. The SYNC ID is represented by 8 bits. SYNC IDs are separately assigned to video sync blocks and audio sync blocks.

ID1 stores information on the track of the sync block. When the MSB side is bit 7 and the LSB side is bit 0, with respect to this sync block,
Bit 7 indicates whether the track is above (upper) or below (Lo)
wer), and bits 5 to 2 indicate the segment of the track. Bit 1 indicates the track number corresponding to the azimuth of the track.
Are bits for distinguishing video data and audio data by this sync block.

FIG. 6B shows an example of bit assignment of DID in the case of video. The DID stores information related to the payload. The content of DID differs between video and audio based on the value of bit 0 of ID1 described above. Bits 7 to 4 are undefined (Reserve
d). Bits 3 and 2 are the mode of the payload, for example, indicating the type of the payload.
Bits 3 and 2 are auxiliary. Bit 1 indicates that one or two macroblocks are stored in the payload. Bit 0 indicates whether the video data stored in the payload is an outer code parity.

FIG. 6C shows an example of bit assignment of DID in the case of audio. Bits 7-4 are R
Eserved. Bit 3 indicates whether the data stored in the payload is audio data or general data. If compression-encoded audio data is stored in the payload, bit 3 is a value indicating the data.
Bit 2 to bit 0 store information of a 5-field sequence in the NTSC system. That is, NT
In the SC system, the sampling frequency of an audio signal for one field of a video signal is 48 kHz.
Is either 800 samples or 801 samples, and this sequence is aligned every five fields. Bit 2 to bit 0 indicate where in the sequence it is located.

Referring back to FIG. 5, FIGS. 5B to 5E
Shows an example of the above-mentioned payload. 5B and 5C
Shows an example in which video data (variable-length coded data) of 1 and 2 macroblocks is stored for the payload, respectively. In the example shown in FIG. 5B in which one macroblock is stored, length information LT indicating the length of the following macroblock is arranged in the first three bytes.
The length information LT may or may not include its own length. 5C shown in FIG.
In an example in which a macroblock is stored, the length information LT of the first macroblock is arranged at the head, and the first macroblock is arranged subsequently. Then, length information L indicating the length of the second macroblock following the first macroblock
T is arranged, followed by a second macroblock.
The length information LT is information necessary for depacking.

FIG. 5D shows video A for the payload.
An example in which UX (auxiliary) data is stored will be described. The head length information LT describes the length of the video AUX data. Subsequent to the length information LT, 5-byte system information, 12-byte PICT information, and 92-byte user information are stored. The remaining portion of the payload length is reserved.

FIG. 5E shows an example in which audio data is stored in the payload. Audio data can be packed over the entire length of the payload. The audio signal is not subjected to compression processing or the like, and is handled in, for example, a PCM format. The present invention is not limited to this, and audio data compressed and encoded by a predetermined method can be handled.

In this embodiment, the length of the payload, which is the storage area for the data of each sync block, is set optimally for the video sync block and the audio sync block, and is not equal to each other. . In addition, the length of a sync block for recording video data and the length of a sync block for recording audio data are set to optimal lengths according to the signal format. Thereby, a plurality of different signal formats can be handled uniformly.

FIG. 7A shows the order of DCT coefficients in video data output from the DCT circuit of the MPEG encoder. Starting from the DC component at the upper left in the DCT block, in the direction where the horizontal and vertical spatial frequencies increase,
DCT coefficients are output by zigzag scan. As a result, as shown in an example in FIG. 7B, a total of 64 (8
DCT coefficients of (pixel × 8 lines) are obtained by being arranged in the order of frequency components.

The DCT coefficient is equal to the V of the MPEG encoder.
Variable length coding is performed by the LC unit. That is, the first coefficient is fixed as a DC component, and the next component (AC
From the component), codes are assigned corresponding to the run of zero and the subsequent level. Therefore, the variable-length coded output for the coefficient data of the AC component is converted from the low (low-order) coefficient of the frequency component to the high (high-order) coefficient of AC ₁ ,
AC ₂ , AC ₃ ,... The elementary stream includes DCT coefficients subjected to variable length coding.

The stream converter 106 rearranges the DCT coefficients of the supplied signal. That is, in each macroblock, DCT coefficients arranged in order of frequency components for each DCT block by zigzag scan are rearranged in order of frequency components over each DCT block constituting the macroblock.

FIG. 8 shows this stream converter 106.
2 schematically shows the rearrangement of the DCT coefficients in. (4:
2: 2) In the case of a component signal, one macroblock is composed of four DCT blocks (Y ₁ ,
Y _2, and Y ₃ and Y _4), chroma signal Cb, DCT blocks (Cb ₁ of every two according to each of Cr, C
b ₂ , Cr ₁ and Cr ₂ ).

As described above, the video encoder 102
Then, a zigzag scan is performed in accordance with the rules of MPEG2, and as shown in FIG. 8A, for each DCT block,
DCT coefficient is changed from DC component and low frequency component to high frequency component,
The frequency components are arranged in order. When scanning of one DCT block is completed, scanning of the next DCT block is performed, and similarly, DCT coefficients are arranged.

That is, in the macro block, DCT blocks Y ₁ , Y ₂ , Y ₃ and Y ₄ , DCT block C ₄
For each of b ₁ , Cb ₂ , Cr ₁ and Cr ₂ , the DCT coefficients are arranged in order of frequency from the DC component and the low-frequency component to the high-frequency component. Then, [DC, AC ₁ , AC
_2, AC _3, and..], So that codes are assigned, it is variable length coded.

In the stream converter 106, the variable-length coded and arranged DCT coefficients are once decoded into variable-length codes to detect the breaks of each coefficient, and the frequency is spread over each DCT block constituting a macroblock. Summarize by component. This is shown in FIG. 8B. First, the DC components of the eight DCT blocks in the macroblock are summarized, the AC coefficient components of the eight DCT blocks having the lowest frequency components are summarized, and the AC coefficients of the same order are grouped in order. The coefficient data is rearranged across the DCT blocks.

The rearranged coefficient data is DC
(Y ₁ ), DC (Y ₂ ), DC (Y ₃ ), DC
(Y ₄ ), DC (Cb ₁ ), DC (Cb ₂ ), DC (C
r ₁ ), DC (Cr ₂ ), AC ₁ (Y ₁ ), AC ₁ (Y
₂ ), AC ₁ (Y ₃ ), AC ₁ (Y ₄ ), AC ₁ (Cb
₁ ), AC ₁ (Cb ₂ ), AC ₁ (Cr ₁ ), AC
₁ (Cr ₂ ),. Where DC, AC ₁ ,
AC ₂ ,... Are, as described with reference to FIG. 7, each of the variable-length codes assigned to the set consisting of the run and the subsequent level.

The converted elementary stream in which the order of the coefficient data has been rearranged by the stream converter 106 is supplied to the packing and shuffling unit 107. The data length of the macroblock is the same for the converted elementary stream and the elementary stream before conversion. In the video encoder 102, even if the length is fixed in GOP (one frame) units by bit rate control, the length varies in macroblock units. The packing and shuffling unit 107 applies the data of the macroblock to the fixed frame.

FIG. 9 schematically shows a packing process of a macroblock in the packing and shuffling unit 107. The macro block is applied to a fixed frame having a predetermined data length and is packed. The data length of the fixed frame used at this time is matched with the sync block length, which is the minimum unit of data during recording and reproduction. This is to simplify the processing of shuffling and error correction coding. In FIG. 9, for simplicity, it is assumed that one frame includes eight macroblocks.

As shown in an example in FIG. 9A, the lengths of eight macroblocks are different from each other due to the variable length coding. In this example, as compared with the length of one sync block, which is a fixed frame, the data of macro block # 1, the data of # 3 and the data of # 6 are each longer, and the data of macro block # 2, the data of # 5, # 7 data and # 8
The data of each is short. The data of the macro block # 4 has a length substantially equal to one sync block.

By the packing process, macro blocks are packed into a fixed-length frame having a length of one sync block. Data can be packed without excess or shortage because the amount of data generated in one frame period is controlled to a fixed amount. As shown in an example in FIG. 9B, a macroblock longer than one sync block is divided at a position corresponding to the sync block length. Of the divided macroblocks, the part (overflow part) that protrudes from the sync block length is placed in an area that is vacant in order from the top,
That is, it is packed after a macroblock whose length is less than the sync block length.

In the example of FIG. 9B, the macro block # 1
The portion that exceeds the sync block length is first packed after the macro block # 2, and when it reaches the length of the sync block, it is packed after the macro block # 5. Next, the portion of the macro block # 3 that is outside the sync block length is packed behind the macro block # 7. Further, the part of the macro block # 6 that protrudes from the sync block length is packed after the macro block # 7, and the part that protrudes further is packed after the macro block # 8. Thus, each macroblock is packed in a fixed frame of the sync block length.

The length of each macroblock can be checked in advance by the stream converter 106.
As a result, the packing unit 107 can know the end of the data of the macro block without decoding the VLC data and checking the contents.

FIG. 10 shows an example of an error correction code used in one embodiment. FIG. 10A shows one ECC block of an error correction code for video data.
B is 1E of an error correction code for audio data.
Indicates a CC block. In FIG. 10A, VLC data is data from the packing and shuffling unit 107. A SYNC pattern, ID, and DID are added to each row of the VLC data, and a parity of an inner code is added to form one SYNC block.

That is, a 10-byte parity of the outer code is generated from a predetermined number of symbols (bytes) aligned in the vertical direction of the array of VLC data, and the ID, DID, and VLC data (or outer) are aligned in the horizontal direction. Parity of the inner code is generated from a predetermined number of symbols (bytes) of the code parity. In the example of FIG. 10A, 10 outer code parity symbols and 12 inner code parity symbols are added. As a specific error correction code, a Reed-Solomon code is used. FIG.
At 0A, the difference between the lengths of VLC data in one SYNC block is 59.94 Hz, 25 Hz, and 23.97.
This is because the frame frequency of video data is different, such as 6 Hz.

As shown in FIG. 10B, the product code for audio data is the same as that for video data.
The parity of the 10-symbol outer code and the parity of the 12-symbol inner code are generated. In the case of audio data, the sampling frequency is, for example, 48 kHz, and one sample is quantized to 24 bits. One sample may be converted to another number of bits, for example, 16 bits. According to the difference in the frame frequency described above, 1SYN
The amount of audio data in the C block is different.
As described above, one field of audio data /
One channel forms two ECC blocks.
One ECC block includes one of even-numbered and odd-numbered audio samples and audio AUX as data.

FIG. 11 shows the configuration on the recording side of this embodiment described above, focusing on the clock signal. The video input processing unit performs packing, which packs variable-length data into the data area of the sync block, and shuffling, which makes the position of the macroblock on the screen and the recording position on the tape uncorrelated. A shuffling unit 107 is included. The audio data input processing unit includes a delay unit 113 and an AUX adding unit 114. The delay unit 113 is provided for time alignment with video data. AUX is auxiliary data,
This is data having information related to audio data such as the sampling frequency of audio data. Audio AUX is treated the same as audio data.

As described above, conventionally, the main processing unit is usually operated with the operation clock ckv of the video input processing unit or a clock related thereto (for example, a clock having a double frequency). In this embodiment, the main processing unit operates by a clock ckm independent of the clock ckv. Operation clock c
km is a frequency different from the clock ckv of the video input processing unit and the clock ckm of the audio input processing unit. In this embodiment, the clock frequency relationship is c
The frequency of kv is selected as the frequency of ckm. Further, the operation clock ckm of the main processing unit can be changed according to the format of the recording data. For example, in the case of a format in which the amount of recording data is large, the frequency of the clock ckm is set to be high. Further, as an interface for transmitting data between the processing units having different operation clock frequencies, the
O162 and 163 are provided. FIFO is
For example, it is constituted by a RAM, and performs rate conversion from an input data rate to an output data rate.

The configuration of the main processing section is different from the configuration shown in FIG. This is because packing, outer code encoding, and shuffling processing are different. The process of FIG. 14 will be described. First, a data packet having a length (fixed frame length) that fits in a fixed frame and an overflow portion that protrudes from the data packet are divided, and the data packet having the fixed frame length is written into a main memory (SDRAM). Write the part to dedicated memory. Then, of the data packets written in the main memory, the overflow portion is sequentially written in an empty area after the data packet shorter than the fixed frame. This process is performed for one frame.

Next, the data of the code series of the outer code is read from the main memory, and the outer code is encoded. The parity of the generated outer code is written into the main memory again. By controlling the write address to this main memory,
Shuffling is performed in sync block units. When the encoding of the outer code for one track or for a plurality of tracks constituting one field or one frame is completed, the data and the parity of the outer code are read from the main memory and supplied to the inner code encoder. As described above, in the configuration shown in FIG. 14, the packing and the encoding of the outer code are performed independently.

On the other hand, in this embodiment, the fixed frame length data and the overflow portion are stored in the main memory (SDR) by referring to the length information LT of each macroblock.
AM) 160 and stored separately. The area for storing the fixed frame length data is a packing processing area of the main memory 160. If the data length is shorter than the fixed frame length, an empty area is created in the corresponding fixed frame of the main memory 160. Shuffling is performed by controlling the address at the time of writing.

Next, data of a fixed frame length is read from the main memory 160 into a memory for one ECC block prepared in the outer code encoder 109, and if there is an empty area in the data of the fixed frame length, Then, the overflow part is read there and the data is packed into the fixed frame length. When the data for one ECC block is read, the reading process is temporarily suspended, and the outer code encoder 10
9, the parity of the outer code is generated. The outer code parity is stored in the memory of the outer code encoder 109. When the processing of the outer code encoder 109 is completed for one ECC block, the data and the outer code parity are rearranged from the outer code encoder 109 in the order of performing the inner code, and the packing processing area of the main memory 160 and another inner code processing area. Write back to The shuffling (shuffling unit 110) in sync block units can be performed by controlling the address at which the data in which the encoding of the outer code has been completed is written back to the main memory 160.

The fixed frame length and the overflow portion are separated so that data is written to the first area of the main memory 160 (first packing process), and the overflow portion is packed in the memory for the outer code encoder 109. The process of reading the data (the second packing process), the process of generating the outer code parity, and the process of writing back the data and the outer code parity to the second area of the main memory 160 are performed in units of one ECC block. Since the outer code encoder 109 includes the memory having the size of the ECC block, the frequency of access to the main memory 160 can be reduced as compared with the configuration shown in FIG.

A predetermined number of Es included in one picture
When the processing of the CC block (for example, 32 ECC blocks) is completed, the packing of one picture and the encoding of the outer code are completed. The data read from the inner code processing area of the main memory 160 and the parity of the outer code are FI
It is supplied to the output processing unit via the FO 161, the ID is added by the ID adding unit 118,
At 9, the parity of the inner code is added.

It is to be noted that a sync block called null sync, in which valid data is not arranged, is introduced into the ECC block, and the ECC block is provided with an ECC block for the difference in recording video signal format.
The flexibility of the configuration of the C block may be provided. The null sync is generated in the packing and shuffling block 107 and written to the main memory 160. Therefore, since the null sync has a data recording area, it can be used as a recording sync for the overflow portion.

In the case of audio data, even-numbered samples and odd-numbered samples of one-field audio data form different ECC blocks. Since the ECC outer code sequence is composed of audio samples in the input order, the outer code encoder 116 generates an outer code parity each time an outer code sequence audio sample is input. The shuffling unit 117 performs shuffling (channel units and sync block units) by address control when writing the output of the outer code encoder 116 to the main memory.

FIG. 12 shows a more specific configuration of one embodiment of the present invention. In FIG. 12, reference numeral 164 denotes an interface of the main memory 160. The interface 164 controls a write / read operation of the main memory 160. The packing and shuffling unit 107 is constituted by the packing unit 107a, the video shuffling unit 107b, and the packing unit 107c.

That is, the packing unit 107a separates the fixed frame length and the overflow portion from each other and separates them from the main memory 160.
In the first area (first packing process). The video shuffling unit 107b performs shuffling by controlling the write address. Packing unit 107c is outer code encoder 109
(The second packing process) of packing and reading the overflow portion into the memory to the memory. The video shuffling unit 110 performs a process of writing the data and the outer code parity back to the second area of the main memory 160,
Shuffling is performed by controlling the address of the rewriting process.

As shown in FIG. 12, the data read from the main memory 160 via the interface 164 is processed by the ID addition section 118, the inner code encoder 119, and the synchronization addition section 120. The output data of the synchronization adding section 120 is converted into bit serial data. The output serial data is processed by the partial response class 4 precoder 125. This output is digitally modulated as necessary, and supplied to the rotary head via the recording amplifier 121.

Further, a CPU interface denoted by 126 is provided, and can receive data from the CPU 127 functioning as a system controller. This data includes shuffling table data, parameters related to the format of the recording video signal, and the like. By shuffling table data,
A video shuffling table 128v and an audio shuffling table 128a are configured. The shuffling table 128v is used for the video shuffling unit 1
Address conversion for shuffling of 07b and 110 is performed. The shuffling table 128a performs an address conversion for the audio shuffling 117.

As described above, in one embodiment of the present invention, the operation clock ckm of the main processing unit is selected to be higher in frequency than the operation clock ckv of the input processing unit. FIG. 13 shows an outline of processing when the clock ckv and ckrf are constant and the operation clock ckm of the main processing unit is changed. FIG. 13A shows a video frame synchronized with the input video data. The input processing unit operates as shown in FIG. 13B in synchronization with the input video frame.
P1, P2,... Represent periods during which the input processing unit processes data of each frame.

In FIG. 13C, the main processing unit sets P1
The data of each frame is processed as indicated by 1, P12,.... Then, in FIG. 13D, P2
As shown by 1, P22,..., The output processing unit performs processing. When the operation clock ckm of the main processing unit is further increased, as shown by P31, P32,... In FIG. 13E, the time required for the processing of the main processing unit becomes shorter, and as shown by P41, P42,. In addition, the timing at which the output processing unit starts processing is advanced. Therefore, the delay time from when the input processing unit starts data processing to when the output processing unit starts processing can be adjusted by the frequency of the operation clock ckm as indicated by Td1 and Td2. In other words, even if the data amount of one frame (one picture) to be processed by the main processing unit is different because the format of the video data to be recorded is different,
The delay time can be made constant by adjusting the frequency of the clock ckm.

When the operation clocks of the input processing section and the main processing section both operate with a clock having a frequency determined by the rate of the input video data, in FIG.
13H, the delay time Td3 is fixed, as can be seen from the timing of the processing of the main processing unit indicated by P51, P52,... And the processing of the output processing unit indicated by P61, P62,.

In the present invention, the operation clock c of the main processing unit is set by parallelizing the processing of the main processing unit.
km may be lower than the frequency of the operation clock ckv of the input processing unit. In the case where the processing of the main processing unit is extremely large and the access to the memory and the external elements is extremely large, and when the processing of the main processing unit is concentrated in a short time, the circuit load may become heavy only at that moment. When the recording signal processing unit is integrated into a circuit, if the load on a specific circuit part becomes heavy, it may affect the power supply of the integrated circuit depending on the degree of integration, and thus the power supply to the device using the recording signal processing unit. It could be shaken. In this case, as described above, if the frequency of the operation clock ckm of the main processing unit is lower than that of the operation clock ckv of the input processing unit, the processing can be dispersed, thereby preventing an instantaneous increase in load. It is possible to do.

The present invention can be applied to a case where data is recorded on a recording medium other than a tape, for example, a disc-shaped recording medium.

[0106]

According to the present invention, while the input processing section operates with the operation clock synchronized with the video data, the main processing section can operate with the operation clock independent of the operation clock of the input processing section. Therefore, it is not necessary to separately design a main processing unit for a plurality of video data having different frame frequencies, and it is also possible to adjust a delay time caused by the processing of the main processing unit, and further to process the main processing unit. Concentration can prevent the load on the power supply from becoming momentarily heavy.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration on a recording side according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a reproducing side according to an embodiment of the present invention.

FIG. 3 is a schematic diagram illustrating an example of a track format.

FIG. 4 is a schematic diagram illustrating another example of a track format.

FIG. 5 is a schematic diagram illustrating a plurality of examples of a configuration of a sync block.

FIG. 6 shows an ID and a DID added to a sync block.
FIG.

FIG. 7 is a schematic diagram for explaining an output method of a video encoder and variable-length encoding.

FIG. 8 is a schematic diagram for explaining rearrangement of an output order of a video encoder.

FIG. 9 is a schematic diagram for explaining a process of packing data rearranged in order into a sync block.

FIG. 10 is a schematic diagram for explaining an error correction code for video data and audio data.

FIG. 11 is a block diagram showing an embodiment of the present invention based on a clock system.

FIG. 12 is a more specific block diagram of a recording signal processing unit.

FIG. 13 is a timing chart conceptually showing a processing flow of a recording signal processing unit.

FIG. 14 is a block diagram of an example of a recording signal processing unit used for reference of the description of the present invention.

[Explanation of symbols]

107 ... packing and shuffling part, 10
9, 116 ... outer code encoder, 110, 117
..Shuffling section, 118... ID adding section, 120
... Synchronization addition unit, 160 ... Main memory

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G11B 20/18 572 G11B 20/18 572B 572G // H04N 5/92 H04N 5/92 HF term (Reference) 5C053 FA03 FA22 GA01 GA11 GB07 GB10 GB11 GB15 GB18 GB22 GB26 GB32 GB38 JA05 JA12 JA21 KA01 KA18 LA15 5D044 AB05 AB07 BC01 CC01 DE14 DE32 DE37 DE68 EF03 FG21 GL28 GM17

Claims (5)

[Claims] 1. A data processing device for converting video data into a signal form for transmission, comprising: an input processing unit for packing video data into a data area of a predetermined length; A main processing unit for encoding, and a synchronization pattern and I
D, an output processing unit constituting a sync block by adding D, wherein the input processing unit operates by a first clock synchronized with the video data, and the main processing unit is independent of the first clock. A data processing device operated by a second clock having a frequency. 2. A data recording apparatus for recording video data on a recording medium, comprising: an input processing unit for packing the video data into a data area of a predetermined length; And a synchronization pattern and I in the data from the main processing unit.
An output processing unit that forms a sync block by adding D, and a recording unit that records the output of the output processing unit on a recording medium, wherein the input processing unit uses a first clock synchronized with the video data A data recording device that operates, wherein the main processing unit operates with a second clock having a frequency independent of the first clock. 3. The data transmission device according to claim 1, wherein the video data is data obtained by performing variable length coding on coefficient data generated by DCT. 4. The input processing unit according to claim 1, wherein the input processing unit further includes an audio data processing unit, and the audio data processing unit includes a delay unit for adjusting time with the video data. And equipment. 5. The product code according to claim 1, wherein the error correction code is a product code, and the outer code of the product code is encoded in the main processing unit, and the inner code of the product code is encoded. In the output processing unit.