JP2000137619A - Microcomputer - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To enable switching of an instruction decoding mode in conjunction with an interrupt. SOLUTION: An interrupt control circuit (11) for judging an instruction decoding mode corresponding to the content of a fetched interrupt and selection information of a decoder involved in instruction decoding based on a judgment result of the interrupt control circuit. A corresponding mode designating circuit (12) for outputting the instruction to the instruction decoding unit; determining an instruction decoding mode corresponding to each of the contents of the fetched interrupt; and engaging in instruction decoding based on the determination result By outputting the selection information of the decoder to the instruction decoding unit, switching of the instruction decoding mode based on the interrupt is achieved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer for performing a predetermined arithmetic processing by executing a series of instructions constituting a program, and is applied to, for example, a one-chip microcomputer (single-chip microcomputer). Regarding effective technology.

[0002]

2. Description of the Related Art A microcomputer (sometimes referred to as a microprocessor) includes necessary peripheral circuits centered on a CPU (central processing unit) on a single semiconductor substrate and holds an operation program for the peripheral circuits. Program R
Built-in OM (read only memory).

A microcomputer has been proposed which has a plurality of instruction decoding modes and can increase the types of instructions without increasing the code length of the instructions.

An example of a document describing such a microcomputer is disclosed in Japanese Patent Application Laid-Open No. 9-330219.
JP, JP-A-9-160774, JP-A-5-1
JP-A-43322, JP-A-5-120003, and JP-A-2-19927.

[0005]

The switching of the instruction decoding mode is generally performed by executing a predetermined switching instruction or by switching an area where the instruction is stored.

However, when a switching command is used, a processing step for that is required, and a switching command must be prepared in all command decoding modes, which means that a plurality of the same switching commands are provided. ineffective.

On the other hand, if the method of switching the area where the instruction is stored is switched, the number of instruction types increases as the switching instruction becomes unnecessary, but the memory area may be switched for each instruction decoding mode. When there are many processes using the instruction decoding mode, the memory area becomes insufficient.On the contrary, when there are few processes using the instruction decoding mode, the memory area corresponding to the instruction decoding mode becomes excessive. As a result, the use efficiency of the memory is reduced. If the degree of freedom of the memory area is to be increased, the scale of the decoding circuit of the memory is inevitably increased.

An object of the present invention is to provide a microcomputer capable of efficiently increasing the number of instruction types and switching between a plurality of instruction decoding modes while maintaining high memory use efficiency. is there.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, an instruction fetch means (509) for fetching an instruction code from a program memory.
And an instruction decoding unit (510) that has a plurality of instruction decoding modes defined in advance corresponding to the interrupt, and is capable of decoding an instruction fetched by the fetch means in the designated instruction decoding mode. The microcomputer includes an interrupt control unit (1) for determining an instruction decoding mode corresponding to an interrupt and designating the mode for the instruction decoding unit.

According to the above-described means, the interrupt control unit determines the instruction decoding mode corresponding to each of the contents of the fetched interrupt, and the corresponding mode designation circuit sets the decode mode corresponding to the determination result to the instruction mode. Output to the decoding unit. This achieves switching of instruction decoding mode based on interrupts.

An instruction fetch means (509) for fetching an instruction code from the program memory and a plurality of instruction decoding modes are provided, and the instructions fetched by the fetch means can be read in a designated instruction decoding mode. An instruction decoding unit (510) capable of decoding, an interrupt control circuit (11) for determining an instruction decoding mode corresponding to each content of the fetched interrupt, and a corresponding decode based on the determination result of the interrupt control circuit A microcomputer can be configured including a corresponding mode designating circuit (12) for outputting a mode to the instruction decoding unit.

At this time, the instruction decoding unit includes a plurality of decoders (21 to 24) and a first selection circuit (26) for distributing the instruction code fetched by the instruction fetch circuit to the plurality of decoders. A second selection circuit (27) for selectively transmitting output signals of the plurality of decoders to a subsequent circuit, and an operation of the first selection circuit and the second selection circuit based on designation of the corresponding mode designation circuit And a switching circuit (25) for controlling the control.

Further, in order to facilitate return to the mode before the decoding mode is changed, a mode determination circuit (13) for determining a mode based on an interrupt and a mode determination circuit based on the determination result of the mode determination circuit are provided. Mode holding means (14) for holding the designated mode, and mode saving means (15) for saving information for returning to the mode immediately before the mode currently held in the mode holding means. Can configure the corresponding mode designating circuit.

[0016]

FIG. 3 shows a computer system to which a microcomputer according to the present invention is applied.

This computer system has a bus BUS
, Microcomputer 131, SDRAM
(Synchronous dynamic random access
Memory) 132, SRAM (static random
Access memory 133, ROM (read only)
Memory) 134, peripheral device control unit 135, display control system 1
36 and the like are communicably connected to each other and perform predetermined data processing according to a predetermined program. The microcomputer 131 is a logical core of the present system. SDRAM 132, SRAM 13
3, and the ROM 134 are positioned as internal storage devices. The SDRAM 132 is loaded with application programs and data necessary for calculation and control by the microcomputer 131. SRAM 13
3 is used as a cache memory. The peripheral device control unit 135 controls the operation of the external storage device 138 and controls information input from the keyboard 139 and the like. The display control of the display control system 136 allows C
Information display control on the RT display 140 is performed.

FIG. 4 shows a configuration example of the microcomputer 131.

Although not particularly limited, the microcomputer 1 is formed on a single semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

The microcomputer 131 is not particularly limited, but includes a CPU (central processing unit) 50, a ROM (read only memory) 4, a RAM (random access memory) 7, a timer 53, and a serial communication interface (SCI). 54, an A / D (analog / digital) converter 55, an interrupt control unit 1, and functional blocks such as first to ninth ports 41 to 49.
For example, they are coupled so that signals can be exchanged with each other.

The main storage devices of the microcomputer 131 are the above-mentioned RAM 51 and ROM 4.
Reference numeral 51 is used as a work area of the CPU 50 or a temporary storage area of data. The ROM 4 is not particularly limited,
It has an operation program for the CPU 50. This ROM4
Although not particularly limited, an EPROM writer can write information from outside the microcomputer by an EPROM writer.
A ROM (electrically programmable read only memory) is used.

On the peripheral edge of the semiconductor substrate, for example, a large number of bonding pads are arranged as electrode pads. For example, bonding pads P10 to P17 coupled to the input / output terminals of the first to ninth ports 41 to 49,
P20 to P24, P30 to P37, P40 to P47, P
50 to P57, P60 to P63, P70 to P77, P8
0 to P87, P90 to P97, and a bonding pad XTA coupled to an input terminal of the clock generator 56.
L, EXTAL, etc. are arranged. An oscillator (not shown) is connected to the bonding pads XTAL and EXTAL, or an external clock is supplied.

In the assembling process, the microcomputer 131 as a chip or a pellet configured as described above is die-bonded to the mount portion of the package, and is sealed after the bonding pads are wire-bonded to the lead terminals of the package.

The microcomputer 131 interfaces with the outside through various ports. The port function can be specified by setting the operation mode, and the operation mode that outputs an address signal to the outside to access an external memory or a peripheral device is also supported.

FIG. 5 shows an example of the configuration of the CPU 50.

An instruction fetch circuit 509 is coupled to the internal data bus 6 and fetches an instruction code stored in the ROM 4. At the subsequent stage of the instruction fetch circuit 109, an instruction decoding unit 510 for decoding the fetched instruction code to decode the instruction is arranged. The result of the instruction decoding by the instruction decoding unit 510 is input to the control unit 511 arranged at the subsequent stage. The control unit 511 sends appropriate control signals to the inside and the outside of the CPU 50, and executes necessary operations designated by the instruction decoded by the instruction decoding unit 510 in several steps. I do.

Arithmetic Logic Unit (ALU) 507
Is a hardware unit for performing necessary numerical and logical operations on data. Numerical operations include addition, subtraction, multiplication, division, etc.
There is a logical product operation, which is executed based on a binary addition circuit. To such an ALU 507, a flag flip-flop 506 for holding various states generated during the operation is connected. Further, a temporary register 505 for temporarily holding data for the operation in the ALU 507 and various register groups 116 are connected to the internal bus 103.

Although not particularly limited, the various register groups 116 are a program counter PC which is a register for storing an address of an instruction to be executed next by the CPU 50, and a status register for storing a status of an instruction execution result. SR, general-purpose registers R0 to Rn appropriately used for various arithmetic processes, and a stack pointer SP which is a register for designating a task stack area.

FIG. 1 shows a configuration example of the interrupt control unit 1 and the instruction decoding unit 510.

The interrupt control unit 1 includes, but is not limited to, an interrupt control circuit 11 and a corresponding mode designating circuit 12. Upon receiving the interrupt request 101, the interrupt control circuit 11 determines the content of the request, sends an interrupt signal 111 to the instruction fetch circuit 509, and sends an interrupt content signal 112 to the corresponding mode designation circuit 12. The corresponding mode specifying circuit 12 transmits to the decoder 2 a mode specifying signal 121 for specifying a decode mode corresponding to the interrupt content signal 112 sent from the interrupt control circuit 11.

The instruction decoding unit 510 is, although not particularly limited, a first instruction decoder 21 that decodes different instructions to realize a plurality of decoding modes.
A second instruction decoder 21, a third instruction decoder 23, a fourth instruction decoder 24, and the four decoders 21, 22, 2;
A mode switching circuit 25 for designating which of the decoders 3 and 24 is to be used;
Instruction code 3 according to the mode signal 250 output from
01 to which one of the four decoders is to be sent, and the decoding results 271, 272, 273, and 274 output from the four decoders 21, 22, 23, and 24, respectively. By selecting one of them, a control signal group 201 transmitted to the control unit 511 and a second selection circuit 27 that generates an interrupt return signal 202 to the instruction fetch circuit 509 are included.

FIG. 2 shows a configuration example of the corresponding mode designating circuit 12.

The corresponding mode designating circuit 12 includes, but is not limited to, a mode determining circuit 13, a mode holding circuit 14, and a mode saving circuit 15.

The mode determination circuit 13 outputs the interrupt content signal 1
The mode designated by 12 is determined, and a mode change signal 130 is output to the mode holding circuit 14.

The mode holding circuit 14 includes a register for holding the current mode. The mode saving circuit 15 can exchange data with the mode holding circuit 14. Based on the mode change signal 130,
When the mode held in the mode holding circuit 14 is changed, the mode before the change is changed to the mode save circuit 1
Saved to 5.

When the new mode is held in the mode holding circuit 14, the new mode is output by the mode designation signal 121. Further, upon receiving the interrupt return signal 202, the mode holding circuit 14 reads the mode before entering the interrupt from the mode saving circuit 15 and outputs the read mode to the mode designation signal 121. Here, the mode determination circuit 13 is constituted by a memory, the interrupt content 112 is taken in as an address, and a mode switching signal 130 is output as data corresponding to the content. Here, the mode saving circuit 15 is constituted by a necessary and sufficient rewritable memory, and can hold a plurality of modes. Therefore, even if another interrupt is received during the interrupt processing, the mode at that time can be stored and the next mode can be entered. The order in which the modes are read from the mode saving circuit 15 is the reverse of the order in which the modes are stored.

Next, the main operation will be described.

When an instruction is decoded in the instruction decoding unit 510 using the first decoder 21 (this is referred to as mode 1), an interrupt request 101 is asserted, and the interrupt request 101 is transmitted to the second decoder 22. When the mode corresponds to the mode (mode 2), the interrupt control circuit 11
Is asserted, and the interrupt content 112 is output. The instruction fetch circuit 509 saves the instruction address at that time, and then stores the address where a predetermined interrupt process is stored based on the interrupt signal 111 on the address bus 5.
And an interrupt processing instruction is read out from the ROM 4 via the data bus 6.

The corresponding mode designating circuit 12 stores the previous mode 1 in the mode saving circuit 15, and switches the new mode 2 to the mode switching circuit 25 according to the mode designating signal 121.
To instruct.

Thereafter, the instruction decoding section 510 decodes the instruction using the second decoder 22. When the interrupt processing ends, the interrupt return signal 202 is asserted. As a result, in the corresponding mode designating circuit 12, the mode before the interruption is read out from the mode saving circuit 15, and the mode designation signal 121 is changed to mode 1.
That is, the mode is returned to the decode mode immediately before the interruption. The instruction fetch circuit 509 outputs the saved address to the read address bus 5 in accordance with the interrupt return signal 202, and returns to the processing performed before the interrupt request 101 was received.

According to the above example, the following effects can be obtained.

(1) The interrupt control unit 1 determines the instruction decoding mode corresponding to the fetched interrupt,
Since the instruction decoding mode is changed based on the determination result, the instruction decoding mode can be changed by interruption. It is considered that the content of the processing is largely changed by an interrupt, and it is effective to switch the instruction decoding mode by the interrupt.

Further, since the instruction decoding mode is not changed by changing the instruction decoding mode by the mode switching instruction, a step for the switching instruction is unnecessary, and the switching instruction is prepared in all the instruction decoding modes. No need. Furthermore, since it is not a method of switching the area where instructions are stored, if there is a lot of processing using a certain instruction decoding mode, the memory capacity becomes insufficient, or conversely, if there is little processing using a certain instruction decoding mode. Does not reduce the memory usage efficiency due to excess memory capacity for the instruction decoding mode.

(2) The instruction decoding unit 510 having a plurality of instruction decoding modes defined in advance in response to an interrupt
A plurality of decoders 21 to 24; a first selection circuit 26 for distributing the instruction code fetched by the instruction fetch circuit to the plurality of decoders; and a circuit for selectively transmitting output signals of the plurality of decoders to a subsequent circuit. Second
It can be easily configured to include the selection circuit 27 and the switching circuit 25 for controlling the operations of the first selection circuit and the second selection circuit based on the specification of the corresponding mode specification circuit.

(3) A mode judging circuit 13 for judging a mode based on an interrupt, a mode holding means 14 for holding a mode instructed based on the judgment result of the mode judging circuit, and a mode holding circuit By configuring the corresponding mode designating circuit including the mode saving means 15 for saving information for returning to the mode immediately before the mode currently held by the means, the mode can be easily returned to before the decoding mode is changed. Can be achieved.

Although the invention made by the inventor has been specifically described above, the present invention is not limited to this, and it goes without saying that various modifications can be made without departing from the gist of the invention.

For example, the number of decoders constituting instruction decoding section 510 can be arbitrarily determined.

In the above description, mainly the case where the invention made by the present inventor is applied to a general-purpose microcomputer, which is the background of the application, has been described. The present invention can be applied.

The present invention can be applied on the condition that it includes at least means for decoding a fetched instruction.

[0050]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the instruction decoding mode corresponding to the fetched interrupt is determined, and the instruction decoding mode is changed based on the determination result. Therefore, the instruction decoding mode can be changed by the interrupt. You.

Further, since the instruction decoding mode is not changed by the mode switching instruction, a step for the switching instruction is unnecessary, and it is not necessary to prepare the switching instruction in all the instruction decoding modes.

Further, since the method is not a method of switching the area in which the instruction is stored, if there are many processes using a certain instruction decoding mode, the memory capacity becomes insufficient. If the number is small, the memory capacity for the instruction decoding mode is not excessive, and the use efficiency of the memory is not reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a main part in a microcomputer according to the present invention.

FIG. 2 is a block diagram showing a configuration example of a corresponding mode designating circuit included in the microcomputer.

FIG. 3 is a block diagram illustrating an overall configuration example of a computer system including the microcomputer.

FIG. 4 is a block diagram showing an overall configuration example of the microcomputer.

FIG. 5 is a block diagram illustrating a configuration example of a CPU included in the microcomputer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Interrupt control part 4 ROM 5 Address bus 6 Data bus 11 Interrupt control circuit 12 Corresponding mode designating circuit 13 Mode determining circuit 14 Mode holding circuit 15 Mode saving circuit 21 First decoder 22 First decoder 23 Second decoder 24 Fourth decoder 25 Mode switching circuit 26 First selection circuit 27 Second selection circuit 101 Interrupt request signal 111 Interrupt signal 112 Interrupt contents 121 Mode designation signal 131 Mode change signal 202 Interrupt return circuit 510 Instruction decode unit 509 Instruction fetch circuit

Claims (4)

[Claims] An instruction fetch unit for fetching an instruction code from a program memory, and a plurality of instruction decoding modes defined in advance corresponding to an interrupt, wherein an instruction fetched by the fetch unit is specified. An instruction decoding unit capable of decoding in an instruction decoding mode, and an interrupt control unit for determining an instruction decoding mode corresponding to the fetched interrupt and designating the instruction decoding unit to the mode. And a microcomputer. An instruction fetch unit for fetching an instruction code from a program memory; and a plurality of instruction decoding modes defined in advance corresponding to an interrupt. An instruction decoding unit capable of decoding in an instruction decoding mode; an interrupt control circuit for determining an instruction decoding mode corresponding to the fetched interrupt; and a corresponding decoding mode based on a determination result of the interrupt control circuit. And a corresponding mode designating circuit for designating the microcomputer. 3. The instruction decoding section selects a plurality of decoders, a first selection circuit for distributing an instruction code fetched by the instruction fetch circuit to the plurality of decoders, and an output signal of the plurality of decoders. A second selection circuit for transmitting the command to the subsequent circuit, and the first selection circuit based on the instruction decoding mode designating means.
3. The microcomputer according to claim 1, further comprising a selection circuit and a switching circuit for controlling an operation of the second selection circuit. 4. A mode determination circuit for determining a mode specified by an interrupt, and a mode holding means for holding a mode specified based on a determination result of the mode determination circuit. 4. The microcomputer according to claim 2, further comprising: a mode saving unit for saving information for returning to a mode immediately before the mode currently held in the mode holding unit.