JP2000138286A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

(57) [Problem] To improve Qsw of a memory section in an FRAM. SOLUTION: In a memory cell of an FRAM on a wafer 30, a lower electrode 34 is formed on a base film 33 laid on a field film 32 of a substrate 31,
The memory unit 35 is formed on the lower electrode 34, and the memory unit 3
5, an upper electrode 36 is formed, a shield film 37 covering the upper electrode 36 is formed on the upper electrode 36, a passivation film 38 is formed on the shield film 37, and the film 3
At 7 and 38, large tapered contact holes 41 are formed by an RIE apparatus using a high etching pressure. [Effect] Since the area of the upper electrode that is affected by etching damage by the RIE apparatus can be reduced, the Qsw of the upper electrode can be improved, and a highly stable FRAM can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technique, and more particularly to a dry etching technique for forming a contact hole in an insulating film formed on a metal pattern.
The present invention relates to a device that is effective for forming a contact hole of an upper electrode in a memory cell of an access memory.

[0002]

2. Description of the Related Art In a memory cell of an FRAM, DR is used.
On / off of the memory unit is detected by a lower electrode and an upper electrode sandwiching a ferroelectric (hereinafter, referred to as a memory unit) corresponding to an AM capacitor. Since an insulating film is deposited on the upper surface of the upper electrode, it is necessary to open a contact hole in the insulating film and electrically connect to the upper electrode. Reactive ion etching (reactive ion etching) is used as a means for opening this contact hole.
. The use of an apparatus (hereinafter referred to as RIE) is being considered.

As an example describing the RIE technology, there is “Introduction to Ultrafine Processing” published by Ohm Co., Ltd. on June 20, 1989, P62 to P79.

[0004]

SUMMARY OF THE INVENTION However, RIE
When a contact hole is opened in the insulating film above the upper electrode using an apparatus, FRA due to etching damage occurs.
The polarization amount of the memory unit at M (μC / cm; hereinafter, Qs
It is called w. The present inventors have found that there is a problem that the value of ()) becomes small.

An object of the present invention is to provide a semiconductor device manufacturing technique capable of increasing the Qsw of a memory section in an FRAM.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, in a semiconductor device in which a contact hole is formed in an insulating film formed on a metal pattern, the diameter of the bottom of the contact hole is smaller than the diameter of the opening. And

According to the above-mentioned means, since the etching damage to the upper electrode is reduced, the etching damage to the upper electrode can be suppressed to a small extent, so that the electrical characteristics of the upper electrode are prevented from lowering. be able to.

[0010]

FIG. 1 is an enlarged partial sectional view showing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a front sectional view showing an RIE apparatus used in the method of manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 3 is an enlarged partial sectional view showing a state before forming a contact hole. FIG. 4 is an enlarged partial cross-sectional view showing a state after forming a contact hole. FIG.
The following is a diagram for explaining the operation.

In the present embodiment, the method for manufacturing a semiconductor device according to the present invention is configured as a method for manufacturing an FRAM, and forms a memory cell on a semiconductor wafer (hereinafter, referred to as a wafer). Have a way. The memory cell forming method includes a lower electrode forming step, a memory section forming step, an upper electrode forming step, a shield insulating film forming step, an insulating film forming step, an upper electrode contact hole forming step, a lower electrode contact forming step, and a wiring forming step. I have.

Hereinafter, the upper electrode contact hole forming step which is a characteristic step of the present embodiment will be described in detail.
The upper electrode contact hole forming step of the memory cell forming method according to the present embodiment is performed by the RIE apparatus 10 shown in FIG. First, an RIE apparatus 10 that performs an upper electrode contact hole forming step (hereinafter, referred to as a contact hole forming method) will be described.

The RIE apparatus 10 used for the contact hole forming method is a chamber 1 in which a processing chamber 11 is formed.
2 is provided. An upper electrode plate 13 capable of blowing out an etching gas in a shower shape is suspended above the processing chamber 11. Although not shown, the upper electrode plate 13 is connected to the ground. The upper electrode plate 13 has an etching gas supply path 14.
The etching gas supply path 15 is connected to the etching gas supply path 14 via a stop valve 16.

A susceptor 17 also serving as a lower electrode plate is provided at the center of the processing chamber 11, and the susceptor 17 is configured to hold a wafer 30 as a work on its upper surface. The susceptor 17 has a built-in heater 18. The heater 18 is mounted on the wafer 3 held by the susceptor 17.
0 is configured to be heated. The susceptor 17 is connected to a high frequency power supply 19. Below the susceptor 17, a baffle plate 20 is horizontally installed, and the processing chamber 1
A wall plate 21 is provided on the inner periphery of the device 1 so as to surround the susceptor 17. An exhaust port 22 connected to a vacuum pump 24 is opened below the chamber 12, and a flow control valve 23 is provided in the exhaust port 22.

A window 25 is formed in the upper part of the chamber 12, and a sensor head 27 for light emission detection connected to a monochromator 26 is arranged outside the window 25. A capillary plate 28 is arranged at a position facing the window 25 of the wall plate 21, and the light emission detection sensor head 27 detects the light emission of the plasma P through the window 25 and the capillary plate 28. A magnet 29 is installed on the outer periphery of the upper part of the chamber 12 so as to rotate around the chamber 12. Although not shown, the chamber 12 is provided with a gate valve for loading and unloading.

Next, a method for forming a contact hole using the RIE apparatus 10 having the above configuration will be described.

The wafer 30 sent from the lithography step as a work in the contact hole forming step of the RIE apparatus 10 is formed as shown in FIG. That is, in FIG. 3, a field insulating film made of a silicon oxide film formed on the upper surface of the substrate 31 of the wafer 30 (hereinafter, referred to as a field film).
A base insulating film (hereinafter referred to as a base film) 33 made of a BPSG (borate / phosphosilicate glass) film is laid on the base film 32, and a lower electrode 34 is patterned on the base film 33. A memory section 35 is patterned on the lower electrode 34, and an upper electrode 36 is patterned on the memory section 35. A shield insulating film (referred to as a shield film) 37 is formed on the upper electrode 36 so as to cover the upper electrode 36.
7, a passivation insulating film (hereinafter, referred to as a passivation film) 38 is formed. Further, a resist film 39 is applied on the passivation film 38, and a hole pattern 40 for opening a contact hole is formed in the resist film 39 by lithography.

In the present embodiment, the ferroelectric material of the memory section 35 is PZT (a typical piezoelectric ceramic material made of a solid solution of lead zirconate and lead titanate, and is a registered trademark of Clebite Corporation in the United States. , Which is widely used as a material name).
PZT is also used as a material for the above. The passivation film 38 is formed of TEOS (tri-ethyl-ortho-silicate). The lower electrode 34 and the upper electrode 36 are formed of platinum (Pt).

The wafers 30 having the above structure are carried from the lithography step in which the hole patterns 40 are formed, and are carried one by one from the carry-in / out gate valve into the processing chamber 11 of the RIE apparatus 10. The wafer 30 carried into the processing chamber 11 is held on the susceptor 17 as shown in FIG. The processing chamber 11 is evacuated by the exhaust port 22 and the upper electrode plate 13
When the plasma is formed by the susceptor 17 and chlorine (Cl ₂ ) is blown out of the upper electrode plate 13 through the etching gas supply path 14 as an etching gas, the passivation film 38 and the shield film 37 exposed at the bottom of the hole pattern 40 are formed. Is etched to form a contact hole 41 as shown in FIG.

The wafer 30 having the contact hole 41 formed as described above is carried out of the processing chamber 11 through the carry-in / carry-out gate valve, and is carried to the next ashing step. In the ashing process, the resist film 3
When 9 is ashed, as shown in FIG.
At the bottom of the hole, the contact hole 41 exposing the upper surface of the upper electrode 36 is in a state where the wafer 30 formed in the passivation film 38 and the shield film 37 is formed.

In the present embodiment, the etching pressure at the time of the above-mentioned etching is set to 20 to 50 mTorr, which is a pressure value higher than the conventional pressure value. When the etching pressure is set to 50 mTorr, a contact hole (hereinafter, referred to as a large tapered contact hole) 41 shown in FIG. 5A is formed.
When the etching pressure is set to 20 mTorr, a contact hole (hereinafter, referred to as a medium tapered contact hole) 42 shown in FIG. 5B is formed.

An example of the etching conditions when the etching pressure is set to 50 mTorr is as follows. Platinum (Pt) upper electrode 3
6, the thickness of the PZT shield film 37 is 250 nm, the thickness of the TEOS passivation film 38 is 200 nm, and the diameter of the hole pattern 40 is 1 μm. The flow rate of chlorine gas as an etching gas is 90 seconds.
ccm (ml / min), the output of the high frequency power supply 19 is 800
W, the processing time is 90 seconds.

As shown in FIG. 1, assuming that the diameter of the hole bottom of the contact hole is S and the diameter of the opening is K, the diameter of the bottom of the large tapered contact hole 41 formed under the above etching conditions. The ratio of the diameter of the opening to the opening is 0.
491! That is, S / K was 0.491. Incidentally, K is 0.906 μm and S is 0.445.
μm.

The etching pressure for etching the insulating film using the resist film as a mask by the RIE apparatus 10 is conventionally set to a low value of about 5 to 10 mTorr. When the passivation film 38 and the shield film 37 are etched by such a low etching pressure, as shown in FIG.
Is a contact hole with a small degree of taper (hereinafter referred to as
It is called a small tapered contact hole. ) 43 was formed by the present inventors. That is, the ratio of the diameter of the hole bottom to the diameter of the opening in the contact hole 43 having a small taper is 0.7 or more. That is, S / K ≧
0.7. By the way, the hole pattern diameter is 1μ
When m, K is 0.945 μm and S is 0.703 μm.

Then, when the polarization amount of the conventional cell memory having the small tapered contact hole 43 was measured,
As shown in FIG. 6, Qsw is 14-22 μC /
cm was found by the present inventors.

FIG. 6 is a graph showing the relationship between the etching pressure and Qsw using LOCA (low oxygen concentration annealing) temperature as a parameter. In FIG. 6, the etching pressure for forming the contact hole is 10 mTo
rr, 20 mTorr and 50 mTorr are shown. The solid line shows the case where the LOCA temperature is 375 ° C, the broken line shows the case where it is 425 ° C, and the chain line shows the case where it is 475 ° C.

Here, Qsw will be described. The ferroelectric is polarized by application of a voltage, and is inverted by reversing the application direction. The polarization inversion has a hysteresis characteristic as shown in FIG. Qsw is the difference (A−B) in the amount of polarization. The larger the value of Qsw is, the more stable the memory operation is. Therefore, if the value of Qsw is small,
Memory operation becomes unstable.

In this embodiment, the etching pressure is 5
When set to 0 mTorr, FIGS. 1 and 5
A large tapered contact hole 41 shown in FIG.
Is formed. The Qsw of this large tapered contact hole 41 is examined in FIG.
m.

When the etching pressure is set to 20 mTorr, a medium tapered contact hole 42 shown in FIG. 5B is formed. The Qsw of the middle tapered contact hole 42 is examined in FIG.
２４24 μC / cm.

As is clear from the above description and FIG.
Qsw of the medium tapered contact hole 42 formed at an etching pressure of 20 mTorr is larger than that of the small tapered contact hole 43 formed at an etching pressure of 10 mTorr, and the large taper formed at an etching pressure of 50 mTorr is obtained. Qsw for the contact hole 41 of the above is that the etching pressure is 20
Medium tapered contact hole 4 formed of mTorr
It is even larger than that for 2.

The reason why the Qsw of the large tapered contact hole 41 and the medium tapered contact hole 42 is larger than that of the small tapered contact hole 43 is considered as follows. The area where damage such as plasma penetrates into the contact hole during etching is larger in the large tapered contact hole 41 and the middle tapered contact hole 4 than in the small tapered contact hole 43.
2 is smaller. For this reason, the degree of damage to the surface of the upper electrode exposed at the bottom of the contact hole is smaller in the case of the large tapered contact hole 41 and the middle tapered contact hole 42 than in the case of the small tapered contact hole 43. Is small. Further, the amount of hydrogen (H ₂ ) penetrating into the surface of the upper electrode exposed at the bottom of the contact hole after the etching is larger than that of the small tapered contact hole 43 in the large tapered contact hole 41 and the middle tapered contact hole. Hall 42
Is smaller. For these reasons, the electrical characteristics of the upper electrode are better in the case of the large tapered contact hole 41 and the middle tapered contact hole 42 than in the case of the small tapered contact hole 43.
w is better in the case of the large tapered contact hole 41 and the middle tapered contact hole 42 than in the case of the small tapered contact hole 43.

By the way, when the etching pressure is increased in the RIE apparatus, the taper of the contact hole is increased because the anisotropy, which is a characteristic of the RIE apparatus, decreases as the etching pressure increases, and the isotropic property of the plasma etching is reduced. Is considered to increase. Therefore, it is considered that if the etching pressure is set too high, the degree of taper of the contact hole becomes large and the hole bottom of the contact hole is closed.

FIG. 6 shows that Qsw depends on the LOCA temperature. At the same time, it has been demonstrated that the Qsw of the large tapered contact hole 41 and the medium tapered contact hole 42 is larger than that of the small tapered contact hole 43 even when the LOCA temperature changes.

According to the above embodiment, the following effects can be obtained.

1) By forming the diameter of the bottom of the contact hole formed in the shield film and the passivation film above the upper electrode in the FRAM smaller than the diameter of the opening, the area of the RIE device that causes etching damage to the upper electrode. , The Qsw of the upper electrode can be increased.

2) By increasing the Qsw of the upper electrode, a highly stable FRAM can be obtained.

3) When etching the contact hole by the RIE apparatus, by setting the etching pressure to be high, a contact hole having a large degree of taper can be formed, so that an increase in the manufacturing cost of the FRAM can be suppressed. An FRAM with high stability can be manufactured.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say.

For example, the ferroelectric material of the memory unit is not limited to PZT, but may be PLZT (L
a) a solid solution of a) and Y
A ferroelectric substance such as 1 (bismuth-based ferroelectric substance) may be used.

The material of the shield film is not limited to PZT, but may be a ferroelectric such as PLZT or Y1 or an insulating film such as TEOS. Further, the shield film may be omitted.

In the above description, the invention made mainly by the present inventor is based on the application field of FRA, which is the background of the invention.
Although the case where the present invention is applied to the method of forming the contact hole of the upper electrode of M has been described, the present invention is not limited to this. Can be applied to general manufacturing techniques.

[0042]

The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.

By forming the diameter of the bottom of the contact hole formed in the insulating film on the metal pattern smaller than the diameter of the opening, etching damage to the upper electrode can be suppressed small. It is possible to prevent the electrical characteristics of the electrode from being lowered.

[Brief description of the drawings]

FIG. 1 is an enlarged partial cross-sectional view showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a front sectional view showing an RIE device used in a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is an enlarged partial cross-sectional view showing a state before a contact hole is formed.

FIG. 4 is an enlarged partial cross-sectional view showing a state after a contact hole is formed.

FIGS. 5A and 5B are partially cutaway perspective views for explaining the operation, in which FIG. 5A shows a large tapered contact hole, FIG. 5B shows a medium tapered contact hole, and FIG. 5C shows a small tapered contact hole. Each is shown.

FIG. 6 is a graph showing a relationship between an etching pressure and Qsw.

FIG. 7 is a graph for explaining Qsw.

[Explanation of symbols]

10 RIE apparatus, 11 processing chamber, 12 chamber, 1
3 upper electrode plate, 14 etching gas supply path, 15 etching gas supply source, 16 stop valve, 17 susceptor,
18 heater, 19 high frequency power supply, 20 baffle plate,
21 ... wall plate, 22 ... exhaust port, 23 ... flow control valve,
24 ... vacuum pump, 25 ... window, 26 ... monochromator,
27: Sensor head for detecting light emission, 28: Capillary plate, 29: Magnet, 30: Wafer, 31: Substrate, 32: Field insulating film, 33: Base insulating film, 3
4 lower electrode, 35 memory section, 36 upper electrode, 37
... shield insulating film, 38 ... passivation insulating film, 3
9: resist film, 40: hole pattern, 41: large tapered contact hole, 42: medium tapered contact hole, 43: small tapered contact hole.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme court ゛ (Reference) H01L 21/8247 H01L 29/78 371 29/788 29/792 (72) Inventor Mitsuhiro Mori Above Kodaira-shi, Tokyo 5-20-1, Mizumotocho Inside Semiconductor Business Division, Hitachi, Ltd. (72) Inventor Naonori Wada 5-2-1, Kamimizuhonmachi, Kodaira City, Tokyo F-term, Semiconductor Business Division, Hitachi, Ltd. ) 5F001 AA17 AD33 AD90 AF05 AG10 5F004 AA06 AA12 BA08 BB13 CA02 DA04 DB03 EB01 EB03 5F033 KK17 NN32 QQ09 QQ10 QQ13 QQ15 QQ34 QQ37 RR01 RR04 RR02 TT02 WW01 WW05 5F083 FR01 GA11 MA15 JA15

Claims (9)

[Claims] 1. A semiconductor device having a contact hole formed in an insulating film formed on a metal pattern, wherein the diameter of the bottom of the contact hole is smaller than the diameter of the opening. Semiconductor device. 2. The semiconductor device according to claim 1, wherein a ratio of a hole diameter of the contact hole to an opening diameter is set to 0.4 to 0.7. 3. The semiconductor device according to claim 1, wherein the metal pattern is an upper electrode formed on a ferroelectric. 4. The semiconductor device according to claim 3, wherein said insulating film is a silicon oxide film. 5. The semiconductor device according to claim 3, wherein said insulating film is a ferroelectric film and a silicon oxide film. 6. The method for manufacturing a semiconductor device according to claim 1, wherein in the dry etching step for opening the contact hole, an etching pressure is 20 to 5 times.
A method for manufacturing a semiconductor device, wherein the method is set to 0 mTorr. 7. The method according to claim 6, wherein the etching pressure is set to 50 mTorr. 8. The method for manufacturing a semiconductor device according to claim 6, wherein chlorine is used as an etching gas. 9. The method for manufacturing a semiconductor device according to claim 6, wherein an RIE apparatus is used.