JP2000242602A - Device and method for sending size acknowledgement back - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correctly recognize a port size by generating more than one kind of size acknowledgement signal to be sent back to a master unit according to a transfer acknowledgement signal and the port size. SOLUTION: The master unit 1 is connected to a slave unit 2 of a 32-bit port, a slave unit 3 of a 16-bit port, and slave units 4 to 19 of an 8-bit port through an address bus B1 and a data bus B2. Then the master unit 1 sends a transfer acknowledgement signal S3 for bus cycles and size acknowledgement signals DSACK1 and DSACK0 showing pieces S1 and S2 of port size information back to the respective slave units 2 to 19 by an acknowledgement generation part 22. Consequently, the pieces S1 and S2 of port size information can correctly be recognized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an apparatus configuration in which the number of slave units connected to the only bus controlled by the master unit is arbitrary and the port sizes, which are the bus widths of the slave units, are different. A size acknowledgment returning device that correctly recognizes a port size without causing a load capacitance difference between size acknowledgment signals that recognize a port size even when the load capacity of each signal on the bus changes depending on the number of mounted devices; Regarding the method of returning the size acknowledgment.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram for explaining a conventional size acknowledgment returning method, and FIG. 5 is a timing chart for explaining the operation of the size acknowledgment returning method of FIG. Referring to FIG. 4, in the conventional size acknowledgment returning method, a 32-bit CPU P23 that supports a dynamic bus sizing function and misalignment detects a port size according to an encoding result of 2-bit size acknowledge signals DSACK1 ^* and DSACK0 ^*. It is used as a processor of the master unit P1. Further, the size acknowledge signal DS in a device in which the number of mounted slave units connected to the only bus controlled by the CPU P23 is arbitrary and the port size which is the bus width of the slave unit is different.
When connecting ACK1 ^* and DSACK0 ^* , as shown in FIG. 4, each slave unit P2,.
The required size acknowledge signal DSACK1 ^* and the size acknowledge signal DSA
One of CK0 ^* , DSACK1 ^* , DSAC
K0 ^* was generated by each of the slave units P2,..., P19 and returned to the master unit P1.

[0003]

However, the prior art has the following problems. The first problem is
When the number of mounted 8-bit port slave units P4,..., P19 increases, if access is performed to the 32-bit port slave unit P2, the slave unit P2 is recognized as a 16-bit port. Misalignment is a malfunction. The reason is that an 8-bit port slave unit P
4, ..., compared to the load capacity of the size acknowledge signal DSACK1 ^* If the mounting speed is increased the P19, dull change in size acknowledge signal DSACK0 ^* by the load capacitance of the size acknowledge signal DSACK0 ^* increases, the size acknowledge The phase difference between the signal DSACK1 ^* and the size acknowledge signal DSACK0 ^* increases, and in this state, as shown in FIG.
3 is the size acknowledge signal DSACK1 ^* , DSAC
This is because a 16-bit port is erroneously recognized when sampling K0 ^* .

The second problem is that the master unit P1
In order to avoid misrecognition of the port size in
The point is that the time required for one bus cycle becomes longer. The reason is that in the master unit P1, the size acknowledge signal DSACK1 ^* and the size acknowledge signal DACK
SACK0 ^* Maximum generate a phase difference more DSACK mask signal, DSACK mask signal size acknowledge signal as a trigger of the bus cycle ending after the maximum phase difference from being asserted DSACK1 ^*, is necessary to enter the DSACK0 ^* to CPUP23 Because there is.

A third problem is that the slave unit
In order to avoid misrecognition of the port size in
Slave unit with 6-bit port and 8-bit port
Knit DSACK^*Large return circuit (not shown)
It is a point. The reason is that the size acknowledge signal D
SACK1^*And size acknowledge signal DSACK0 ^*
DSAC not required to equalize the load capacity of
K^*For example, in a slave unit with a 16-bit port
Size acknowledge signal DSACK0^*, 8-bit port
In the slave units P4,.
Knowledge signal DSACK1^*Output inactivity to
This is because it is necessary to provide a pseudo circuit.

The present invention has been made in view of such a problem, and an object of the present invention is to provide any number of slave units connected to the only bus controlled by the master unit, and In a device configuration with a different port size, which is the bus width, even if the load capacity of each signal on the bus changes depending on the number of mounted slave units, the load capacity difference between the size acknowledgment signals for recognizing the port size may vary. It is an object of the present invention to provide a size acknowledgment returning device and a size acknowledgment returning method for correctly recognizing a port size without causing a port size.

[0007]

According to the gist of the present invention, there is provided a port having an arbitrary number of slave units connected to a single bus controlled by a master unit and having a bus width of the slave unit. Even if the load capacity of each signal on the bus changes depending on the number of slave units mounted in a device configuration having a different size, even if the load capacity of each signal on the bus changes, the load capacity between at least one or more size acknowledge signals for recognizing the port size. What is claimed is: 1. A size acknowledgment returning device for correctly recognizing a port size without causing a difference, wherein an address of a bus access from the master unit to the slave unit is decoded to detect a bit number of a bit port of the slave unit. An interface for generating the port size information corresponding to the detected number of bits. And a transfer acknowledge signal input from any of the slave units and the at least one type of size acknowledge signal returned to the master unit based on the port size input from the address decode unit. There is provided a size acknowledgment returning device comprising an acknowledgment returning unit having an acknowledgment generating unit for generating the acknowledgment. According to another aspect of the present invention, when the master unit accesses the slave unit, the address decoding unit detects that the access is to the slave unit and the port size 2. The size acknowledgment sending device according to claim 1, wherein the information on the port size of the slave unit is transmitted to the acknowledgment generating unit based on a predetermined truth table for the acknowledgment. According to another aspect of the present invention, when the slave unit sends the transfer acknowledgment signal to the acknowledgment generation unit, the acknowledgment generation unit converts the transfer acknowledgment signal to the at least one or more size acknowledgment signals having a predetermined logical value. 2. The apparatus according to claim 1, wherein the at least one type of size acknowledge signal is generated based on the port size information and the transfer acknowledge signal based on the port size information and the transfer acknowledge signal is returned to the master unit. 3. It exists in the size acknowledge return device. The gist of claim 4 of the present invention is that the acknowledgment returning means integrates and separates the function of generating the at least one type of size acknowledgment signal into one and increases or decreases the number of mounted slave units. 4. The apparatus according to claim 2, wherein, even in such a case, a correct port size of the slave unit is detected by preventing a load capacitance difference between the at least one type of size acknowledge signal. The size acknowledgment return device described above is present. The gist of claim 5 of the present invention is that the acknowledgment returning means integrates and separates the function of generating the at least one type of size acknowledgment signal into one and increases or decreases the number of mounted slave units. 4. The apparatus according to claim 2, wherein even in such a case, a change in a phase difference between the at least one type of size acknowledgment signal is prevented and a correct port size for the slave unit is detected. In the size acknowledgment returning device described in (1). Claim 6 of the present invention
The gist described in is that the number of mounted slave units connected to the only bus controlled by the master unit is arbitrary, and for device configurations with different port sizes that are the bus width of the slave units, Even if the load capacity of each signal on the bus changes,
A size acknowledgment returning method for correctly recognizing a port size without causing a load capacitance difference between at least one or more types of size acknowledgment signals for recognizing a port size, wherein an address of a bus access from the master unit to the slave unit is provided. An address decoding step of detecting the number of bits of the bit port of the slave unit and generating information of the port size corresponding to the detected number of bits, and a transfer acknowledge input from any of the slave units. An acknowledge generating step of generating the at least one type of size acknowledge signal to be returned to the master unit based on a signal and the port size input from the address decoding step. Lies in the size acknowledge back method characterized by having a. Further, the gist of the present invention is that, when the master unit accesses the slave unit, it detects that the address decoding step is an access to the slave unit, and detects the port size. 7. The method according to claim 6, further comprising the step of transmitting information on the port size of the slave unit to the acknowledgment generation step based on a predetermined truth table for the size acknowledgment. The gist of claim 8 of the present invention is that when the slave unit sends the transfer acknowledge signal to the acknowledge generating step, the acknowledge generating step has a predetermined logic value of at least one of the predetermined acknowledged values.
A step of generating the at least one type of size acknowledge signal using the port size information and the transfer acknowledge signal based on at least one type of size acknowledge signal and returning the generated size acknowledge signal to the master unit. 6. The size acknowledge return method described in No. 6. The gist of claim 9 of the present invention is:
The acknowledgment returning step collects and separates the function of generating the at least one or more types of size acknowledgment signals into one, and the at least one or more types of size acknowledgments even when the number of mounted slave units increases or decreases. 9. The method according to claim 7, further comprising a step of detecting a correct port size of the slave unit while preventing a load capacity difference between signals. The gist of claim 10 of the present invention is that the acknowledgment returning step includes:
The function of generating the at least one type of size acknowledge signal is integrated and separated into one, and the phase difference between the at least one type of size acknowledge signal even when the number of mounted slave units increases or decreases. 9. The method according to claim 7, further comprising a step of detecting a correct port size of the slave unit while preventing a change.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The features of each embodiment described below are as follows.
2-bit data transfer / size acknowledge signal (hereinafter, size acknowledge signal DSACK1 ^* , DSACK0)
^* ) A 32-bit CPU supporting the dynamic bus sizing function and misalignment based on the above is used as the processor of the master unit, and the number of slave units connected to the only bus controlled by the CPU is arbitrary, and In an apparatus configuration having different port sizes (bus widths), even if the load capacity of each signal on the bus changes depending on the number of mounted slave units, a size acknowledge signal DSACK1 ^* for recognizing the port size, and a size acknowledge signal. DS
The point is that it is possible to correctly recognize the port size by preventing a load capacity difference from occurring between ACK0 ^* . Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a functional block diagram for explaining a first embodiment of a size acknowledgment returning apparatus and a size acknowledgment returning method according to the present invention. Referring to FIG. 1, the size acknowledgment returning device includes one master unit 1, one 32-bit port slave unit 2, one 16-bit port slave unit 3, and an 8-bit port slave unit. This device can be arbitrarily mounted from at least 1 to up to 16 according to the required processing amount. FIG. 1 shows an example of a configuration in which 16 8-bit port slave units are mounted, as an example.

In FIG. 1, a master unit 1 has an address bus B1 (32, 16, 8 bits) and a data bus B1.
2, the slave unit 2 having a 32-bit port, the slave unit 3 having a 16-bit port, and the slave units 4,... Each of the slave units 2,.
The address bus B1 to which 19 is connected is connected. Acknowledgment generation unit 22 returns a transfer acknowledge signal S3 of the bus cycle from master unit 1 to each of slave units 2,..., 19 and size acknowledge signals DSACK1 ^* and DSACK0 ^* indicating port size information S1 and S2. Also, each slave unit 2,
, 19 are connected to the acknowledgment generation unit 22 by a wired OR connection with the transfer acknowledge signal S3 for the bus cycle from the master unit 1.

A CPU which is a 32-bit CPU 23 mounted on the master unit 1 and operating as a processor of the apparatus.
23 is a size acknowledge signal DSACK1 shown in Table 1.
^* , DSACK0 ^* encoding result (H: logical value H,
L: Supports a dynamic bus sizing function and misalignment according to a logical value L).

[0012]

[Table 1]

The acknowledgment returning means 20 decodes the address of the bus access from the master unit 1 to the slave unit, detects how many bit ports the slave unit has, and responds to the port size information S1 and S2 shown in Table 2 below. Port size information S according to the truth table
, S2, and a transfer acknowledge signal S3 input from any of the slave units 2,.
Acknowledge signal DS returned to master unit 1 from port size information S1 and S2 input from
An acknowledgment generation unit 22 that generates ACK1 ^* and DSACK0 ^* is provided.

FIG. 2 is a timing chart for explaining a bus cycle from the master unit 1 of FIG. 1 to the slave unit 2 having a 32-bit port. Next, FIGS.
The operation of the first embodiment will be described with reference to FIG. In FIG. 1, when the CPU 23 of the master unit 1 accesses the slave unit 2 of the 32-bit port, the address decoding unit 21 detects that the access has been made to the slave unit 2 of the 32-bit port. Based on a truth table (H: logical value H, L: logical value L) for the port size information S1 and S2 shown in Table 2, an acknowledgment is generated by using the port size information S1 and S2. To the unit 22.

[0015]

[Table 2]

The slave unit 2 having a 32-bit port sends a transfer acknowledgment signal S 3 to the acknowledgment generator 22. In response to this, the acknowledgment generation unit 22
Is the size acknowledge signal DSACK shown in Table 3.
1 ^* , DSACK0 ^{*, based} on a truth table (H: logical value H, L: logical value L, *: undefined), using the port size information S1, S2 and the transfer acknowledge signal S3, the size acknowledge signal DSACK1 ^* , DSACK
0 ^* is generated and returned to the CPU 23.

[0017]

[Table 3]

As described above, the size acknowledge signal DSA
CK1^*, DSACK0^*Function to generate
Separation increases or decreases the number of slave units mounted
Size acknowledge signal DSACK
1^*, DSACK0^*So that there is no load capacity difference between them.
it can. At the same time, the size acknowledge signal DSACK1 ^*
-Size acknowledge signal DSACK0^*Phase difference between
Since there is no change, correct port size information S
1, S2 can be detected.

The operation of the first embodiment will be described in more detail with reference to FIGS. CPU 2 of master unit 1
3 along with the address strobe signal AS ^* synchronized with the clock signal CPUCLK.
Indicates the address of the slave unit 2 of the 32-bit port, the address decoding unit 21 detects that the access is to the 32-bit port in response to the address, and the port size information S1 and S2 indicate that the 32-bit port is # 0. Is output to the acknowledgment generation unit 22.

On the other hand, the slave unit 2 of the 32-bit port detects access to its own unit, and performs data output or data write according to the read / write signal R / W ^*.
The transfer acknowledgment signal S3 indicating that valid data has been output is output to the acknowledgment generation unit 22, the data on the data bus B2 is fetched into the unit during a write cycle, and the transfer acknowledgment signal S3 indicating that writing has been completed. Is output to the acknowledgment generation unit 22.

In response, the acknowledgment generation unit 22
The size acknowledge signals DSACK1 ^* , D shown in Table 3
SACK0 based on truth table for ^*, port size information S1, S2 and transfer acknowledge signal S3 size acknowledge signal using the DSACK1 ^*, DSA
CK0 ^* is generated and returned to master unit 1.

In response, the CPU 2 of the master unit 1
3 is a size acknowledge signal DSACK1 ^* , DSA
The level of CK0 ^* is sampled, and if the size acknowledge signals DSACK1 ^* and DSACK0 ^* are asserted, the data on the data bus B2 is latched during the read cycle, the address strobe is negated, and the bus cycle ends. Further, the address strobe is negated in the write cycle and the bus cycle is completed.

At this time, when detecting the negation of the address strobe, the slave unit 2 of the 32-bit port negates the transfer acknowledge signal S3. In response to this, the acknowledgment generation unit 22 transmits the transfer acknowledgment signal S
3, the size acknowledge signal DSACK1 ^* and the size acknowledge signal DSACK0
Negate ^* .

Similarly, when a bus cycle to the slave unit 3 of the 16-bit port occurs, the port size information S1 and S2 output from the address decoding unit 21 to the acknowledgment generation unit 22 indicate the 16-bit port.
Indicates that the size acknowledge signals DSACK1 ^* and DSACK0 ^* returned to the master unit 1 are 1
Indicates a 6-bit port.

When a bus cycle to any of the slave units 4,..., 19 of the 8-bit port occurs, the port size information S1 and S2 output from the address decoding unit 21 to the acknowledgment generation unit 22 are stored in the 8-bit port. Indicates that the master unit 1
Acknowledge signal DSACK1 ^* , D returned to
SACK0 ^* indicates an 8-bit port.

The present embodiment is configured as described above, and has the following effects. First, a 2-bit size acknowledge signal DSACK1 ^* , DSACK0
^* , A 32-bit CPU 23 that supports the dynamic bus sizing function and misalignment is used as a processor of the master unit 1,
The number of mounted slave units having specific port size information S1 and S2 is variable in a device in which the number of mounted slave units connected to the only bus controlled by the device is different and the port size information S1 and S2 of the slave units are different. The size acknowledge signal DSA
Port size information S is obtained by CK1 ^* and DSACK0 ^*.
1, S2 can be correctly detected. The reason is that the size acknowledge signals DSACK1 ^* , DSAC
By integrating the function of generating K0 ^* into one, the number of mounted slave units and the size acknowledge signal DS
The causal relationship between the load capacity difference between ACK1 ^* and DSACK0 ^* disappears, and the size acknowledge signal DSACK1 ^*
This is because the phase difference between the size acknowledge signals DSACK0 ^* does not depend on the number of mounted slave units.

Second, the acknowledge return circuit (not shown) of the slave unit can be used as a common circuit even in the slave units having different port size information S1 and S2.
In, the circuit scale can be reduced. The reason is that the function of generating the size acknowledge signals DSACK1 ^* and DSACK0 ^* for notifying the master unit 1 of the completion of the data transfer and the port size information S1 and S2 is integrated and separated into one, so that the slave unit has the port size information. This is because it is sufficient to return only the transfer acknowledge signal S3 regardless of S1 and S2.

Third, a multiprocessor for load distribution
In the case of a Sessa configuration (multiple master units)
Even the size acknowledge signal DSACK1^*, DSAC
K0 ^*The configuration of the acknowledge return means is a single process
It may be the same as when the configuration is made. The reason is that multiprocessor
Address bus B1 / data
Bus B2 and size acknowledge signal DSACK
1^*, DSACK0^*Use multiple slaves
Executed from any processor in the unit
Access is the only slave unit.

(Second Embodiment) FIG. 3 is a functional block diagram for explaining a size acknowledgment returning apparatus and a size acknowledgment returning method according to a second embodiment of the present invention. Referring to FIG. 3, in the second embodiment, a transfer acknowledge signal S103 dedicated to a 32-bit port output from each of the slave units 2,..., 19 to the acknowledge generation unit 22 instead of the address decoding unit 21 of the acknowledge return unit 20 , A dedicated line for a transfer acknowledge signal S203 dedicated to a 16-bit port, and a dedicated line for a transfer acknowledge signal S303 dedicated to an 8-bit port.

Address decoding unit 2 shown in the first embodiment
1 is a slave unit having different port size information S1 and S2.
The address given to the unit is set randomly
The port size information S1 and S2
Decoding when the addresses between
There is a problem that the scale of the circuit is increased. So the second
In the embodiment, the size acknowledgment of the acknowledgment generation unit 22 is set.
Edge signal DSACK1 ^*, DSACK0^*To the condition for generating
The truth table (H: logical value H, L: logical value L) of Table 4 is shown.
Dedicated transfer acknowledge signals S103, S203, S3
03, the address decoding unit 21 is disabled.
I need it. As a result, the second embodiment is different from the first embodiment.
In addition to the effects described in the above, the acknowledgment returning means 20
There is a new effect that the circuit scale can be reduced.

[0031]

[Table 4]

It should be noted that the present invention is not limited to the above embodiments, and each embodiment can be appropriately modified within the scope of the technical idea of the present invention. Further, the number, position, shape, and the like of the constituent members are not limited to the above-described embodiment,
The number, position, shape, and the like suitable for carrying out the present invention can be obtained. In each drawing, the same components are denoted by the same reference numerals.

[0033]

Since the present invention is configured as described above, the following effects can be obtained. First, a 32-bit CPU supporting a dynamic bus sizing function and misalignment is used as a processor of a master unit according to a 2-bit data transfer and size acknowledge signal, and a slave unit connected to the only bus controlled by the CPU is used. For devices with arbitrary number of mounts and different port sizes, which are bus widths of slave units, correct detection of the port size by size acknowledge signal even when the number of mounts of slave units with a specific port size varies. Is possible. The reason is that by consolidating the function to generate the size acknowledge signal into one, there is no causal relationship between the number of mounted slave units and the difference in the load capacitance of the size acknowledge signal, and the phase difference between the size acknowledge signals is This is because it does not depend on the number of mounted units. Secondly, the acknowledge return circuit (not shown) of the slave unit can be used as a common circuit even for slave units having different port sizes, and the circuit scale can be reduced for a 32-bit port slave unit. The reason is that the function to generate the size acknowledge signal that notifies the master unit of the data transfer completion and the port size is integrated and separated into one, so that the slave unit can return only the transfer acknowledge signal regardless of the port size. It is good. Third, even when a multiprocessor configuration (a plurality of master units) for load distribution is adopted, the configuration of the acknowledge return means for the size acknowledge signal may be the same as that of the single processor configuration. The reason is,
Even if a multiprocessor configuration is used, since the common address bus / data bus and size acknowledge signal are used, the access executed from any one of the plurality of slave units is the only slave unit. .

[Brief description of the drawings]

FIG. 1 is a functional block diagram illustrating a first embodiment of a size acknowledgment returning device and a size acknowledgment returning method according to the present invention.

FIG. 2 is a timing chart for explaining a bus cycle from a master unit of FIG. 1 to a slave unit of a 32-bit port.

FIG. 3 is a functional block diagram illustrating a second embodiment of a size acknowledgment returning apparatus and a size acknowledgment returning method according to the present invention;

FIG. 4 is a block diagram for explaining a conventional size acknowledgment returning method.

FIG. 5 is a timing chart for explaining the operation of the size acknowledgment returning method of FIG. 4;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Master unit 2 ... 32-bit port slave unit 3 ... 16-bit port slave unit 4, ..., 19 ... 8-bit port slave unit 20 ... Acknowledge return means 21 ... Address decode part 22 ... Acknowledge generation part 23 ... CPU AS ^* : Address strobe signal B1: Address bus B2: Data bus CPUCLK: Clock signal DSACK1 ^* , DSACK0 ^* : Size acknowledge signal R / W ^* : Read / write signal P1: Master unit P2: 32-bit port slave unit P3 ... 16-bit port slave unit P4 to P19 ... 8-bit port slave unit P23 ... CPU PB1 ... address bus PB2 ... data bus S1, S2 ... port size information S103 ... 32-bit port Data Only the transfer acknowledge signal S203 ... 16-bit port on the transfer acknowledge signal S3 ... transfer acknowledge signal S303 ... 8 bit port on the transfer acknowledge signal

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[Procedure amendment]

[Submission Date] January 26, 2000 (2000.1.2
6)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction contents]

[0007]

The gist of the invention described in claim 1 is that the number of mounted slave units connected to the only bus controlled by the master unit is arbitrary, and the port size is the bus width of the slave unit. However, even if the load capacity of each signal on the bus changes depending on the number of slave units mounted for different device configurations, a load capacity difference occurs between the two types of size acknowledge signals that recognize the port size. A size acknowledgment returning device for correctly recognizing a port size without causing the slave unit to decode a bus access address from the master unit to the slave unit to detect the number of bits of the bit port of the slave unit. Address decoding unit for generating information on the port size corresponding to the number of bits , It generates the two kinds of cyclic <br/> Zuakunorijji signal returning to said master unit based on the port size to be inputted from the transfer acknowledge signal and said address decoding unit is input from any of said slave unit Acknowledgment returning means having an acknowledgment generating unit for changing the size of the acknowledgment
The function to generate the signal
The port size signal that indicates the transfer completion output from the unit
A size acknowledgment returning apparatus characterized by having means for converting one signal regardless of the size of the signal . Further, the gist of the invention according to claim 2 is that, when the master unit accesses the slave unit, the address decoding unit detects that the access is to the slave unit and the port size. sending an information port size of the slave unit to the acknowledge generating unit based on a predetermined truth table for
With one function of generating the size acknowledge signal,
Transfer completed by the slave unit
The signal that indicates is one signal regardless of the port size
Be configured resides in size acknowledge back device according to claim 1, wherein the. The gist of the invention according to claim 3 is that when the slave unit sends the transfer acknowledgment signal to the acknowledgment generation unit, the acknowledgment generation unit sets the two types of predetermined logic values.
The port size information and the transfer acknowledge signal based on the size acknowledge signal of the two types.
By generating a size acknowledgment signal of a kind and returning it to the master unit, the size acknowledgment signal is
The functions to be generated are integrated into one unit and the slave unit
Outputs the signal indicating transfer completion regardless of the port size.
2. The size acknowledgment returning device according to claim 1, wherein the size acknowledgment is returned as one signal .
The gist of the invention described in claim 4 is that the acknowledgment returning means integrates and separates the function of generating the two types of size acknowledgment signals into one to increase or decrease the number of mounted slave units. Even the above
The size acknowledgment signal is generated by detecting a correct port size applied to the slave unit while preventing a load capacity difference between the two types of size acknowledgment signals .
Functions are integrated into one unit and output by the slave unit.
One signal indicating transfer completion regardless of the port size
Claim 2, characterized in that it is configured so as to
Or the size acknowledgment returning device described in 3. The gist of the invention described in claim 5 is that the acknowledgment returning means integrates and separates the function of generating the two types of size acknowledgment signals into one to increase or decrease the number of mounted slave units. Even by detecting the correct port size applied to the slave unit by preventing a change in the phase difference between the two types of size acknowledge signals , the size acknowledge signal
The functions to be generated are integrated into one unit and the slave unit
Outputs the signal indicating transfer completion regardless of the port size.
4. The size acknowledgment returning device according to claim 2, wherein the signal is configured to be one signal . The gist of the invention described in claim 6 is that the number of mounted slave units connected to the only bus controlled by the master unit is arbitrary and the slave unit has a different port size as a bus width. Even if the load capacity of each signal on the bus changes according to the number of mounted slave units, the port size is recognized.
A size acknowledgment returning method for correctly recognizing a port size without causing a load capacitance difference between two types of size acknowledgment signals, comprising decoding a bus access address from the master unit to the slave unit, An address decoding step of detecting the number of bits of the bit port and generating information of the port size corresponding to the detected number of bits, and a transfer acknowledge signal input from any of the slave units and the address decoding step. and acknowledge returning step that includes a acknowledge generating process of generating the two sizes acknowledge signal to be returned to said master unit based on the port size to be entered, the size acknowledge signal
The functions to be generated are integrated into one unit and the slave unit
Outputs the signal indicating transfer completion regardless of the port size.
A size acknowledgment returning method characterized by having a step of making one signal . Further, the gist of the invention according to claim 7 is that, when the master unit accesses the slave unit, it is detected that the address decoding step is an access to the slave unit, and the port size is detected. based on a predetermined truth table for by transmitting the information of the port size of the slave unit to the acknowledge generating step,
The function of generating the size acknowledge signal is integrated into one.
Indicates that transfer is complete and the slave unit outputs transfer completion
The method according to claim 6, further comprising the step of setting a signal to be one signal regardless of the port size . The gist of the invention according to claim 8 is that when the slave unit sends the transfer acknowledgment signal to the acknowledgment generation step, the acknowledgment generation step is based on the two types of size acknowledgment signals having a predetermined logical value. The two types of size acknowledge signals are generated using the port size information and the transfer acknowledge signal, and are returned to the master unit.
To generate the size acknowledge signal.
Functions are integrated into one unit and output by the slave unit.
The signal indicating transfer completion is one signal regardless of the port size.
7. The method according to claim 6, further comprising the step of: Further, the gist of the invention according to claim 9, wherein the acknowledgment returning step, the 2
One function to generate different size acknowledge signals
By collecting and separating, even if the number of mounted slave units increases or decreases, by detecting a correct port size applied to the slave unit by preventing a load capacity difference between the two types of size acknowledge signals ,
Function to generate size acknowledge signal is integrated into one
Release The signal indicating transfer completion output by the slave unit.
The method according to claim 7 or 8, further comprising a step of setting the signal to one signal regardless of the port size . Further, the gist of the invention according to claim 10, wherein the acknowledge back step, aggregated content into one function for generating the two kinds of <br/> size acknowledge signal
By separating, even if the number of mounted slave units increases or decreases, by preventing a change in the phase difference between the two types of size acknowledgment signals and by detecting the correct port size applied to the slave unit, Rhinoceros
The function to generate the Zack acknowledge signal is integrated and separated into one.
A signal indicating the completion of transfer output from the slave unit
The method according to claim 7 or 8, further comprising a step of setting one signal regardless of the port size .

Claims (10)

[Claims] 1. A device configuration in which the number of slave units connected to the only bus controlled by the master unit is arbitrary and the port size, which is the bus width of the slave units, is different from each other. Even if the load capacity of each of the above signals changes, a size acknowledgment returning device for correctly recognizing a port size without causing a load capacity difference between at least one or more types of size acknowledgment signals for recognizing a port size. And decoding a bus access address from the master unit to the slave unit to detect a bit number of a bit port of the slave unit and generate information of the port size corresponding to the detected bit number. An address decoding unit and any of the slave units And an acknowledgment generation unit that generates the at least one type of size acknowledgment signal to be sent back to the master unit based on the transfer acknowledgment signal input from the controller and the port size input from the address decoding unit. A size acknowledge return device comprising return means. 2. When the master unit accesses the slave unit, the address decoding unit detects that the slave unit has been accessed, and generates a predetermined truth table for the port size. 2. The size acknowledgment returning device according to claim 1, wherein information on the port size of the slave unit is transmitted to the acknowledgment generating unit based on the received information. 3. When the slave unit sends the transfer acknowledge signal to the acknowledge generating unit,
The acknowledgment generation unit generates the at least one or more size acknowledgment signals using the port size information and the transfer acknowledgment signal based on the at least one or more size acknowledgment signals having a predetermined logical value, and sends the generated acknowledgment signal to the master unit. The size acknowledgment returning device according to claim 1, wherein the device is configured to return the size acknowledgment. 4. The acknowledgment returning means integrates and separates the function of generating the at least one type of size acknowledgment signal into one, and the at least one acknowledgment signal is provided even when the number of mounted slave units is increased or decreased. 4. The size acknowledgment sending device according to claim 2, wherein a correct port size of the slave unit is detected by preventing a difference in load capacity between the size acknowledgment signals of more than one type. 5. The acknowledgment returning means integrates and separates the function of generating the at least one type of size acknowledgment signal into one, and the at least one acknowledgment signal is provided even when the number of mounted slave units increases or decreases. 4. The size acknowledgment returning apparatus according to claim 2, wherein a correct port size for the slave unit is detected by preventing a change in a phase difference between more than one type of size acknowledgment signals. 6. In a device configuration in which the number of mounted slave units connected to the only bus controlled by the master unit is different and the port size, which is the bus width of the slave units, is different, the bus is determined by the number of mounted slave units. A size acknowledgment returning method for correctly recognizing a port size without causing a load capacity difference between at least one or more size acknowledgment signals for recognizing a port size even when the load capacity of each of the above signals changes. And decoding a bus access address from the master unit to the slave unit to detect a bit number of a bit port of the slave unit and generate information of the port size corresponding to the detected bit number. An address decoding step; An acknowledgment generating step of generating the at least one or more types of size acknowledgment signals to be returned to the master unit based on the transfer acknowledgment signal input therefrom and the port size input from the address decoding step. A size acknowledgment returning method, comprising an acknowledgment returning step. 7. When the master unit accesses the slave unit, it detects that the address decoding step is an access to the slave unit, and generates a predetermined truth table for the port size. 7. The method according to claim 6, further comprising the step of transmitting information on the port size of the slave unit to the acknowledgment generating step based on the information. 8. When the slave unit sends the transfer acknowledgment signal to the acknowledgment generation step, the acknowledgment generation step determines the port size information and the port size information based on the at least one type of size acknowledgment signal having a predetermined logical value. 7. The method according to claim 6, further comprising the step of generating the at least one type of size acknowledge signal using a transfer acknowledge signal and returning the generated size acknowledge signal to the master unit. 9. The acknowledgment returning step collects and separates the function of generating the at least one or more types of size acknowledgment signals into one, and performs the at least one acknowledgment even if the number of mounted slave units increases or decreases. 9. The method according to claim 7, further comprising a step of detecting a correct port size of the slave unit by preventing a load capacity difference between the size acknowledgment signals of more than two kinds. 10. The acknowledgment returning step collects and separates the function of generating the at least one or more types of size acknowledgment signals into one, and performs the at least one acknowledgment even if the number of mounted slave units increases or decreases. 8. The method according to claim 7, further comprising a step of detecting a correct port size of the slave unit by preventing a change in a phase difference between two or more types of size acknowledge signals.
Or the method of returning the size acknowledgment described in 8.