JP2000250492A - Driving method and driving device for liquid crystal display device - Google Patents

Abstract

(57) [Abstract] (with correction) [PROBLEMS] To reduce display unevenness due to distortion of an applied voltage waveform at the time of high gradation display in a simple matrix liquid crystal display device which performs simultaneous selection driving of a plurality of lines by an orthogonal function. I do. A first frame and a second frame divided into two are continuous, and a selection period T2, T1, T0 in each frame is provided.
Is set to 4: 2: 1. In each selection period, 8 gradation display of 7/7 to 0/7 is performed by combining on and off data. Since the number of change points is small, the waveform distortion of the applied voltage is small, and as a result, the display unevenness is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a liquid crystal display device suitable for driving a liquid crystal display device which responds at a high speed, and a liquid crystal display device using the driving method. In particular, the present invention relates to a driving method and a driving device suitable for a liquid crystal display device driven by a multiple line simultaneous selection method.

[0002]

2. Description of the Related Art A multiple line simultaneous selection method (multi-line addressing method: MLA method) has been proposed to drive an STN liquid crystal element at higher speed. The multiple line simultaneous selection method is a method in which a plurality of scan electrodes (row electrodes) are collectively selected and driven. In the multiple line simultaneous selection method, a predetermined voltage pulse train is applied to each of the simultaneously driven row electrodes in order to independently control a column display pattern supplied to the data electrodes (column electrodes).

A voltage pulse voltage group (selection pulse group) applied to each row electrode can be represented by a matrix of L rows and K columns. Hereinafter, this matrix is referred to as a selection matrix (A). L is the number of simultaneous selections. The voltage pulse voltage group is represented as a vector group orthogonal to each other. Therefore, a matrix including those vectors as elements is an orthogonal matrix. Each row vector in each matrix is orthogonal to each other.

[0004] In the orthogonal matrix, each row corresponds to each line of the liquid crystal display device. For example, the element of the first row of the selection matrix (A) is applied to the first line of the L selection lines. That is, the selection pulse is applied to the first row electrode in the order of the first column element and the second column element.

FIGS. 12 to 14 are explanatory views showing how to determine the sequence of the voltage waveform applied to the column electrode. Here, a Hadamard matrix of 8 rows and 2 columns shown in FIG. 12 is used as a pixel, and a Hadamard matrix of 4 rows and 4 columns shown in FIG. In the selection matrix shown in FIG. 13, "1" means a positive selection pulse, and "-1" means a negative selection pulse. Hereinafter, the four lines that are simultaneously selected are referred to as a subgroup. FIG.
In SG2, SG1 indicates subgroup 1 and SG2 indicates subgroup 2.

It is assumed that display data to be displayed on the column electrodes 1 and 2 is as shown in FIG.
In FIG. 12, a white circle indicates that the light is on, and a black circle indicates that the light is off. Then, the column display patterns of subgroup 1 and subgroup 2 are represented by a vector (d) as shown in FIG. In the vector (d) shown in FIG.
“−1” corresponds to the ON display, and “1” corresponds to the OFF display.

The voltage levels to be sequentially applied to the subgroups 1 and 2 of the column electrodes 1 and 2 are as shown in a vector (v) shown in FIG. This vector corresponds to a product obtained by multiplying a column display pattern (image display pattern) and a corresponding row selection pattern for each bit, and taking the sum of the results.

FIG. 15 shows the vector (v) shown in FIG.
5 is a timing chart showing voltage waveforms of column electrodes 1 and 2 corresponding to FIG. In FIG. 15, the vertical axis indicates the voltage applied to the column electrode, and the horizontal axis indicates time. sg1 and sg2 are the selection periods of subgroup 1 and subgroup 2, respectively.
sf1 to sf4 are subframes 1 to 4
Is shown. When a selection matrix of L rows and 4 columns is used, 4 subframe periods from subframe 1 to subframe 4 constitute one frame.

Such a method of simultaneously selecting a plurality of lines suppresses the frame response of the liquid crystal, resulting in a high-speed response (r + d
<200 ms: r is the rise time of liquid crystal molecules, d is the fall time) and high contrast (40: 1 or more) can be achieved. That is, in a simple matrix display device such as an STN, it is possible to provide a high-quality image which has been difficult in the conventional drive display.

Next, the PW method for the multiple line simultaneous selection method is used.
A driving method in a case where a gradation method based on the M (pulse width modulation) method is applied will be described. FIG. 16 is an explanatory diagram showing an example in which seven gradations are displayed in a period of two frames using the PWM method. In FIG. 16, the selection period means a period for selecting a subgroup, that is, sg1 or sg2.

The selection period of each subgroup is divided into two,
The ratio between T1 and T0 indicating the length of the division time is 2: 1. If the seven gradations are expressed by gradation levels of 0/6 to 6/6, the relationship between each gradation level and the ON and OFF of the T1 and T0 periods in the first frame and the second frame is as shown in FIG. become. Here, “1” corresponds to the ON display, and “0” corresponds to the OFF display.

In the example shown in FIG. 16, the lowest grayscale level 0/6 is off during both the T1 and T0 periods of the two frames, and the highest grayscale level 6/6 is the T2 of the two frames.
Both the 1 and T0 periods are turned on. As shown in the figure, on-display and off-display are performed in T1 and T0 periods of two frames, as shown in the figure.

The voltage applied to the column electrode in this case will be described. For example, it is assumed that the gradation levels displayed on four lines L1, L2, L3, and L4 of a certain subgroup selected at the same time are 3/6, 2/6, 1/6, and 0/6.
Then, the ON / OFF display in the period of T1 and T0 in the selection period in the first frame is performed as shown in FIG.
Is [1,1], L2 is [1,0], L3 is [0,1],
L4 becomes [0,0].

FIG. 1 shows the period of T1 and T0.
When the voltage levels applied to the column electrodes are obtained using the Hadamard matrix of 4 rows and 4 columns shown in FIG. 3, the voltage waveforms are as shown in subframes 1 to 4 in FIG. That is, a change in the applied voltage level occurs when the period from T1 to T0 is switched between subframe 2 and subframe 3.

In FIG. 14, "-1" corresponds to the ON display, and "1" corresponds to the OFF display. Is set to “0”. The same applies to the example shown in FIG. Therefore, the voltage levels shown in FIG. 18 are obtained by setting “0” shown in FIG. 17 to “1” (off display) and “1” to “−1” (on display), This is equivalent to taking the bitwise product of the column values and summing the results.

At these changing points of the applied voltage, waveform distortion occurs as shown by a dotted line in FIG. Since this waveform distortion causes a loss of the effective value of the applied voltage, a so-called “display unevenness” occurs in which a luminance difference occurs in the display screen.
Causes a problem that the number increases. Further, in the case of the multiple line simultaneous selection method, the change in the voltage level is large so that the voltage change occurs between “−4” and “0” or “± 2”. Therefore, there is a problem that the waveform distortion increases accordingly.

In order to increase the number of gradations that can be displayed in two frames, each selection period may be divided into three as shown in FIG. FIG. 19 shows an example in which the ratio of the lengths T2, T1, and T0 of the three divided periods is 4: 2: 1. Then, the applied voltage waveform changes twice when switching between T2 and T1 and when switching between T1 and T0. Therefore, display unevenness further increases due to waveform distortion of the applied voltage.

[0018]

As described above, as described above,
In a liquid crystal display device in which a gradation display method based on the PWM method is applied to the simultaneous selection method for a plurality of lines, when the number of divisions in the selection period is increased in order to increase the number of gradations, a changing point of a voltage level applied to a column electrode becomes And as a result,
There is a problem that display unevenness due to distortion of the applied voltage waveform is increased.

An object of the present invention is to solve such a problem and to provide a driving method and a driving apparatus for a liquid crystal display device capable of increasing the number of gradations while suppressing display unevenness and obtaining high-quality display. And

[0020]

According to the present invention, the selection period of any one frame is divided into two for two consecutive display frames, and the time of each of the two divided periods is represented by T0 and T1. When the time of the selection period in the other frame is represented by T2, the respective times of T2, T1, and T0 are not made equal, and the number of gradations is increased by changing and applying pulse width modulation, In addition, two consecutive
If the selection periods of both frames are divided into two for one display frame, and the time of each of the two divided periods is represented by T3, T2, T0, T1, T3, T2, T
The gist is to increase the number of gradations by applying pulse width modulation after changing the times of 0 and T1 without making them equal. T2, T0, T1 or T3, T2, T0,
When T1 is set to a predetermined time ratio, one frame time is configured to be a time ratio selected from 50 to 90% of another frame time, and further, gradation display is performed by pulse width modulation. I do.

According to a first aspect of the present invention, there is provided a driving method of a liquid crystal display device, wherein a plurality of row electrodes of a liquid crystal display device having a plurality of row electrodes and a plurality of column electrodes are collectively selected, and each of the selected row electrodes is selected. A driving method of a liquid crystal display device for applying a predetermined voltage during a selection period.
A time ratio selected from 90% is set. Further, the selection period of either one frame or both frames is divided into two for two display frames, and one or more of the two display frames are divided. In the combination, ON data and OFF data are mixed in each period after division to perform gradation display by pulse width modulation.

According to a second aspect of the present invention, in the driving method of the liquid crystal display device, the time ratio of two consecutive display frames is set to 4
It is characterized in that the selection period in a short frame is divided into a time ratio of 2: 1. According to such a method, in 8-gradation display, the waveform distortion of the voltage level applied to the column electrode does not increase, and as a result, a display in which display unevenness is suppressed is realized.

According to a third aspect of the present invention, in the driving method of the liquid crystal display device, the time ratio of two consecutive display frames is set to 9
It is characterized in that the selection period in a long frame is divided into an 8: 1 time ratio, and the selection period in a short frame is divided into a 4: 2 time ratio. According to such a method, in 16-gradation display, waveform distortion of the voltage level applied to the column electrode does not increase, and as a result, display in which display unevenness is suppressed is realized.

According to a fourth aspect of the present invention, the driving method of the liquid crystal display device is based on pulse width modulation by mixing ON data and OFF data in each period after the division processing in two combinations of two display frames. It is characterized in that gradation display is performed. According to such a method, the waveform distortion of the voltage level applied to the column electrode does not increase, and as a result, a multi-gradation display exceeding 16 gradations in which display unevenness is suppressed can be realized.

According to a fifth aspect of the present invention, there is provided a driving device for a liquid crystal display device, wherein a plurality of row electrodes of a liquid crystal display device having a plurality of row electrodes and a plurality of column electrodes are collectively selected, and each of the selected row electrodes is selected. A driving device for a liquid crystal display device for applying a predetermined voltage during a selection period, wherein one frame time is selected from 50 to 90% of another frame time for a column driver for driving a column electrode. One or more combinations of two consecutive display frames having the same time ratio are configured, and the selection period of either one or both frames is divided into two for the two display frames, and a total of n ( timing control means for providing a timing signal so that n (an integer of 3 or more) divided periods are generated;
A gradation processing means for generating n-bit gradation data from the input image data and writing the same in the frame memory, and sequentially reading out the n-bit gradation data stored in the frame memory in each divided period to convert the column data Column data generating means for generating and supplying the generated column data to a column driver.

The n divided periods include a period generated by dividing the selected period and a period that is the selected period itself.

According to a sixth aspect of the present invention, in the driving device for a liquid crystal display device, the timing control means determines that the total time of two display frames displayed continuously and the time of an input frame to which image data is input are set. In this configuration, the timing signals are generated so as to be the same. According to such a configuration, writing and reading to and from the frame memory can be performed simultaneously, and the memory capacity can be reduced.

[0028]

Embodiments of the present invention will be described below. FIG. 1 is a block diagram showing an example of the configuration of a liquid crystal driving device for performing simultaneous selection driving of a plurality of lines according to the present invention. In FIG. 1, a liquid crystal driving device 10 receives image data 100 and a control signal 101, outputs a column data signal 104 to a column driver, and outputs necessary control signals 108 to a column driver and a row driver. . The control signal 101 includes a dot clock signal, a vertical synchronization signal, a horizontal synchronization signal, a data enable signal indicating a valid period of image data, and the like.

The liquid crystal driving device 10 is also provided with a row selection pattern generator for supplying a row selection pattern signal based on an orthogonal matrix as shown in FIG. 13 to a row driver, but is not shown in FIG. Omitted.

The image data 100 having the gradation signal inputted to the liquid crystal driving device 10 is inputted to the gradation processing circuit 11. The gradation processing circuit 11 receives the input image data 100
Is the gradation data 1 indicating the gradation level for each display frame.
02 and write it to the frame memory 12. The frame memory 12 holds the written gradation data until it is read a plurality of times in order to perform the multiple line simultaneous selection drive (MLA drive).

The MLA operation circuit 13 includes a frame memory 1
2 and 3 are read out and read out from FIG.
The voltage pattern applied to the column electrode is generated by performing the multiple line simultaneous selection calculation processing as exemplified in (1). And
The voltage pattern is output as a column data signal 104 to the column driver. A row selection pattern signal from the row selection pattern generator is output to a row driver. The timing control circuit 15 generates control signals 105, 106, and 107 necessary for each circuit block and a control signal 108 for a column driver and a row driver.

Note that the column driver operates as a column data signal 104.
In response to the above, a liquid crystal driving voltage is applied to the column electrodes of the liquid crystal panel. The row driver applies a predetermined voltage to a row electrode of the liquid crystal panel according to a row selection pattern signal. Next, the operation of the liquid crystal driving device of each example of the present invention will be described.

[Example 1] FIG. 2 is an explanatory diagram showing Example 1 in which eight gradations are displayed in a period of two frames. In Example 1, the first
The selection period in the frame is T2, and the selection period in the second frame is divided into T1 and T0. And T2, T1,
The time ratio of T0 is 4: 2: 1. Therefore, the length of the selection period in the first frame is different from the length of the selection period in the second frame. In this example, the period is divided only in the selected period in one frame.

If the eight gradations are expressed by gradation levels of 0/7 to 7/7, the relationship between the ON and OFF of the T2, T1, and T0 periods of the first frame and the second frame for each gradation level is shown in FIG. As shown. Here, “1” indicates ON,
“0” corresponds to the off display. Lowest gradation level 0 /
7 is turned off in the period of T2, T1, and T0, and the highest gradation level 7/7 is turned on in the period of T2, T1, and T0. On the other hand, at the intermediate gray level, ON display and OFF display are performed in the periods T2, T1, and T0 as shown in FIG.

As shown in FIG. 2, the division of the period is not performed in the selection period of the first frame, but is performed only in the selection period of the second frame. Therefore, the change in the applied voltage level during the selection period of the first and second frames occurs only at the switching point between T1 and T0 in the second frame.
Therefore, since the number of change points is small, the waveform distortion of the applied voltage is small, and as a result, display unevenness is reduced.

The gradation processing circuit 1 in the liquid crystal driving device 10
1 generates 3-bit gray-scale data [b2, b1, b0] from the image data 100 having the input gray-scale signal and writes it into the frame memory 12. As shown in FIG. 2, the relationship between the gradation data and the gradation level is [b2, b1, b
0] = [000] indicates the gradation level 0/7, and [b2,
[b1, b0] = [111] indicates the gradation level 7/7.

In order to realize the switching of the gradation levels as shown in FIG. 2, the MLA operation circuit 13 converts the gradation data of [b2, b1, b0] stored in the frame memory 12 into the first frame. B2 during the period, T1 of the second frame
In the period of b1, b1 is read in the period of T0, and the column data signal 104 ([c2, c1,
c0]). Further, the timing control circuit 15 determines that the time ratio between the first frame and the second frame is 4:
The latch signal to the column driver is controlled so as to be 3 and the time ratio of the division of the selection period in the second frame is 2: 1.

FIG. 3 shows the timing control circuit 15.
FIG. 4 is a timing chart showing the timing of a latch signal output from the latch circuit. As shown in the figure, the timing control circuit 15 determines that the column data signal (column data) c2 for the first subgroup (sg1) is M for the first frame.
When the data is output from the LA operation circuit 13 to the column driver, a latch signal for causing the column driver to take in data is output. Upon receiving the latch signal, the column driver applies a liquid crystal driving voltage corresponding to the input data to the column electrode.

Similarly, when the column data c2 for the second sub-group (sg2) is output from the MLA operation circuit 13 to the column driver and the latch signal is output from the timing control circuit 15 to the column driver, the column electrode Is applied with a predetermined voltage. Accordingly, the period between the latch signal and the next latch signal indicates T2, which is the selection period of one subgroup.

In the second frame, the column data c1 for the first subgroup (sg1) is stored in the MLA arithmetic circuit 1
3 is output to the column driver, and when the latch signal is output from the timing control circuit 15 to the column driver, a predetermined voltage is applied to the column electrode. Then, when the column data c0 is output from the MLA operation circuit 13 to the column driver and a latch signal is output from the timing control circuit 15 to the column driver, a predetermined voltage is applied to the column electrode. Hereinafter, a voltage is applied to the column electrodes in the same procedure.

Therefore, as shown in FIG. 3, the period of each latch signal represents the T1 period and the T0 period. As described above, the timing control circuit 15 controls the period of T2, T1, and T0 to be a 4: 2: 1 time ratio by changing the output timing of the latch signal.

[Example 2] FIG. 4 shows a case where 16
FIG. 9 is an explanatory diagram showing Example 2 for realizing gradation display. In Example 2, the selection period of the first frame is divided into T3 and T0, and the selection period of the second frame is divided into T2 and T1. T3
The ratio of the times T2, T1, and T0 is 8: 4: 2: 1. When the 16 gray scales are expressed by gray scale levels of 0/15 to 15/15, the relationship between each gray scale level and the ON / OFF states of the respective T3, T2, T1, and T0 periods in the first and second frames is shown in FIG. As shown in FIG.

Therefore, also in this example, the length of the selection period in the first frame is different from the length of the selection period in the second frame. In this example, the period is divided in the selection periods in both frames. Here, also, “1” corresponds to the ON display, and “0” corresponds to the OFF display.

The lowest gradation level 0/15 corresponds to T3, T
The display is turned off during the period T2, T1 and T0, and the uppermost gradation level 15/15 is turned on during the period T3, T2, T1 and T0. In addition, as shown in FIG. 4, on-display and off-display are performed during the periods T3, T2, T1, and T0 at the intermediate gradation levels.

When such division is performed, the change point of the applied voltage level during each selection period is the switching point between T3 and T0 in the first frame and T2 and T1 in the second frame.
Occurs at two switching points. That is, it occurs once in one selection period as in the case of the conventional example. Therefore, in this example, the degree of display unevenness due to waveform distortion is similar to that of the conventional example, but the number of gradations can be increased.

The gradation processing circuit 1 in the liquid crystal driving device 10
1 generates 4-bit gray-scale data [b4, b2, b1, b0] from the image data 100 having the input gray-scale signal, and writes it into the frame memory 12. As shown in FIG. 4, the relationship between the gradation data and the gradation level is [b3,
b2, b1, b0] = [0000] is the gradation level 0/1
5 and [b3, b2, b1, b0] = [1111] indicate the gradation level 15/15.

In this example, the timing control circuit 1
5 is such that the time ratio between the first frame and the second frame is 9: 6, the division ratio of the selection period in the first frame is 8: 1, and the division ratio of the selection period in the second frame is 8: 1. Control is performed so that the time ratio becomes 4: 2. MLA
The arithmetic circuit 13 stores [b] stored in the frame memory 12
3, b2, b1, b0], b3 during the period T3 of the first frame, b0 during the period T0, b2 during the period T2 of the second frame, and b1 during the period T1. Generate a column data signal to be output.

The timing control circuit 15
Controls the period of T3, T2, T1, and T0 so that the time ratio becomes 8: 4: 2: 1 by changing the output timing of the latch signal, as in the case of Example 1.

[Example 3] Next, a method of further increasing the number of gradations by setting the number of frames for realizing the gradation display to 4 frames will be described. A case where 21 gradation display is performed in four frames will be described. As shown in FIG. 5, the selection period in the first and third frames is T2, and the selection period in the second and fourth frames is divided into T1 and T0. The ratio of the times T2, T1 and T0 is 6: 3: 1 or 6: 3: 2.

If ON and OFF are mixed during the periods T2, T1, and T0 in the four frames, 21 types of gradation display can be performed. For example, FIG. 6 shows that the ratio of T2, T1, T0 is 6:
An example of gray scale display in the case of 3: 1 is shown. FIG. 7 shows an example of gradation display when the ratio of T2, T1, and T0 is 6: 3: 2. There are 21 types of gradation levels shown in FIG. 6 from 0/20 to 20/20.
Are the gradation levels 0/22, 2/22 to 20/2.
2, and 21 types of 22/22.

In FIGS. 6 and 7, f1, f2, f
3 and f4 indicate frame numbers. Also here,
“1” indicates ON and “0” indicates OFF. Also in the case of these divisions, since the change point of the applied voltage level during the selection period occurs only at the switching point between T1 and T0 in the second or fourth frame, the waveform distortion is small and the display unevenness does not increase.

Next, the operation of the liquid crystal driving device 10 of the present embodiment will be described with reference to FIGS. FIG.
FIG. 4 is an explanatory diagram showing how data is written and read from the frame memory 12.

When writing the gradation data into the frame memory 12, T2 of the first frame and T2 of the second frame
3-bit gray-scale data [b2, b1, b0] indicating ON / OFF display in the period of 1, T0, and 3-bit indicating ON / OFF display in the period T2 of the third frame and T1, T0 of the fourth frame. It is possible to write both 6 bits of the grayscale data [b2, b1, b0] to the frame memory 12. However, when such control is performed, the capacity of the frame memory 12 increases and the cost of the display device increases.

Therefore, the writing and reading of the gradation data are performed with reference to the input frame indicating the time when the image data for one screen is input. That is, the gradation processing circuit 11
Converts the image data 100 input during the period of the input frame 1 into gradation data [b2, b1, b0] for the first frame and the second frame as shown in FIG. Write. The following input frame 2
In the period, the image data 100 is converted into the gradation data [b2, b1, b0] for the third and fourth frames.
And writes it to the frame memory 12.

The MLA operation circuit 13 outputs the gradation data [b] stored in the frame memory 12 during the period of the input frame 1.
2, b1, b0], b2 is read during the period T2 of the first frame, b1 is read during the period T1 of the second frame, and b0 is read during the period of T0. Further, the grayscale data [b2, b] stored in the frame memory during the period of the input frame 2
[B] in the period T2 of the third frame.
2. b1 in the period T1 of the fourth frame and b in the period T0
0 is read out.

According to such control, since writing and reading of 3 bits are performed on the frame memory 12 as in the case of Example 1, there is no need to increase the memory capacity.

The timing control circuit 15 uses T
When the division ratio of 2, T1, T0 is 6: 3: 1, the first
The time ratio between the frame and the second frame and the time ratio between the third and fourth frames are set to 6: 4, and the time ratio for dividing the selection period is set to 3: 1 in the second and fourth frames. To control. When the division ratio of T2, T1, and T0 is 6: 3: 2, the time ratio between the first and second frames and the third and fourth frames are 6: 5, and In the second and fourth frames, control is performed such that the time ratio of the division of the selection period is 3: 2.

It is to be noted that the timing control circuit 15 controls the time ratio by changing the output timing of the latch signal in the same manner as in each of the above examples.
In this example, the time ratio of the first frame to the second frame and the time ratio of the third frame to the fourth frame are the same, and the time ratio of the division of the selection periods of the second and fourth frames is the same. is there. Accordingly, if attention is paid only to the output timing of the latch signal, the timing control is performed in units of two frames.

[Example 4] Next, Example 4 in which 45 frames are displayed in 4 frames will be described. In this example, as shown in FIG. 9, the selection period in the first frame and the third frame is T3.
And T0, and the selection period in the second and fourth frames is divided into T2 and T1. T3, T2, T1, T0
The time ratio is 12: 6: 3: 1 or 12: 6: 3:
2.

If ON and OFF are mixed during the period of T3, T2, T1, and T0 in the four frames, display of 45 kinds of gradations is possible. FIG. 10 shows an example of gradation display when the ratio of T3, T2, T1, and T0 is 12: 6: 3: 1. FIG. 11 shows T3, T2, T1, and T0.
The example of the gray scale display when the ratio is 12: 6: 3: 2 is shown. The gradation levels shown in FIG.
/ 44, and the gradation level shown in FIG.
/ 46, 2/46 to 44/46, and 46 / 46-4
There are five types. Note that f1, f in FIGS. 10 and 11 are used.
2, f3 and f4 indicate frame numbers, "1" is on,
“0” indicates off.

In the case of these divisions, the change point of the applied voltage level during the selection period is the switching point between T3 and T0 in the first frame and the third frame, and the second frame or the fourth frame.
It occurs at the switching point of the frame between T2 and T1. That is, only three application voltage level switchings occur in at most four frames. Therefore, the waveform distortion does not increase and the display unevenness does not increase.

Next, the operation of the liquid crystal driving device 10 of this embodiment will be described with reference to FIGS. The gradation processing circuit 11 converts the image data 100 input during the period of the input frame 1 into gradation data [b3, b2, b1, b0] for the first frame and the second frame, and stores the converted data in the frame memory 12. Write. The following input frame 2
In the period of, the image data 100 is divided into the gradation data [b3, b2, b1,
b0] and writes it to the frame memory 12.

The MLA operation circuit 13 outputs the gradation data [b] stored in the frame memory 12 during the period of the input frame 1.
3, b2, b1, b0], b3 is read in the period T3 of the first frame, b0 is read in the period of T0, b2 is read in the period of T2 in the second frame, and b1 is read in the period of T1. Also, from the gradation data [b3, b2, b1, b0] stored in the frame memory during the period of the input frame 2, the third
B3 during the T3 period of the frame, b0 during the T0 period, the fourth
B2 is read out during the period T2 of the frame, and b1 is read out during the period of T1.

The timing control circuit 15
3, T2, T1, and T0 have a division ratio of 12: 6: 3: 1, the time ratio of the first frame to the second frame and the time ratio of the third frame to the fourth frame are 13: 9. ,
In the first and third frames, the division ratio of the selection period is 1
In the second and fourth frames, control is performed so that the time ratio of the division of the selection period is 6: 3.

When the division ratio of T3, T2, T1, and T0 is 12: 6: 3: 2, the time ratio between the first and second frames and the time ratio between the third and fourth frames are different. 13: 9, and control is performed so that the division ratio of the selection period is 12: 2 in the first and third frames, and the division ratio of the selection period is 6: 3 in the second and fourth frames. .

It is to be noted that the timing control circuit 15 controls the time ratio by changing the output timing of the latch signal in the same manner as in the above examples.
Further, in this example, the time ratio between the first frame and the second frame and the time ratio between the third frame and the fourth frame are the same, and the time ratio of the division in the selection period of the first and third frames is the same as the second time ratio. , And the time ratio of division in the selection period of four frames is the same. Accordingly, if attention is paid only to the output timing of the latch signal, the timing control is performed in units of two frames.

As described above, in each of the above examples, the time ratio between the first frame and the second frame is different between two frames that are continuously displayed.
The timing is controlled so that the selection period of one or both frames is divided into different time ratios for the first frame and the second frame. Specifically, Examples 1 to
The time ratio for No. 4 is as follows.

[0068]

[Table 1]

The time ratio between the first frame and the second frame can be variously selected according to the required number of gradations and the like. However, if there is an extreme difference, the operating frequency becomes higher in the shorter frame. Is not preferred. If there is not much difference, it is often necessary to shorten one of the divided selection periods in a frame in which the selection period is divided. In consideration of such circumstances, it is appropriate that the time ratio between the first frame and the second frame is about 50 to 90%.

Further, when gradation display is realized by four consecutive frames, the time ratio between the third frame and the fourth frame is the same as the time ratio between the first frame and the second frame. That is, even when gradation display is realized with four frames, the time ratio between two consecutive frames (for example, an odd frame and an even frame) is the same.

[0071]

As described above, according to the present invention,
The driving method and the driving device of the liquid crystal display
One display frame is configured such that one frame time is a time ratio selected from 50 to 90% of the other frame time, and furthermore, either one frame or both frames for two display frames Selection period of 2
The number of gray scales is increased because the gray scale display is performed by pulse width modulation by mixing ON data and OFF data in each of the divided periods in one or more combinations of two display frames. In this case, high-quality display can be obtained by increasing the number of gradations while suppressing display unevenness. That is, the division ratio of the selection period can be improved without increasing the number of divisions during the selection period. For example, a multi-level of 8 gradations or 16 gradations in 2 frames and 21 gradations or 45 gradations in 4 frames. Key display becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a liquid crystal driving device according to the present invention.

FIG. 2 is an explanatory diagram showing an example 1 in which 8-gradation display is performed in a period of two frames.

FIG. 3 is a timing chart showing the timing of a latch signal output by a timing control circuit.

FIG. 4 is an explanatory diagram showing an example 2 in which 16-gradation display is realized in a period of two frames.

FIG. 5 is an explanatory diagram showing division of a selection period in Example 3.

FIG. 6 is an explanatory diagram showing an example of gradation data in Example 3.

FIG. 7 is an explanatory diagram showing another example of the gradation data in Example 3.

FIG. 8 is an explanatory diagram showing writing and reading of gradation data to and from a frame memory in Examples 3 and 4.

FIG. 9 is an explanatory diagram showing division of a selection period in Example 4.

FIG. 10 is an explanatory diagram showing an example of gradation data in Example 4.

FIG. 11 is an explanatory view showing another example of the gradation data in Example 4.

FIG. 12 is an explanatory diagram showing an example of pixels in 8 rows and 2 columns.

FIG. 13 is an explanatory diagram showing an example of a 4 × 4 Hadamard matrix.

FIG. 14 is an explanatory diagram showing an example of column electrode data.

FIG. 15 is a timing chart showing an example of a column electrode voltage waveform.

FIG. 16 shows a diagram of 7 in a two-frame period using the PWM method.
FIG. 3 is an explanatory diagram showing a conventional example of performing grayscale display.

FIG. 17 is an explanatory diagram showing an example of gradation data in a conventional example.

FIG. 18 is an explanatory diagram showing an example of a voltage level applied to a column electrode in a conventional example.

FIG. 19 is an explanatory diagram showing division of a selection period in a conventional example.

[Explanation of symbols]

 Reference Signs List 10 liquid crystal drive device 11 gradation processing circuit 12 frame memory 13 MLA operation circuit

Continued on the front page (72) Inventor Makoto Nagai 1150 Hazawa-cho, Kanagawa-ku, Yokohama-shi, Kanagawa Prefecture F-term in Asahi Glass Co., Ltd. GA02 5C080 AA10 BB05 DD05 EE29 FF10 JJ02 JJ04 JJ05

Claims (6)

[Claims] 1. A plurality of row electrodes of a liquid crystal display device having a plurality of row electrodes and a plurality of column electrodes are collectively selected, and a predetermined voltage is applied to each of the selected row electrodes during a selection period. In the method of driving a liquid crystal display device, two display frames that are continuously displayed are configured so that one frame time has a time ratio selected from 50 to 90% of another frame time, The selection period of either one frame or both frames is divided into two for one display frame, and ON data and OFF data are mixed in each of the divided periods in one or more combinations of the two display frames. A gradation display by pulse width modulation using a pulse width modulation method. 2. The driving of the liquid crystal display device according to claim 1, wherein a time ratio of two display frames displayed continuously is set to 4: 3, and a selection period in a short frame is divided into a time ratio of 2: 1. Method. 3. A time ratio of two display frames displayed continuously is set to 9: 6, and a selection period in a long frame is set to 8:
2. The driving method for a liquid crystal display device according to claim 1, wherein the liquid crystal display device is divided into a time ratio of 1: 1, and a selection period in a short frame is divided into a time ratio of 4: 2. 4. A driving method for a liquid crystal display device according to claim 1, wherein the on-data and the off-data are mixed in each of the divided periods in the two combinations of the two display frames to perform gradation display by pulse width modulation. Method. 5. A liquid crystal display in which a plurality of row electrodes of a liquid crystal display device having a plurality of row electrodes and a plurality of column electrodes are collectively selected and a predetermined voltage is applied to each selected row electrode during a selection period. In the apparatus driving apparatus, one or more of two consecutive display frames in which one frame time has a time ratio selected from 50 to 90% of another frame time for a column driver driving a column electrode. A combination is formed, and the selection period of either one or both frames is divided into two for the two display frames, and a total of n (n: an integer of 3 or more) is obtained.
Timing control means for providing a timing signal so that a plurality of divided periods are generated; grayscale processing means for generating n-bit grayscale data from input image data and writing the grayscale data to a frame memory; A liquid crystal display device comprising: column data generating means for sequentially reading n-bit gradation data stored in a frame memory to generate column data, and supplying the generated column data to the column driver. Drive. 6. The timing control device according to claim 5, wherein the timing control means generates a timing signal such that the total time of two display frames displayed continuously and the time of an input frame to which image data is input become the same. A driving device for a liquid crystal display device according to claim 1.