JP2000269941A - Clock reloading circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily avoid a slip without changing the readout order of readout addresses by writing input data to a storage means according to write addresses, reading the input data out according to the readout addresses, alternately placing read and write means in operation, and selecting and outputting input data read out by a read and write means in operation. SOLUTION: Memories 10-1 and 10-2 of systems 1 and 2 are placed in operation by turns, in with of frames, by using input frame pulses and the memory 10-1 of the system 1 are placed in writing and reading operation by a choice 1 and a choice 2 for the 1st frame of input data. By using different memories for each frame, both the write and read addresses overlap with each other, even at the place where the reading of a last frame as a slip occurrence place and the writing of a next frame overlap with each other, so that a slip can be avoided without varying a WR-RD address initial phase difference and the memory capacity and changing the readout order of RD addresses.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock transfer circuit suitable for use in a synchronous multiplex transmission device or the like.

[0002]

2. Description of the Related Art (1) First Conventional Example A clock transfer circuit according to a first conventional example generates a memory 10 and a write address WR and a read address RD for the memory 10 as shown in FIG. Address generators 11a and 11b, and a phase comparator 1 that monitors an address phase difference between the addresses WR-RD.
And 2.

According to such a configuration, input data including a gap synchronized with the clock A is written into the memory 10 using the write address WR also synchronized with the clock A, while the clock B asynchronous with the clock A is written. The data is read from the memory 10 using the read address RD synchronized with. Further, since the address WR-RD is asynchronous, the phase comparison unit 12 always monitors the address phase difference between the WR-RD, and when the read address RD is about to overtake the write address WR. Then, the phase comparison unit 12 outputs a forced stop signal to the read address generation unit 11b to adjust the phase difference, and performs clock switching in the manner shown in FIG.

A feature of this clock change is that the phase difference is adjusted by comparing the phase difference between the addresses WR and RD. The gap included in the input data due to the phase difference adjustment (* in FIG. 4) ** part) is directly transmitted to the output. In general, a clock generation circuit for generating a clock from a data string is often added to the next stage of the clock transfer circuit,
In this case, if the time width of the gap included in the data string is large, the jitter (frequency deviation) of the generated clock may be adversely affected. In the case where the data train corresponding to the transmission frame SDH / VC11 is actually clocked and used in the above-described conventional technique, a gap of about 15 bits is directly propagated from the input to the output in 1.62 MHz conversion, which adversely affects the jitter. Some examples have been reported.

(2) Second Conventional Example Therefore, in recent years, a technique for solving the above-mentioned problem has been devised, and as a configuration, as shown in FIG. An address generator 11a that generates a write address WR and a read address RD,
There is a known type that includes a delay unit 13b (in the example, a 2-bit delay) that generates an initialization signal of the write RD address generation unit 11a and performs clock transfer. According to the second conventional example, data is written to the same input data as the conventional one by using the write address WR initialized for each frame by the input frame pulse, and furthermore, by the delayed frame pulse from the delay unit 13, By reading data from the memory 10 using the read address RD initialized for each frame, the clock is switched in the manner shown in FIG.

In the second prior art, the clock switching is based on the precondition that the input data has some frame structure and a frame pulse exists. In such a technique, the method of initializing the address phase difference between the addresses WR and RD (periodical phase difference adjustment) is changed from the method of adjusting the phase difference to the method of initializing the address phase difference between the addresses WR and RD on a frame basis. The read order of the read addresses RD is devised so that the gap is dispersed (for example, AB * CA *
BCABC *, etc.) to easily disperse the gap,
It is possible to minimize it.

[0007]

In the above-mentioned second conventional example, there are conditions such as an initial phase difference between the addresses WR and RD, a position of a gap included in input data, a time width, and a memory capacity. When the condition is satisfied, there is a possibility that the reading of the previous frame and the writing of the next frame may overlap. In this case, as shown in FIG.
A phenomenon called "slip" occurs in which R and the read address RD match to cause data destruction.

FIG. 7 introduces a simple case, so that slips can be easily eliminated by avoiding measures such as changing the initial phase difference between the addresses WR and RD, changing the memory capacity, and changing the RD address reading order. Although it is possible to avoid the slip, when the slip occurs by applying the second related art to a complicated and long input frame (for example, an SDH frame) used in an actual transmission device or the like, the above-described workaround is provided. Is often extremely difficult to do.

The present invention has been made in view of such circumstances, and easily avoids slippage without changing the initial phase difference between a read address and a write address, or changing the read order of read addresses. It is an object of the present invention to provide a clock transfer circuit that can be used.

[0010]

In order to achieve the above object, according to the first aspect of the present invention, while input data is written to storage means in accordance with a write address generated in synchronization with a first clock, Two systems of read / write means for reading input data from the storage means in accordance with a read address generated in synchronization with a second clock, and two systems of read / write in frame units in accordance with an input frame pulse Read / write control means for operating the means alternately and selecting and outputting input data to be read by the read / write means on the operated side.

In the invention according to claim 2 dependent on claim 1, the read / write control means assigns any one of the write addresses of the two systems of read / write means in response to an input frame pulse. A write selecting means for selecting, a read selecting means for selecting one of read addresses of two read / write means in accordance with an input frame pulse, and a corresponding system in response to a read address selected by the read selecting means. Output selection means for selecting input data to be read by the storage means on the side and outputting the selected input data to the next stage.

Further, in the invention according to claim 3 dependent on claim 1, the read / write control means performs writing and reading to and from the storage means by one of the read / write means. While the other lead
The writing means is initialized.

According to the present invention, two systems of read / write means are alternately operated in frame units in accordance with an input frame pulse, and input / output data read by the operated read / write means is selected and output. The storage means used for each frame is different. Therefore, even at the position where the reading of the previous frame and the writing of the next frame, which is the location where the slip occurs, the writing / reading address is not overlapped. Can be easily avoided without changing the initial phase difference or changing the reading order of the read addresses.

[0014]

An embodiment of the present invention will be described below with reference to the drawings. First, FIG. 1 is a block diagram showing a configuration of a clock transfer circuit according to an embodiment of the present invention. Note that among the components shown in this figure, elements common to the above-described second conventional example are given the same numbers, and
The description is omitted. The clock transfer circuit shown in FIG. 1 includes a memory 10 and an initializable write address WR.
And two address generators 11a and 11b (hereinafter, referred to as 1 system / 2 systems) for generating a read address RD, and a write address WR selection signal (select 1)
, A delay unit 13 for generating a read address RD and an output selection signal (selection 2), and an output selection unit 15 for selecting an output.

In such a configuration, the first and second memories 10 and 10 are used for each frame by using the input frame pulse.
-1 and 10-2 are alternately operated. First, in the first frame, writing and reading are performed in the first-system memory 10-1 by selecting the selection 1 and the selection 2 in the first frame. In the meantime, the write address WR generator 11a-2 and the read address RD generator 11b-2 of the second system are initialized, and the memory 10-2 of the second system is also stopped.

Next, in the second frame, the operations of the first and second systems are reversed. That is, the memory 1 of the second system
Writing and reading are performed for 0-2, during which time the write address WR generator 11a-1 and the read address RD generator 11b-1 of the first system are initialized, and therefore, the memory 10-1 of the first system is also initialized. It will be stopped. These operations are alternately repeated for each frame between the 1-system / 2-system, and the 1-system / 2-system is selected by the selection 2 at the output stage.
By selecting the output of the system, clock switching is performed in the form shown in FIG.

As described above, according to the present invention, since the memory used for each frame is different (system 1 / system 2), even in the position where the reading of the previous frame and the writing of the next frame, which are the locations where the slip occurs, overlaps. Since both the write and read addresses do not overlap, it is possible to avoid a slip without changing the initial phase difference between the WR and RD addresses, changing the memory capacity, changing the read order of the RD addresses, and the like. It is a translation. Note that the meaning of no change in the memory capacity in the present invention means no change for the amount on the time axis (4 bits of ABCD in the example).
Strictly, the capacity is doubled because two memories in the second conventional example are used.

[0018]

According to the present invention, two systems of read / write means are alternately operated in frame units in accordance with an input frame pulse, and input data to be read by the operated read / write means is selected. Since the output means outputs different storage means for each frame, the write and read addresses do not overlap even at the position where the reading of the previous frame and the writing of the next frame, which are the locations where slips occur, are not duplicated. The slip can be easily avoided without changing the initial phase difference between the read address and the write address, or changing the read order of the read address.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a clock transfer circuit according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining an operation example of the clock transfer circuit according to the embodiment;

FIG. 3 is a diagram for explaining a first conventional example.

FIG. 4 is a diagram for explaining a first conventional example.

FIG. 5 is a diagram for explaining a second conventional example.

FIG. 6 is a diagram for explaining a second conventional example.

FIG. 7 is a diagram for explaining a slip phenomenon.

[Explanation of symbols]

 10-1, 10-2 Memory 11a-1, 11a-2 Write Address WR Generation Unit 11b-1, 11b-2 Read Address RD Generation Unit 12 Phase Comparison Unit 13 Delay Unit 14 Selection Signal Generation Unit 15 Output Selection Unit

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[Procedure amendment]

[Submission date] March 21, 2000 (200.3.2
1)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction contents]

[0010]

In order to achieve the above object, according to the first aspect of the present invention, while input data is written to storage means in accordance with a write address generated in synchronization with a first clock, Two systems of read / write means for reading input data from the storage means in accordance with a read address generated in synchronization with a second clock, and two systems of read / write in frame units in accordance with an input frame pulse operating the means alternately; and a read-write control means selects and outputs the input data operation the side of the read-write means reads said Li
The write / write control means responds to the input frame pulse.
Therefore, there are two types of read / write means for each frame.
Write control means for selecting a shift write address
And two systems for each frame according to the input frame pulse
Any read address of the read / write means
Reading selecting means for selecting the data, and the reading selecting means
Corresponding to the read address selected by the
Selects input data to be read by the storage means and outputs it to the next stage
Output selection means for
Writing and reading to storage means by write / read means
The other side's read / write means during initialization.
Characterized by reduction.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Deleted

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Deleted

Claims (3)

[Claims] An input data is written to a storage unit in accordance with a write address generated in synchronization with a first clock, and input data is written from the storage unit in accordance with a read address generated in synchronization with a second clock. Two systems of read / write means for reading input data are provided, and two systems of read / write means are alternately operated in frame units in response to an input frame pulse, and input data read by the operated read / write means is read out. And a read / write control means for selectively outputting. 2. The read / write control means includes a write selection means for selecting a write address of any one of two read / write means in accordance with an input frame pulse, and two systems in response to an input frame pulse. Read selection means for selecting any one of the read addresses of the read / write means, and input data to be read by the corresponding storage means on the system side in accordance with the read address selected by the read selection means and output to the next stage. 2. The clock transfer circuit according to claim 1, further comprising output selection means. 3. The read / write control means initializes the read / write means on the other side while writing and reading to / from the storage means are performed by the read / write means on one side. 2. The clock transfer circuit according to claim 1, wherein: