JP2000278062A - Automatic gain control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain a light weight, a small size and a low cost for a receiver used for a mobile communication terminal or the like by realizing an automatic gain control circuit having more stable automatic gain compensation with less number of components than that of a conventional control circuit. SOLUTION: A level detection circuit 104 samples a demodulation output obtained through an A/D converter 101, an orthogonal demodulator 102 and a digital filter 103 for a prescribed period to obtain a mean value A. The level detection circuit 104 sets a reciprocal of a quotient N to a multiplier 106, where the N is obtained by dividing the calculated mean value A of received signal levels by a target value for received signal level B. A filter coefficient output circuit 105 sets a new filter coefficient resulting from multiplying the reciprocal 1/N with a current filter coefficient of the digital filter 103 to the multiplier 106. The gain compensation is realized by rewriting the filter coefficient of the digital filter every moment so that a mean level of levels of output signals from the digital filter 103 reaches an expected signal level at all times.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic gain control circuit for compensating a gain of a received signal level to an expected signal level.

[0002]

2. Description of the Related Art FIG. 9 shows a conventional automatic gain control circuit.
In FIG. 9, a QPS consisting of an intermediate frequency (IF) signal
The reception signal of the K wave is given an attenuation amount corresponding to the fluctuation of the input signal in the variable attenuator 903, and then is digitally converted in the A / D converter 101. After that, the detection output composed of the I channel (in-phase component) and the Q channel (quadrature component), which has been quadrature-detected by the quadrature demodulator 102, undergoes a required band limitation through the digital filter 103, and becomes a demodulated output. On the other hand, the level detection circuit 104
Is connected to the output of the digital filter 103, monitors the level of the reception signal output from the digital filter 103, and controls the D / A output circuit so that the average value of the reception signal level is constant. A control signal is output to 901. The D / A output circuit 901 outputs a D / A converter 90 according to a signal obtained from the level detection circuit 104.
2, data of the amount of gain to be compensated is output as needed. This data is converted to an analog signal via a D / A converter 902 and supplied to a variable attenuator 903. Variable attenuator 9
In reference numeral 03, the demodulation output level is maintained at a desired level by changing the attenuation amount according to the analog signal.

[0003]

In recent years, mobile communication devices, especially mobile communication terminals used in mobile communication systems such as mobile phones, have exploded and are expected to continue to increase in demand in the future. . It is no exaggeration to say that the biggest issue in the market for such mobile communication terminals is weight reduction.

An object of the present invention is to realize a more stable automatic gain compensation with a smaller number of parts than a conventional automatic gain control circuit, and to reduce the weight and size of a receiving apparatus such as a mobile communication terminal and to reduce the cost. It is an object of the present invention to provide an automatic gain control circuit.

[0005]

An automatic gain control circuit according to the present invention comprises an A / D converter for digitally converting a QPSK wave reception signal composed of an intermediate frequency signal, and a quadrature detection of an output from the A / D converter. A quadrature demodulator that performs the necessary band limitation on the detection output consisting of the in-phase and quadrature components, and a digital filter for demodulation output, and is connected to the output of the digital filter and monitors the level of the demodulation signal output from the digital filter. A level detection circuit that outputs data so that the average value of the demodulated signal level is constant; a filter coefficient output circuit that outputs a filter coefficient;
By multiplying the data output from the level detection circuit and the filter coefficient output from the filter coefficient output circuit,
A multiplier that sets the digital filter and updates a filter coefficient held in the filter coefficient output circuit.

[0006]

Next, an embodiment of the present invention will be described with reference to the drawings.

The present invention relates to an automatic gain control for compensating a gain of a received signal level to an expected signal level.
By realizing this gain compensation using a digital filter, a circuit dedicated to automatic gain control is reduced, and stable gain control is enabled.

FIG. 1 is a block diagram showing a first embodiment of the automatic gain control circuit according to the present invention. The automatic gain control circuit shown in FIG. 1 includes an A / D converter 101, a quadrature demodulator 102, a digital filter 103, a level detection circuit 104, a filter coefficient output circuit 105, a multiplier 1
06.

In FIG. 1, a received QPSK signal consisting of an intermediate frequency (IF) signal is digitally converted by an A / D converter 101. Then, the quadrature demodulator 10
A detection output composed of an I channel (in-phase component) and a Q channel (quadrature component), which has been subjected to quadrature detection in 2, undergoes a required band limitation via a digital filter 103, and becomes a demodulated output.

On the other hand, the level detecting circuit 104 is connected to the output of the digital filter 103, monitors the level of the received signal output from the digital filter 103, and keeps the average value of the received signal level constant. The data is output to the multiplier 106 such that

The filter coefficient output from the filter coefficient output circuit 105 is multiplied by the data set in the multiplier 106 to be set in the digital filter 103, and the filter coefficient held in the filter coefficient output circuit 105 is also changed. Update.

FIG. 2 is a block diagram showing a configuration example of the digital filter 103 according to the first embodiment.
As an example, the number of TAPs is six.

The data series inputted to each of the delay circuits 301 to 306 are respectively multiplied by filter coefficients C0 to C5 by a multiplier 3
After multiplication at 07 to 312, adders 313 and 3
At 14, all I and Q channels are added and output. The filter coefficients C0 to C5 can be set from the outside, and it is assumed that all the filter coefficients are instantaneously rewritten at a time when they are changed.

FIG. 3 is a block diagram showing an example of the configuration of the level detection circuit 104 according to the first embodiment.

The input I-channel and Q-channel signals are squared in multipliers 401 and 402, respectively, and then added in an adder 403. Where I ² +
The data obtained as Q ² is added to the adder 404 and the latch circuit 4.
The average value A is calculated by performing the addition for a fixed number of times using 05. The average value A is normalized by the target value B in the multiplier 406. The normalized value N becomes 1 / N in the reciprocal operation unit 407 and is output.

Now, it is assumed that the filter coefficient when the average value of the received signal level monitored by the level detection circuit 104 is equal to the target value is as shown in FIG. If the average value of the received signal levels detected by the level detection circuit 104 becomes 3/2 times the target value, the level detection circuit 104 sets the value of the multiplier 106 to 2/3.

The filter coefficient output from the filter coefficient output circuit 105 is multiplied by 2/3 in a multiplier 106.
This is sent to the digital filter 103. That is, the filter coefficient of FIG. 4B, which is ／ of the filter coefficient shown in FIG. 4A, is set in the digital filter 103. At the same time, the filter coefficient newly set in the digital filter 103 is also sent to the filter coefficient output circuit 105, and the filter coefficient held by the filter coefficient output circuit 105 is also updated.

As described above, the level detection circuit 104 updates the value set in the multiplier 106 at any time according to the detected received signal level, so that the average output level of the digital filter 103 always has the same value as the target value. And automatic gain control is realized.

FIG. 5 is a flowchart for explaining the operation of the first embodiment shown in FIG. The operation of the embodiment of the present invention will be described with reference to FIGS.

First, initial values C0 to C5 of filter coefficients are given to the digital filter 103 (step A1).

The level detection circuit 104 samples the demodulated output obtained through the A / D converter 101, the quadrature demodulator 102, and the digital filter 103 at a constant period to obtain an average value, which is defined as A (step A2).

Further, the level detection circuit 104 divides the calculated average value A of the received signal level by the target value B of the received signal level, sets this solution as N (step A3), and sets the reciprocal of N in the multiplier 106. I do.

The filter coefficient output circuit 105 sets the values obtained by multiplying the filter coefficients C0 to C5 of the current digital filter by the reciprocal 1 / N of N as new filter coefficients C0 to C5 of the digital filter. (Step A4).

After that, by repeating the operations other than the step A1, the filter coefficient of the digital filter 103 changes every moment so as to keep the level of the received signal constant, and the average value of the output signal level of the digital filter 103 is changed. Will always be automatically gain compensated to the expected signal level.

As described above, the level detection circuit 104
Monitors the level of the demodulated output of the digital filter 103 and rewrites the filter coefficient of the digital filter every moment so that the level becomes an expected level. As a result, the variable attenuator, D / A converter, and the like required by the conventional automatic gain control circuit can be eliminated. Further, since all of them are realized in a digital circuit, there is no change in characteristics due to the ambient temperature, and stable gain compensation can be performed.

Next, a second embodiment of the present invention will be described with reference to FIGS.

FIG. 6 is a block diagram showing an example of the configuration of the level detection circuit 104 according to the second embodiment of the present invention. The configuration of the entire automatic gain control circuit is the same as that shown in FIG. It is.

The input I-channel and Q-channel signals are squared in multipliers 401 and 402, respectively, and then added in an adder 403. Where I ² +
The data obtained as Q ² is added to the adder 404 and the latch circuit 4.
The average value A is calculated by performing the addition for a fixed number of times using 05. The average value A is normalized by the target value B in the multiplier 406. The normalized value N becomes 1 / N in the reciprocal operation unit 407.

On the other hand, the average value A is also input to the comparator 601, and is compared with the target value B ± T (T is an allowable range). Vessel 6
01 outputs a control signal to the switch 602.
Switch 602 receiving control signal from comparator 601
Ignores the input from the reciprocal operation unit 407 and returns the value “1”.
Is output.

FIG. 7 is a flowchart for explaining the operation of the second embodiment of the present invention. The operation of the second embodiment of the present invention will be described with reference to FIGS.

First, initial values C0 to C5 of filter coefficients are given to the digital filter 103. (Step A1).

The level detection circuit 104 samples the received signal obtained through the A / D converter 101, the quadrature demodulator 102, and the digital filter 103 at a constant period to obtain an average value. (Step A2).

Further, the level detection circuit 104 determines whether the calculated A is within the recognized received data range (step B1), and if it is within the allowable range, N = 1 (step B2). .

If A is outside the allowable range of the received data, the average value A is divided by the target value (B) of the received data, and this solution is set to N (step B3).

The filter coefficient output circuit 105 sets the values obtained by multiplying the current filter coefficients C0 to C5 of the digital filter by the reciprocal 1 / N of N as new filter coefficients C0 to C5 of the digital filter. (Step A4).

Thereafter, operations other than step A1 are repeated, so that automatic gain compensation is performed only when the demodulated output is out of the allowable range T of the target value B.

In the second embodiment, the comparator 601 is used.
Control signal output from the filter coefficient output circuit 105
And the filter coefficient output circuit 105 outputs the filter coefficient only when the average value of the demodulation output level is out of the allowable range.

Further, the present invention can be easily realized by using a CPU instead of the level detection determination circuit in the first and second embodiments. This is a third embodiment, and a block diagram is shown in FIG.

In FIG. 8, the demodulated output of the digital filter 103 is input to the RAM 801. RAM 801
Is assumed to hold a fixed number of data obtained from the digital filter 103 by changing the address. CPU 802
Reads the data in the RAM 801 and performs the processing of steps A2 to A3 and B1 to B3 in FIGS.
The coefficient is set in the multiplier 106.

[0040]

As described above, if the automatic gain control circuit of the present invention is used, the D / A output circuit 901, the D / A converter 902,
The variable attenuator 903 can be eliminated, and a great effect can be expected on reduction in weight and size and cost in mobile communication terminals. In addition, since all automatic gain control is realized by a digital circuit, the ambient temperature is reduced. Even if it changes, gain compensation with stable characteristics can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of an automatic gain control circuit according to the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a digital filter.

FIG. 3 is a block diagram illustrating a configuration example of a level detection circuit according to the first embodiment.

FIG. 4 is a diagram illustrating an example of a filter coefficient.

FIG. 5 is a flowchart illustrating the operation of the first embodiment.

FIG. 6 is a block diagram illustrating a configuration example of a level detection circuit according to a second embodiment;

FIG. 7 is a flowchart illustrating the operation of the second embodiment.

FIG. 8 is a block diagram showing a third embodiment of the present invention.

FIG. 9 is a block diagram of a conventional automatic gain control circuit.

[Explanation of symbols]

Reference Signs List 101 A / D converter 102 Quadrature demodulator 103 Digital filter 104 Level detection circuit 105 Filter coefficient output circuit 106, 401, 402, 406, 307 to 312 Multiplier 301 to 306 Delay circuit 313, 314, 403, 404 Adder 405 Latch circuit 407 Reciprocal operation unit 601 Comparator 602 Switch 801 RAM 802 CPU 901 D / A output circuit 902 D / A converter 903 Variable attenuator

Claims (6)

[Claims] An automatic gain control circuit for compensating a gain of a received signal level to an expected signal level, comprising a digital filter for limiting a band, monitoring a demodulated output level of the digital filter, and adjusting a demodulated output level. An automatic gain control circuit characterized by realizing gain compensation by rewriting a filter coefficient of a digital filter every moment so as to have an expected level. 2. An A / D converter for digitally converting a reception signal of a QPSK wave composed of an intermediate frequency signal, a quadrature demodulator for quadrature detection of an output from the A / D converter, and an in-phase component and a quadrature component. A digital filter for performing a required band limitation on the detection output and demodulating and outputting, and a digital filter connected to the output of the digital filter and monitoring the level of the demodulated signal output from the digital filter, and when the average value of the demodulated signal level is constant. A level detection circuit for outputting data, a filter coefficient output circuit for outputting a filter coefficient, and a data output from the level detection circuit and a filter coefficient output from the filter coefficient output circuit.
A multiplier which sets the digital filter and updates the filter coefficient held in the filter coefficient output circuit. 3. The level detection circuit comprises: a first multiplier for squaring an input in-phase component, a second multiplier for squaring an input quadrature component, and an output of the first multiplier. A first adder for adding the outputs of the two multipliers; a second adder and a latch circuit for calculating an average value by adding the outputs of the first adder a fixed number of times; and the average value. 3. The automatic gain control circuit according to claim 2, further comprising: a third multiplier that normalizes the normalized value by a target value; and a reciprocal operation unit that performs reciprocal operation on the normalized value and outputs the result. 4. The level detection circuit comprises: a first multiplier for squaring the input in-phase component, a second multiplier for squaring the input quadrature component, and an output of the first multiplier. A first adder for adding the outputs of the two multipliers; a second adder and a latch circuit for calculating an average value by adding the outputs of the first adder a fixed number of times; and the average value. A third multiplier that normalizes the normalized value by a target value, a reciprocal calculator that performs reciprocal operation on the normalized value, and outputs the average value, and the average value is a value within an allowable range from the target value. A comparator for outputting a control signal, if any, and a switch for receiving a control signal from the comparator and ignoring an input from the reciprocal operation unit and outputting a value “1”. Item 3. The automatic gain control circuit according to Item 2. 5. An A / D converter for digitally converting a received signal of a QPSK wave comprising an intermediate frequency signal, a quadrature demodulator for performing quadrature detection on an output from the A / D converter, and an in-phase component and a quadrature component. A digital filter that performs a required band limitation on the detection output and demodulates and outputs, a RAM that is connected to the output of the digital filter and that holds a fixed number of data obtained from the digital filter by changing addresses and reading data in the RAM A CPU that outputs data so that the average value of the demodulated signal level is constant, a filter coefficient output circuit that outputs a filter coefficient, a filter that is output from the level detection circuit, and a filter that is output from the filter coefficient output circuit Multiply by the coefficient
A multiplier which sets the digital filter and updates the filter coefficient held in the filter coefficient output circuit. 6. A QPSK wave received signal is digitally converted, the digitally converted signal is subjected to quadrature detection, and a digital filter performs a required band limitation on a detection output composed of an in-phase component and a quadrature component, and demodulates the digital filter. An automatic gain control method comprising monitoring an output level and realizing gain compensation by rewriting a filter coefficient of a digital filter every moment so that a demodulated output level becomes an expected level.