JP2000285017A - Storage device - Google Patents

Abstract

(57) [Summary] An object of the present invention is to shorten the access time of a storage device using a flash memory. When data is written to a storage device using a flash memory, whether or not to perform interleaving is determined according to the amount of data to be written at a time, and writing is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device using a flash memory.

[0002]

2. Description of the Related Art In a storage device including a plurality of flash memories and a controller for controlling the flash memory, when writing and reading the data, a logical address constituted by a cylinder, a track, and a sector of the controller is converted into a controller by a conversion table. Corresponded to the physical address of the flash memory. This controller shortens the writing time to the flash memory by a method called interleaving. Interleaving is a method of writing continuous data not over continuous addresses of one flash memory but over a plurality of memories. For example, when writing 10 sectors of data, one sector consists of 512 bytes and 16 bytes of management information for the data, for a total of 528 bytes.
It is necessary to write 28 x 10 bytes of data to flash memory. When writing to the flash memory, 528 bytes of data are transferred to the flash memory chip and stored in a buffer inside the flash memory, and then a write command is issued to the flash memory to write the data to the flash memory. Assuming that the time required to transfer data to the flash memory chip is tT and the time required to write data to the flash memory is tW, the time required to write 10 sectors of data to one flash memory chip is 10 × (t
T + tW).

In interleaving, the first 528-byte data of the 10 528-byte data is written to the k-th flash memory chip, and the next 528-byte data is written to k + 1
The third 528-byte data is written to the k-th flash memory again.

In this manner, data transfer to the (k + 1) th flash memory chip can be started without waiting for the time until the writing of the 528-byte data to the k-th flash memory is completed. Therefore, the time required to write data for 10 sectors is 5 × (tT + tW) + tT. Generally t
Since T <tW, the interleave operation reduces the write time by about half compared to the case without interleave.

[0005]

However, when interleaving is performed for all write operations, there is a problem that the access time of the storage device is lengthened. For example, when an operation of rewriting data of only one sector in the storage device is performed, only data of 528 bytes should be rewritten. However, the flash memory performs writing in units of blocks composed of, for example, 528 × 16 = 8448 bytes. This is for the following reason. The flash memory cannot overwrite the currently written data, and erases and writes data once in units of 8448 bytes. 528 inside a block of 8448 bytes
When rewriting bytes, it is not possible to erase only 528 bytes out of 8448, so 84
Either erasing the same address area and writing again the 8448-byte data obtained by changing only 528 bytes of the 48-byte data, or writing to another erased area.
In any case, writing 8448 bytes (16 times 528 bytes) is required. Therefore, it takes 16 × (tT + tW) to write one block. This requires the same time when rewriting only one sector or rewriting data in a plurality of sectors.

For example, if writing of only two sectors is required, interleaving requires 16 × (tT + tW) + tT, but if interleaving is not performed, 16 × (tT + tW) + tT is required.
The writing ends at (tT + tW). On the other hand, when writing more than 16 sectors, interleaving is faster. When writing 17 sectors, it is necessary to write two blocks of 8448 bytes. If interleaving is not performed, it is necessary to rewrite 16 sector data of the first flash memory after rewriting 16 sector data of the second flash memory, so 2 × 16 × (tT + tW) -tW time is required It is. But with interleaving, 16x
Writing is possible at (tT + tW) + tT.

As described above, there are cases where the writing time is shortened and the writing time is delayed by performing the interleaving.

[0008]

According to a storage device of the present invention, in a storage device including a plurality of flash memory chips and a controller for controlling the flash memory chips, data to be written into a general storage device is written to consecutive addresses of the flash memory. There is a bit for determining whether the data is to be written to the flash memory or a plurality of flash memories alternately, and the writing method is switched according to the bit.

[0009]

FIG. 1 is a block diagram of the present invention. 101 is a controller, and the controller 101 temporarily stores necessary data by the CPU for processing the controller, the ROM for executing the processing program of the controller, and the CPU.
It comprises an address for reading and writing data from and to the RAM and flash memory, a data bus, and an interface for exchanging data with the outside of the storage device. Reference numerals 102 and 103 denote flash memories which are accessed by the controller 101. In this embodiment, the case where there are two flash memories is described, but any number of flash memories may be used as long as the number is two or more.

When a logical address of a storage device such as a cylinder, a track, and a sector and information to be written are given to the controller 101 from an external interface, the controller 101 uses the address conversion table in a part of the flash memory 102 to determine which area of the actual flash memory Determines whether to write data to

FIG. 2 shows this address conversion table.
When a cylinder, track, or sector is input to this address conversion table, the corresponding flash memory address is output. Write data to this address. The conversion table is defined for every 16 sectors (8448 bytes). The address translation table has a bit indicating whether to interleave. The controller 101 determines whether it is more advantageous to interleave based on the amount of data to be written at a time, and if so, sets a bit indicating interleaving in the conversion table and writes data across the flash memories 102 and 103.

FIG. 3 shows a method of writing data. Although the flash memory includes several blocks of 8448 units, data is written as shown in FIG. 3 using blocks located at the same position of the flash memories 102 and 103. The numbers in FIG. 3 indicate the order of writing data. The first data is written to the flash memory 102, and the second data is written to the flash memory 103. Similarly, odd-numbered data is written to the flash memory 102, and even-numbered data is written to the flash memory 103. When reading this data, a bit indicating the interleave in the address conversion table is read and the data is alternately read from the flash memories 102 and 103. If the amount of data to be written at a time is small, the bit indicating the interleave in the address conversion table is reset and data is continuously written to one flash memory as shown in FIG. When reading this data, continuous data is read by referring to the bit indicating the interleave in the address conversion table.

[0013]

As described above, the access speed can be increased by determining whether or not to perform interleaving based on the amount of data to be written at one time and writing the data into the flash memory.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram showing an embodiment of the present invention.

FIG. 2 is a diagram of an address conversion table.

FIG. 3 is a diagram of an example of data writing when interleaving is performed.

FIG. 4 is a diagram of an example of data writing when interleaving is not performed.

[Explanation of symbols]

 101 Controller 102 Flash memory 103 Flash memory

Claims (1)

[Claims] In a storage device comprising a plurality of flash memory chips and a controller for controlling the flash memory chips, data to be written to a general storage device is written to consecutive addresses of the flash memory or alternately written to a plurality of flash memories. A storage device that has a bit for determining whether to write data and switches a writing method according to the bit.