JP2000286683A - Multiplier circuit - Google Patents

Abstract

Abstract: PROBLEM TO BE SOLVED: To significantly reduce different delay time errors .DELTA.Td2 and .DELTA.Td3 generated in two of three variable pulse delay circuits used in an IC-based multiplier, thereby multiplying a clock. Provided is a multiplying circuit for ensuring operation accuracy. SOLUTION: A frequency-divided output signal of the first frequency-divided circuit 1 is delayed by a first frequency-divided circuit 1 for dividing an input clock signal by two and a delay control signal generated based on a reference current Io. Three pulse delay circuits 2 for outputting controlled delay signals,
In the multiplying circuit having the third and fourth circuits, the second frequency dividing circuit 12 for dividing the input clock signal by two and the volume 13 pass from the positive signal to the negative signal of the frequency-divided output of the second frequency dividing circuit 12. To generate a voltage signal ΔV2 whose amplitude is set, and a current signal ΔI2 correlated with this voltage signal ΔV2.
Is generated by the voltage-current conversion circuit 14, and the current signal ΔI2 is added to the reference current Io by the current addition circuit 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplier for generating a pulse signal (clock signal) delayed from an input pulse signal (input clock signal).

[0002]

2. Description of the Related Art (Outline of Operation of Conventional Multiplier) FIG. 4 shows a conventional example of a multiplier which outputs a double clock signal to an input clock signal. FIG. 5 is a time chart showing the operation of the frequency multiplier. Since the clock duty of the input clock signal (waveform of FIG. 5A) is not normally guaranteed, the frequency divider 1 removes an uncertain clock duty component (waveform of FIG. 5B).

A reset signal is input to a frequency dividing circuit 1 on the assumption that an input clock signal is a synchronous clock signal. The output of the frequency divider 1 is input to the input terminals of the variable pulse delay circuit 2 and EXOR (exclusive OR circuit) 5. The variable pulse delay circuit 2 outputs a pulse signal delayed by time Td1 and Td1 'with respect to the ↑ edge (rising edge) and ↓ edge (falling edge) of the input signal, respectively (waveform c in FIG. 5).

The output of the variable pulse delay circuit 2 is a variable pulse delay circuit 3 having the same configuration as that of the variable pulse delay circuit 2 and EX.
It is input to the input terminal of OR6. Variable pulse delay circuit 3
Outputs a pulse signal delayed by Td2 and Td2 'each time with respect to the ↑ and エ ッ ジ edges of the output signal of the variable pulse delay circuit 2 (d waveform in FIG. 5).

[0005] The output of the variable pulse delay circuit 3 is a variable pulse delay circuit 4 having the same configuration as the variable pulse delay circuit 2 and EX.
It is input to the input terminal of OR5. Variable pulse delay circuit 4
Outputs a pulse signal delayed by times Td3 and Td3 'with respect to the ↑ and エ ッ ジ edges of the output signal of the variable pulse delay circuit 3 (waveform e in FIG. 5). The output of the variable pulse delay circuit 4 is input to the input terminal of the EXOR 6.

The same delay control current Id is input to the variable pulse delay circuits 2 to 4, so that the pulse delay times are equal, and the delay times Td1 = Td1 'and Td2 =
It is assumed that the relationship of Td2 ′, Td3 = Td3 ′ holds, and that the delay control current Id is controlled such that each delay time is １ ／ To the input clock period To.
At this time, the outputs of EXOR5 and EXOR6 are respectively shown in FIG.
As shown in FIG. 5F and FIG. 5G, the clock duty is reproduced, and clock signals having different quarter-phases are created.

The output of EXOR5 and EXOR6 is EXO
R7, and the output of this EXOR7 includes h in FIG.
As shown in (2), a double clock signal whose clock duty is secured is output as an output signal. If this multiplied clock signal is used, even if a general logic circuit is used, 1
Various controls with / 4To accuracy can be performed. For example, clock phase control including a frequency-divided clock signal, and 3/4 (multiplication), 5/4, 3/2, 7/4, 9/4, 5/2, 11
/ 4. . . . It is possible to easily create an accurate divided clock such as.

The operation described above is guaranteed immediately from the clock input even for a synchronous clock whose phase changes instantaneously as an input clock signal.

(Explanation of the variable pulse delay circuit) What is important in realizing this operation is the operation of the variable pulse delay circuits 2 to 4, which will be described below. FIG.
FIG. 7 is a time chart showing the operation of this variable pulse delay circuit.

With respect to the emitter size and resistance of the transistor, Q1b = Q2b, Q3b = Q4b, Q5b =
Q6b, Q7b = Q8b, Q9b = Q10b, Q11b
= Q12b, Q13b = Q14b, Q15b = Q16
b, R1b = R2b, R3b = R4b, R5b = R6
b, R7b = R8b, R7b = R8b, and voltage Vp =
R1b · I1b, and the base-emitter voltage of the transistor is Vbe. The delay control current Iz becomes the delay drive current Id via the current AMP (amplifier) 6, and is input to the emitter couple including the transistors Q1b and Q2b. The current AMP6 corresponds to the currents AMP1 to AMP in FIG.
This is shown as P3.

The differential input signals pVi and nVi input to the bases of the transistors Q1b and Q2b are indeterminate of the input clock signal (the waveform of FIG. 7a) as shown in FIG. 7b (pVi). This is a pulse signal from which the duty component has been removed.

Now, pVi before time t0 is at L level,
Transistor Q8b is ON (transistor Q7b is OF
F), the transistor Q1b is ON, and the voltage at the point B is (Vcc-2Vbe). Also,
At this time, it is assumed that the transistor Q2b is off and the voltage at the point A is fixed at (Vcc-2Vbe + Vp).

The bold waveform in FIG. 7c shows the signal waveform at point A, the thin waveform shows the signal waveform at point B, and the d waveform in FIG. 7 shows the output signal pVo1. At time t0, when the input pulse signal pVi goes to the H (high) level, the transistor Q
2b is turned on and a discharge current is supplied to the capacitor (capacitor) C1b, so that the voltage at the point A starts to drop while the voltage at the point B remains fixed.

At time t1, when the voltage at point A drops to (Vcc-2Vbe-Vp), current starts to flow through transistor Q4b, and transistor Q8b rapidly turns on (transistor Q7b turns off rapidly). Therefore, the output pulse signal pVo1 becomes H level (nVo is L level). The point A becomes (Vcc-2Vbe), and the point B
The point becomes (Vcc-2Vbe + Vp). N at time t2
When Vo1 becomes H level, the transistor Q1b is turned on.
Then, in order to supply a discharge current to the capacitor C1b, the voltage at the point A starts to drop while the voltage at the point A remains fixed.

At time t3 when the voltage at the point B drops to (Vcc-2Vbe-vp), a current starts to flow through the transistor Q3b, and the transistor Q7b rapidly turns ON (the transistor Q8b rapidly turns OFF). Therefore, the output pulse signal pVo1 is at the L (low) level (nVo is at the H level). The point B becomes (Vcc-2Vbe), and the point A becomes (Vcc-2Vbe + Vp). This state is the same as the assumption in the state before time t0, and thereafter, the same operation as described above is repeated according to the level change of the input signal pVi / nVi. As can be understood from the waveform of FIG. 7D, the output signal pVo1 / nVo1 is equal to the ↓ edge and the ↑ edge of the input signal pVi / nVi, and is a pulse signal delayed by the time Td.

The variable pulse delay circuit of FIG. 6 is provided with another pair of output signals pVo2 / nVo2. These output signals have an H level of (Vcc) so that the transistors Q1b and Q2b do not become saturated when a plurality of variable pulse delay circuits are connected in series as in the example of the multiplier circuit of FIG. This is because it is necessary to prepare a signal of (−2Vbe−Vs).

The level shift voltage Vs is equal to the resistance R4b / R6
When the output signal amplitude Vp is 0.5 V and the level shift voltage Vs is set to about 0.3 V, for example, the collector-emitter voltage Vce of the transistor Q1b and the transistor Q2b becomes high even at a high temperature. 0.3
V or more, and does not fall into a problematic saturated state. The variable pulse delay circuit 2 to which the output of the frequency dividing circuit 1 is input performs the same level shift in the frequency dividing circuit 1 shown in FIG.

The frequency dividing circuit shown in FIG. 9 has a general configuration, and a description thereof will be omitted. However, the resistance value and the constant current value are R1c = R2c =
R3c = R4c = R1b, I1c = I1b, R5c = R
By setting 6c = R3b, R7c = R8c = R5b, and inputting the same bias voltage VB,
The frequency dividing function is realized, and the output differential signal pVo2 / nVo2 is input to the variable pulse delay circuit 2. The pulse delay time Td in the variable pulse delay circuit can be expressed by the following equation (1), assuming that the delay drive current Id is DC with respect to the input pulse signal period.

[0019]

Td = C1b · 2Vp / Id (1) Vp = R1b · I1b (Description of Pulse Delay Control) In the above equation (1) for determining the pulse delay time Td, a circuit is formed on an IC (integrated circuit). In such a case, the capacitance C1b in FIG. 6 must take into account the absolute value variation ± 30%. For this reason, a circuit for controlling the pulse delay time Td is provided in the multiplier circuit of FIG. That is, the output of the EXOR 5 is input to the charge pump 8, and the delay error voltage signal ΔV
Outputs 1. The charge pump 8 has a configuration as shown in FIG. 8, and a constant current I1g is supplied to the emitter couples of the transistors Q1g and Q2g.
EXO at the base of transistor g (base of transistor Q2g)
A negative signal nVi (positive signal pVi) of the differential output of R5 is input, a constant current 0.5I1g and an appropriate capacitor C1g are connected to the collector of the transistor Q1g, and an error voltage signal ΔV1 is output. The error voltage signal ΔV1 is variable g
m amplifier (amplifier) 9 and receives an error current signal ΔI1
Is output. The variable gm amplifier 9 receives the reference current Io as k2 · Io via the current AMP5. The error current signal ΔI1 is expressed by the following equation (2).
It can be represented by the function of V1.

[0020]

ΔI1 = k2 · Io · k3 · f (ΔV1) (2) where k3 is a positive constant equal to or less than 1, and k2 is a coefficient f (ΔV1) increases and changes in the range of −1 to +1 as ΔV1 increases. The function reference current Io is input to the current addition circuit 10 by adding k1 · Io via the current AMP4, where it is added to the error current signal ΔI1 to output a delay control current Iz represented by the following equation (3). k1 is a coefficient.

[0021]

Iz = k1 · Io + ΔI1 Iz = k1 · Io (1+ (k2 · k3 / k1) · f (ΔV1)) (3) The delay control current Iz has the same configuration as the current AMP1 and the current AM.
P2, and becomes the delay drive current Id via the current AMP3 and is input to the variable pulse delay circuits 2 to 4.

The error voltage signal ΔV1, which is the output signal of the charge pump 8, can be balanced only when the duty of the output pulse signal of the EXOR 5 is balanced. If the delay amount of the variable pulse delay circuits 2 to 4 is too large (or too small), the error voltage signal ΔV1 rises (or falls if it is too small), and the delay control current is obtained from the above equations (2) and (3). Iz (the delay drive current Id) is increased (if it is too small, it is decreased), and the delay time Td is reduced (if it is too small, it is increased).

With the above operation, the delay time Td is reduced to a desired quarter.
Converge to To. Note that the coefficient (k2 ·
k3 / k1) is set to about ± 1/2 (± 50%) corresponding to the element variation including the internal capacitance.

[0024]

However, the above-described variable pulse delay circuit has the following problems which cannot be avoided in the IC configuration.

In the variable pulse delay circuit shown in FIG. 6, resistors R3b / R4b and R5b / determine the level shift balance of the output signal pVo2 / nVo2 for connection to the next stage.
As shown in FIG. 6, the resistance diffusion regions of R6b cannot be formed in the same region. For this reason, the IC component layout must be constituted by a diffusion region in which all the resistances related to the level shift balance are divided in order to satisfy the AC characteristics. In this component layout, even in an IC circuit which is generally considered to have high component relative accuracy, it is not possible to ensure a state in which resistance relative accuracy is good. Moreover, this level shift error causes a delay error from the timing ↑ and the timing ↓ in the pulse delay operation. The respective delay errors of the respective delay outputs of the variable pulse delay circuits 2 to 4 are represented by ΔTd1 to ΔTd.
If it is 3, it is shown as the following equations (4), (5) and (6).

[0026]

ΔTd1 = Td1−Td1 ′ Almost = 0 (4)

[0027]

ΔTd2 = (Td1 + Td2) − (Td1 ′ + Td2 ′) (5)

[0028]

ΔTd3 = (Td1 + Td2 + Td3) − (Td1 ′ + Td2 ′ + Td3 ′) Almost = 2ΔTd2 (6) Only the input of the variable pulse delay circuit 2 uses the level shift circuit in the frequency dividing circuit 1. As shown in FIG. 9, since the resistance pairs related to the level shift balance can all be laid out in the same diffusion region, the delay error ΔTd1 is very small. Since the variable pulse delay circuits are arranged side by side with the same configuration on the IC, ΔTd3 is about twice as large as ΔTd2 considering that ΔTd1 is minute. When the above-described clock generation control is performed from the multiplied output signal configured as described above, the period fluctuation and the duty fluctuation of the generated clock signal are caused, and this becomes more remarkable as the clock period becomes shorter.

FIG. 10 shows a conventional correction circuit for reducing this delay error. The clock input is connected to the clock input of the D-type flip-flop DFF1 and divided by two,
A reset signal is connected to the reset input. A volume (variable resistor) VR2 is connected to the Q and NQ outputs of the D-type flip-flop DFF1, so that the level-divided clock signal is output while setting the level from the positive electrode to the negative electrode, The output signal and the clock input are added by appropriate resistors Rx3 and Rx4, and input as a clock output to the multiplication circuit of FIG. With such a configuration, the clock output can be periodically fluctuated by the volume VR2.

However, since the delay errors ΔTd1 to ΔTd3 are all different, the correction circuit shown in FIG. 10 is not so effective.

The present invention has been made in view of the above points, and has as its object to provide different delays generated in two of three variable pulse delay circuits used in an IC-based multiplier circuit. It is an object of the present invention to provide a multiplying circuit in which the time errors ΔTd2 and ΔTd3 are greatly reduced and the accuracy of the clock multiplying operation is ensured.

[0032]

In order to achieve the above object, according to the present invention, a first frequency dividing circuit for dividing an input clock signal by two and a second frequency dividing circuit for dividing the input clock signal by two are provided. A voltage signal generating circuit for generating a voltage signal for delay balance correction having an amplitude set from a positive signal to a negative signal of a divided output of the second frequency dividing circuit; A voltage-current conversion circuit that generates a current signal having a correlation with a signal; a current addition circuit that adds the current signal to a reference current; and a first frequency division circuit that uses an output of the current addition circuit as a new reference current. A pulse delay circuit that outputs three delayed signals obtained by delay-controlling the frequency-divided output signal; and a multiplied signal generating circuit that generates a multiplied signal of the input clock signal based on the three delayed signals. And

Here, the voltage signal generating circuit may be a volume for generating the voltage signal by connecting both ends to a positive output and a negative output of the second frequency dividing circuit.

The voltage-current conversion circuit may be a time constant circuit composed of a resistor and a capacitor.

Further, a circuit portion comprising the second frequency dividing circuit, the electric signal generating circuit, the voltage / current converting circuit and the current adding circuit can be externally connected to an IC constituting the multiplying circuit. It can be characterized.

(Operation) In the present invention, the first frequency dividing circuit (1) for dividing the frequency of the input clock signal by two and the delay control signal generated based on the reference current Io are used for the first frequency dividing circuit. A frequency divider having three pulse delay circuits (2, 3, 4) for outputting a delay signal obtained by delay-controlling the frequency-divided output signal of (1), a second frequency divider for dividing the input clock signal by 2 (12) and the volume 13 generate a voltage signal ΔV2 whose amplitude is set from the positive signal of the frequency-divided output of the second frequency dividing circuit (12) to the negative signal, and have a correlation with the voltage signal ΔV2. A certain current signal ΔI2 is generated by a voltage-to-current conversion circuit (14), and a current addition circuit (15)
To add the current signal ΔI2 to the reference current Io.

[0037]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Configuration of Multiplier Circuit of the Present Invention) FIG. 1 shows a configuration of a multiplier circuit according to an embodiment of the present invention. The difference between the frequency multiplier using the present invention shown in FIG. 1 and the conventional frequency multiplier shown in FIG. 4 will be described.

In FIG. 1, 12 is a frequency dividing circuit, 13 is a volume (variable resistor), 14 is a voltage-to-current converting circuit,
Reference numeral 5 denotes a current addition circuit, which is a circuit element added to the conventional multiplication circuit to achieve the present invention, and the other configuration is the same as that of the conventional circuit of FIG.

The clock signal and the reset signal are inputted to the conventional first frequency dividing circuit 1 and also inputted to the second frequency dividing circuit 12, which constitutes the present invention, and are divided by two. The positive output PQ and the negative output NQ of the frequency dividing circuit 12 are connected by a volume 13 to generate a voltage signal ΔV2 for delay balance correction. The voltage signal ΔV2 is input to the voltage-to-current conversion circuit 14 and converted into a current signal ΔI2. The current signal ΔI2 is input to the current addition circuit 15 together with the reference current Io, and the added current output from the current addition circuit 15 is The reference current (Io + ΔI2) is input to the currents AMP4 and AMP5 of the multiplier circuit having the same configuration as that of the conventional example of FIG.

FIG. 2 shows an actual circuit configuration according to the present embodiment up to generation of the delay control current Iz 'corresponding to the circuit of FIG. Here, the voltage VBa is a band gap voltage (up to 1.26 V), and is a voltage that is stable with respect to the environment (Vcc and Td). The reference current Io is VBa / Ro1.

The voltage signal ΔV2 generated by the frequency dividing circuit 12 and the volume 13 in FIG. 1 passes through a time constant circuit which is sufficiently large with respect to the clock cycle constituted by the resistor Rx1 and the capacitor Cx1, and has a phase delay. The signal is converted into a triangular wave voltage signal, and is connected to a reference current input terminal via a resistor Rx2. As a result, the current signal ΔI is supplied to the resistor Ro1.
2 is generated, and a new reference current Io ′ = Io + ΔI2 is supplied to an IC (multiplier circuit) having the same configuration as that of the related art surrounded by a broken line frame.

The addition current Iz of the current k1 · Io ′ and the error current signal ΔI1 is converted into three transistors Q9a, Q10a,
The delay control current Iz 'is generated by inputting the current to the Wilson-type current buffer composed of Q11a, and the delay control current Iz' is supplied to each variable pulse delay circuit.

Since the Wilson-type current buffer has the capacitance C1a, the current feedback operation does not sufficiently respond to a high-frequency signal such as the current signal ΔI2, so that the current signal ΔI2 component is sufficiently close to a sine wave. -9
A phase lead of less than 0 ° occurs, thereby correcting the phase lag of the current signal ΔI2 with respect to the voltage signal ΔV2 due to the time constant (Rx1 · Cx1) of the time constant circuit.

By appropriately setting the value of the resistor Rx2, the current signal Δ
The phase of the I2 component can be changed from outside the IC.

(Operation for Correcting Delay Time Balance) The current signal ΔI2 when the phase of the current signal ΔI2 component is set to + 45 ° with respect to the variable pulse delay operation cycle in the multiplier circuit.
The components are shown in FIG. Here, the horizontal axis represents the variable pulse delay operation period, which is normalized by the clock period To. The vertical axis indicates the current signal ΔI2 component, the thick line curve indicates the odd clock cycle, the thin line curve indicates the even clock cycle, and the amplitude set by the volume VR1 (volume 13 in FIG. 1) is normalized. is there. That is, the current signal Δ
The I2 component can be expressed by the following equation (7) by using a function x that becomes 2π in the period 2To.

[0047]

The current signal ΔI2 component = SIN (x−π / 16) (7) From the following equation (7), the odd clock cycle and the even clock cycle become substantially symmetric as shown in FIG. Is self-evident. Since the delay time Td of the variable pulse delay circuit is determined by the integral value of the drive current Id during the delay operation period, the current signal ΔI2 component included in the drive current Id includes the delay time Td of the odd clock cycle and the even clock. The cycle delay time Td ′ can be changed.

Next, the integrated value of the current signal ΔI2 component supplied during each delay operation period of the variable pulse delay circuits 2 to 4 in FIG. 1 will be calculated.

[0049]

(Equation 8)

From the above, the following can be understood.

1) The delay time error ΔTd1 between the odd clock cycle and the even clock cycle does not affect the variable pulse delay circuit 2.

2) The current signal ΔI2 components supplied to the variable pulse delay circuits 3 and 4 have a relationship of approximately 1: 2.
Accordingly, the delay time errors ΔTd2 and ΔTd3 between the odd clock cycle and the even clock cycle of the variable pulse delay circuit 3 and the variable pulse delay circuit 4 can be substantially corrected by considering the above equation (6).

The voltage-to-current conversion circuit 14 and the current addition circuit 15 for realizing the operation described above are very small, as can be seen from FIG. Even if included, the circuit of the present embodiment added to the multiplier circuit can be realized at a low cost with a simple configuration.

[0054]

As described above, according to the present invention, I
Of the three variable pulse delay circuits used in the C multiplication circuit, two different delay time errors ΔTd2 and ΔTd3 generated by two are added by one adjustment circuit having a simple configuration added from outside the IC. This has the effect of greatly reducing the frequency and ensuring the accuracy of the clock multiplication operation.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a multiplying circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a real circuit configuration in the present embodiment up to generation of a delay control current Iz ′ corresponding to the circuit of FIG. 1;

FIG. 3 is a graph showing the current signal ΔI2 component when the phase of the current signal ΔI2 component in FIG. 1 is set to + 45 ° with respect to the variable pulse delay operation cycle in the multiplier.

FIG. 4 is a block diagram showing a configuration of a conventional frequency multiplier.

FIG. 5 is a time chart illustrating a basic operation of the multiplying circuit of FIG. 4;

FIG. 6 is a circuit diagram showing a configuration of a variable pulse delay circuit used in the multiplier circuit of FIG. 4;

FIG. 7 is a time chart illustrating an operation of the variable pulse delay circuit of FIG. 6;

8 is a circuit diagram showing a configuration of a charge pump circuit used for delay time control of FIG.

FIG. 9 is a circuit diagram showing a configuration of a conventional clock divide-by-2 circuit.

FIG. 10 is a circuit diagram showing a configuration of a conventional delay time error correction circuit.

[Explanation of symbols]

 1, 12 divider circuit 2, 3, 4 variable pulse delay circuit 5, 6, 7 EXOR circuit 8 charge pump 9 variable gm amplifier 10, 15 current addition circuit 13 volume 14 voltage → current conversion circuit AMP1-AMP6 current amplifier (amplifier)

Continuation of the front page (72) Inventor Yuya Ebata 3-30-2 Shimomaruko, Ota-ku, Tokyo F-term in Canon Inc. (reference) 5J039 AC03 AC16 AC23 KK09 KK11 KK13 KK27 MM06 MM16

Claims (4)

[Claims] A first frequency divider for dividing the input clock signal by two; a second frequency divider for dividing the input clock signal by two; and a frequency divider output of the second frequency divider. A voltage signal generation circuit for generating a voltage signal for delay balance correction having an amplitude set from the positive signal to the negative signal, a voltage-current conversion circuit for generating a current signal correlated with the voltage signal, and the current A current adding circuit for adding a signal to a reference current, and using the output of the current adding circuit as a new reference current,
A pulse delay circuit that outputs three delayed signals obtained by delay-controlling the frequency-divided output signal of the frequency divider circuit; and a multiplied signal generation circuit that generates a multiplied signal of the input clock signal based on the three delayed signals. A multiplying circuit, comprising: 2. The voltage signal generating circuit according to claim 1, wherein the voltage signal generating circuit is a volume for generating the voltage signal by connecting both ends to a positive output and a negative output of the second frequency dividing circuit. Multiplication circuit. 3. The multiplication circuit according to claim 1, wherein the voltage-current conversion circuit is a time constant circuit including a resistor and a capacitor. 4. A circuit portion comprising the second frequency dividing circuit, the electric signal generating circuit, the voltage-current converting circuit and the current adding circuit can be externally connected to an IC constituting the multiplying circuit. The multiplying circuit according to claim 1, wherein: