JP2000292502A - Semiconductor device test apparatus and semiconductor device test method - Google Patents

Abstract

(57) Abstract: An object of the present invention is to provide an IC tester capable of suppressing ringing caused by multiple reflection of a response waveform from a DUT on a transmission path between the DUT and pin electronics. A transmission path is connected between a transmission path and an input terminal of a comparator, and is turned on in response to a change in a response waveform from a high level to a low level, to provide an impedance substantially equal to the characteristic impedance of the transmission path to the transmission path. A first switch circuit to be connected, and a low-level to a high-level response waveform connected between the transmission path and the input end of the comparator.
a second switch circuit that is turned on in response to a change to the high level and connects an impedance substantially equal to the characteristic impedance of the transmission line to the transmission line, and a low-level response waveform connected to the first switch circuit to change the response waveform A first voltage generating circuit for generating a voltage for clamping with
And a second voltage generation circuit for generating a voltage for clamping the response waveform at a certain High level.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD OF THE INVENTION

[0001] The present invention relates to a semiconductor device test apparatus (hereinafter referred to as I
C tester) and a semiconductor device test method (hereinafter referred to as an IC test method). More specifically, ringing due to multiple reflection generated between pin electronics and a semiconductor device under test (hereinafter referred to as a DUT) connected via a transmission line is described. IC that can suppress and obtain good test waveforms
About testers.

[0002]

2. Description of the Related Art In an IC tester, a predetermined terminal is driven by a preset voltage, and after a predetermined time, a waveform of a signal output from an output terminal (or an input / output terminal, hereinafter the same) of a DUT has a High level. (Hereinafter "H")
Or a low level (hereinafter, “L”) is determined by a determination circuit in accordance with a strobe signal generated at a predetermined timing (hereinafter, a determination mode), and is compared with an expected value to perform an operation test or a performance test of the DUT. I do.

At present, the operating clock of the DUT has a frequency in a high-frequency range, and its output waveform is also high-frequency. The terminals of the IC tester and the DUT are connected by a transmission line such as a coaxial cable. You. Therefore, a reflected wave is generated between the power supply side and the power receiving side, which is a problem as a high-frequency circuit, and ringing occurs in the waveform. This is particularly problematic when the output waveform is determined on the IC tester side without terminating the line with matching impedance in the transmission line receiving the output waveform obtained from the output terminal of the DUT. This is because a waveform distortion occurs due to a reflected wave due to a mismatch between the output impedance of the DUT and the transmission line. In a conventional IC tester, in a pin electronics for connecting a TTL or CMOS device to an input / output terminal (I / O terminal) of a DUT without using a terminating resistor designed on the assumption that a transmission line is not driven, a DUT is used. As a measure to prevent a ringing waveform due to multiple reflection of a response waveform due to an output from a computer, 45th of IEICE Communication Technical Report ICD92-121 (1992)
As described in Item 50 to Item 50, the ringing is removed by injecting a current from a load current injection circuit (dynamic load) provided as a standard feature on the tester side to the load side (DUT side), whereby the response is reduced. An erroneous level determination by an analog comparator that determines the level of the output waveform in the tester side determination circuit based on the ringing waveform of the waveform is prevented.

FIG. 9 is an explanatory diagram of a reflection diagram for explaining the principle of the occurrence of multiple reflection and ringing in this type of IC tester and a response waveform from the DUT. FIG. 9A is a reflection diagram, in which the horizontal axis represents the current I and the vertical axis represents the voltage V. FIG. 9B is an explanatory diagram of an input waveform (DUT response waveform) at the analog comparator input terminal for determining the level of the output waveform. FIG.
In (a), the input resistance of the comparator is very high, as shown by the graph 100.
Since it is from kΩ to several tens MΩ, the current / voltage characteristics here are along the vertical axis for convenience. On the other hand, the characteristic impedance Zo of a transmission line such as a coaxial cable is 50Ω as a standard value as shown by 101, and the current / voltage characteristic becomes a tilted graph 101. In recent years, the output resistance of a DUT whose impedance has been reduced in recent years has been about several Ω to several tens of Ω.
If the output of T shifts from “H” to “L”, the current / voltage characteristics are as shown in a graph 102.

The change in the output voltage from "H" to "L" of the DUT is the characteristic impedance of the transmission line from the H point of the voltage "H" at the input end of the comparator after receiving the first reflected wave. The point of intersection between the characteristic graph 101 and the output characteristic graph 102 of the DUT is reached, and the next reflected wave reaches the point of intersection with the input characteristic graph 100 of the comparator.
Further, the output characteristic graph 1 of the DUT is passed through a graph parallel to the characteristic impedance characteristic graph 101 by the next reflected wave.
02, and as a result, H ----
Eventually, after reaching the point L at the input end of the comparator through the order of −−, it will settle to the point L of “L”. This is the time on the horizontal axis,
When the voltage is plotted on the vertical axis, as shown in FIG. 9B, the input waveform of the comparator becomes a waveform that rings due to the reflected wave.

An analog comparator which determines the level of an output waveform in an IC tester-side determination circuit receiving such a response waveform has a low level determination voltage as shown in FIG.
It is assumed that the level is indicated by a dotted line 103 in FIG. The determination voltage 103 is, for example, 0.4 V in the case of a memory such as a DRAM. The output “L” of the DUT such as logic is almost 0V. Therefore, the response waveform 104 at the input terminal of the DUT comparator exceeds the voltage level 103 for the Low level determination in the state of FIG. 9B. If the comparator makes a Low level determination at this time, an erroneous determination is made.

In order to avoid such a situation, a current value predetermined according to the output waveform of "H" or "L" is applied to a specific output terminal, for example, as a current injection from the dynamic load. A load current of about several tens mA to several tens mA is supplied from a constant current source to make a determination in the determination mode. However, this dynamic load is originally provided in the IC tester to simulate the load of the device under test during the test, and therefore, the load current is applied to the output terminal of the DUT in the judgment mode using the comparator. Supply. The load current at this time is different from the current value for the ringing prevention operation. Therefore, the dynamic load cannot perform both the operation of the device under test as a pseudo load and the operation of preventing ringing, and is limited to only one of the operations. This load current supply circuit (dynamic load) is normally connected to an output terminal on the transmission line side of a driver or an input terminal of a comparator via an internal diode switch.
The diode switch is generally configured by a diode bridge, and controls supply of a load current by turning on / off a diode according to the output of “H” and “L” at an output terminal. In this connection, the diode switch is turned off in modes other than the determination mode.

[0008]

SUMMARY OF THE INVENTION Such TTL,
In non-terminated pin electronics such as CMOS, the response waveform from the DUT is received via the transmission line to determine the state of the waveform. When input to the comparator, which is the determination circuit, multiple reflections occur. However, if a current for preventing ringing is not properly injected from the dynamic load, the ringing due to multiple reflection may exceed the comparison level of the comparator and cause erroneous judgment.
On the other hand, the conventional technology of the dynamic load uses the dynamic load composed of the diode bridge and the constant current source as described above. Therefore, in the determination mode, even when the current is not injected to the DUT (load) side, always,
Power will be consumed inside the dynamic load.

In the case of using a diode bridge, in order to satisfy the condition of leakage current, it is necessary to use an element having a small leakage current for the diode.
For this reason, in the conventional IC tester, the diode switch portion of the dynamic load (load current output circuit) must be provided as a discrete circuit. In addition, there is a problem that an IC tester becomes large by providing a discrete circuit because many pin electronics circuits are used. In addition, if the diode switch is composed of a discrete circuit, the wiring length of the path between the diode switch (diode bridge) and the buffer circuit becomes longer, so that when the frequency of the output signal increases, a high-speed response cannot be performed. High precision measurement is not possible.

By the way, in a standard IC tester, if the characteristic impedance of the transmission line is 50Ω, the output amplitude of the DUT is 5V, and the output impedance is 10Ω, the first undershoot of the ringing shown in FIG. Is close to 4V. The injection current value from the dynamic load to cancel this is 80 m
A and very large. Therefore, when a diode bridge is used, the power consumption of the IC tester as a whole increases, and the device generates a large amount of heat. This also causes a problem in a highly accurate test. SUMMARY OF THE INVENTION An object of the present invention is to solve such a problem of the prior art.
It is an object of the present invention to provide an IC tester capable of suppressing ringing caused by multiple reflection in a transmission path between a pin and a pin electronics. It is another object of the present invention to provide an IC test method capable of suppressing ringing caused by multiple reflection of a response waveform from a DUT on a transmission path between the DUT and pin electronics.

[0011]

A feature of the IC tester of the present invention for achieving the above object is that the response test circuit is connected between the transmission path and the input terminal of the comparator and has a response waveform Hi.
a first switch circuit that is turned on in response to a change from the gh level to the Low level and connects to the transmission line an impedance substantially equal to the characteristic impedance of the transmission line;
A second circuit which is connected between the transmission path and the input terminal of the comparator, is turned on in response to a change in response waveform from a low level to a high level, and connects an impedance substantially equal to the characteristic impedance of the transmission path to the transmission path. , A first voltage generating circuit connected to the first switch circuit to generate a voltage for clamping the response waveform at a certain Low level, and a high voltage connected to the second switch circuit and changing the response waveform to a certain High level. And a second voltage generating circuit for generating a voltage for clamping.

In particular, the first and second switch circuits are connected to a transmission line by turning on the transistor as a transistor configuration. In this case, the impedance substantially equal to the characteristic impedance of the transmission line is equal to that of the transistor. The multiple reflection of the response waveform is suppressed by its internal impedance on the output side. Another feature of the IC test method of the present invention for achieving the other object is that the IC test method is connected between the transmission path and the input terminal of the comparator, and responds to the change of the response waveform from the high level to the low level. The first switch circuit is turned on to connect an impedance substantially equal to the characteristic impedance of the transmission path, and is connected between the transmission path and the input end of the comparator in response to a change in the response waveform from a low level to a high level. The second switch circuit is turned on to connect an impedance substantially equal to the characteristic impedance of the transmission line, and when the response waveform falls below a certain Low level, the response waveform is clamped to a certain Low level, and the response waveform is clamped. The response waveform is clamped to a certain High level when the waveform exceeds a certain High level or higher. .

As described above, for example, a transistor circuit is provided as a switch circuit that is turned on in response to a change from a High level to a Low level of a response waveform or vice versa, and the output of the transistor when turned on is provided. By connecting the internal impedance of the transmission side to the transmission line, for example, the impedance between the collector and the emitter or the impedance obtained by adding this impedance and a resistance value such as a resistor connected in series to the transmission line is equivalent to providing a terminating resistor. Can be a circuit. Thereby, multiple reflection of the response waveform can be suppressed. Furthermore, Hi
The transmission lines are turned on by using the transistors turned on at each of the gh level and the low level, and the transmission paths are respectively set to a certain high level or a certain low level by the voltage of the voltage generation circuit.
When the level is exceeded, a certain High level or a certain L
By voltage clamping to the ow level, reflected waves can be absorbed and ringing can be suppressed.

As a result, since the response waveform becomes accurate, it is possible to eliminate erroneous determination of the comparator for determining the level of the output waveform. Further, accurate timing measurement of a response waveform from the DUT can be performed. Further, since no current flows except when the reflected wave is absorbed, power consumption can be reduced. This allows for highly accurate waveform determination,
In this case, it is not necessary to use a diode bridge that operates at a high speed, so that the leakage current is small, switching control is not required, and the circuit can be simplified and the control is simplified. In addition, there is an advantage that the IC can be easily formed.

In particular, as a multiple reflection suppressing circuit near the input terminal of the analog comparator in the pin electronics,
The first and second voltage generating circuits each including a resistor, the first and second transistors, and a variable voltage source are provided. The resistance of the multiple reflection suppressing circuit and the O
The combined resistance value of the N resistor and the pin electronics and DU
It is preferable that the characteristic impedance is substantially equal to the characteristic impedance of the transmission line connecting between T. By setting the voltage level of the variable voltage source of the multiple reflection suppressing circuit to a level at which the level of the transmission line on the comparator connection side is substantially equal to the “L” or “H” voltage of the DUT, By matching only the voltage components, multiple reflections can be prevented.

[0016]

FIG. 3 is an overall configuration diagram of an IC tester having a multiple reflection suppressing circuit according to the present invention. In FIG. 3, a pin electronics 1 receives a test waveform signal 9a from a test signal generation / judgment unit 2 by a driver 10, and the driver 10 outputs the driver output via a transmission path 14 of a coaxial cable to DUTs 151, 152, 153, and the like. Add to After a predetermined time, for example, the analog comparator 11 receives the response waveform 15 a (output waveform) from the DUT 151 via the transmission line 14 and determines the level of the waveform.
(Hereinafter, comparator 11). In this circuit, a multiple reflection suppressing circuit 13 is connected to a connection point between the driver output and the transmission line 14. The test signal generation / determination unit 2 includes a control computer (or MPU) 3, a reference signal generator 4, a timing generator 5,
A pattern generator 6, a fail bit memory 7, a digital comparator 8, a waveform formatter 9, a reference voltage generator 12, a monitor, a printer, and the like are provided.

The reference signal generator 4 receives the signal 16a from the tester bus 16 and generates a reference clock 4a which is a time reference for a test waveform set by the signal 16a. The timing generator 5 receives the signal 16b from the tester bus 16 and further receives the reference clock 4a to receive the timing setting signal 16b.
b, the reference clock 4a is counted, and phase clock signals (hereinafter referred to as phase signals) 5a, 5
b, 5c are generated. The pattern generator 6 receives the signal 16c from the tester bus 16 and generates a pattern data signal 6a according to the timing of the phase signal 5b from the timing generator 5. The waveform formatter 9 generates a test waveform signal 9a for testing the DUT 15 (representing the DUTs 151, 152 and 153) by logic synthesis of the pattern data signal 6a at the timing of the timing signal 5a. The driver 10 outputs the test waveform signal 9a
"H" and "L" test waveforms 1 according to the waveform setting level signal 12a input from the reference voltage generator 12
0a to generate a test waveform, and
Is applied to the DUT 15.

The analog comparator 11 is connected to the DUT 15
Is input via the transmission line 14, and the comparison voltage 12b,
12c, and outputs a comparison result 11a.
At this time, the multiple reflection suppression circuit 13 suppresses the multiple reflection voltage generated due to the difference between the characteristic impedance of the transmission line 14 and the input impedance of the comparator 11 by employing impedance matching. The digital comparator 8 is a DUT 15 compared with the analog comparator 11.
Is compared with the expected value signal 6b, which is a non-defective response, at the timing of the phase signal 5c. The fail bit memory 7 stores the judgment result 8a for judging the quality of the DUT 15 and stores the judgment result 16d via the tester bus 16 after the test is completed.
Output to The above operation is performed simultaneously for each pin of the DUT 15, and the quality judgment of the DUT 15 is completed.

FIG. 1 is a detailed view focusing on the pin electronics 1 portion of the IC tester. The relationship between the operation of the pin electronics 1 and the reflection suppressing operation will be described with reference to FIG. A driver 10 receives a test waveform signal 9a from a waveform formatter, and the driver 10 sends an output waveform to a transmission path 14 of a coaxial cable via a driver output adjustment resistor 10b, and outputs the output waveform to a DUT 15 via the transmission path 14. The waveform is added as a test waveform. After a predetermined time, a response waveform 15 a (output waveform) from the DUT 15 is applied to an analog comparator 11 (hereinafter, comparator 11) that performs waveform determination via the transmission line 14. In this circuit, the multiple reflection suppressing circuit 13 is connected to a connection point N on the transmission line 14 side of the driver output adjustment resistor 10b.

The driver 10 receives the waveform voltage data 12a from the test signal generation / judgment unit 2 at the timing of the test waveform signal 9a and outputs a test waveform having the voltage level. When the driver 10 receives the response waveform 15a of the DUT 15, The high resistance mode is set at a timing according to the test waveform signal 9a. In the high-resistance mode, the output impedance of the driver 10 is set to a high resistance.
In the I / O switching time of the UT 15, the DUT output side (O
Side), the I / O switching period of the DUT 15, and a switching time shorter than the I / O switching period. The adjustment resistor 10b connected to the driver 10 matches the output impedance of the driver when applying a test waveform by making the output resistance equal to the characteristic impedance of the transmission line 14.

On the other hand, the multiple reflection suppressing circuit 13
5 and the characteristic impedance of the transmission line 14,
Further, the ringing of the response voltage waveform due to multiple reflection caused by the mismatch of the input impedance of the comparator 11 is suppressed by matching the characteristic impedance of the transmission line 14 with the impedance. Comparator 11
Is the DUT 15 suppressed by the multiple reflection suppression circuit 13.
Received by the input terminal via the transmission line 14 and compared with the comparison reference voltage levels 12b and 12c, respectively, and outputs comparison result signals 11a and 11b.

The multiple reflection suppressing circuit 13 includes a variable voltage source 13
4 and a high-side clamp circuit 131 having a variable voltage source 137. The voltage levels of the variable voltage sources 134 and 137 correspond to the clamp voltage control signal 1 from the test signal generation / determination unit 2.
In response to 3i, control is performed in accordance with the “H” and “L” output voltages of the DUT 15. The low-side clamp circuit 130 is composed of an npn-type bipolar transistor on the base side receiving the voltage of the variable voltage source 134, the collector side of which is connected to the positive side power supply line Vcc, and the emitter side of which is connected via a resistor 133 to the transmission line. 14 and is connected to a connection point N. The high-side clamp circuit 131 includes a pnp-type bipolar transistor on the base side receiving the voltage of the variable voltage source 137, the collector side of which is connected to the negative side power supply line Vee, and the emitter side of which is connected to the resistor 136.
Is connected to a connection point N with the transmission line 14 via the. Here, the variable voltage source 134 of the low-side clamp circuit 130
And the variable voltage source 1 of the high-side clamp circuit 131
The voltage 37 can be adjusted and set in a positive voltage range and a negative voltage range including the ground potential, respectively.

When the response waveform 15a of the DUT 15 falls from "H" to "L", the connection point N
The response waveform 15a of the DUT 15 at the input end of the response waveform 10a of the comparator 11 connected to the comparator 11 is significantly lower than "L" due to the influence of the reflected wave.
When the transistor 132 of the w-side clamp circuit 130 is turned on, the ON resistance is changed to the characteristic impedance Zo of the transmission line 14.
A current is injected from the power supply line Vcc to the transmission line 14 at a connection point N via an additional resistor 133 provided to make the current value equal to. Here, the resistance value of the ON resistance of the transistor 132 + the resistance value of the resistance 133 is set substantially equal to the characteristic impedance Zo of the transmission line 14, and
The voltage of the variable voltage source 134 of the side clamp circuit 130 is D
The transistor 132 is set to “L” of the UT 15, thereby turning on the transistor 132 when the value falls below the “L” by a predetermined value or more. As described above, the low-side clamp circuit 130 sets the response waveform 10a at the input terminal of the comparator 11 to the DUT
It is a circuit that operates only when the "L" of 15 falls below a predetermined value. Therefore, current consumption is not always caused, power consumption can be reduced, and the transistor 132 is turned on.
In this case, the impedance connected to the transmission line 14 is set to be substantially equal to the characteristic impedance Zo, so that the occurrence of ringing due to the reflected wave is suppressed.

Similarly, when the response waveform 10a of the DUT 15 rises, when the response waveform 10a exceeds "H" of the DUT 15, the High-side clamp circuit 131 operates. H
The high-side clamp circuit 131 is a pull-side complementary circuit arranged at a symmetrical potential with respect to the transmission line 14 with respect to the push-side low-side clamp circuit 130. This is the resistance value of the ON resistance of the transistor 135 + the resistance 1
36 is set substantially equal to the characteristic impedance Zo, and the voltage of the variable voltage source 137 of the high-side clamp circuit 131 is set to the “H” voltage, thereby exceeding the “H” by a predetermined value or more. The transistor 137 is turned on. The operation is similar to that described above, but rather than injecting current into the transmission line 14, this draws current. As described above, the power can be reduced, and the occurrence of ringing due to the reflected wave can be suppressed.

FIG. 2 shows such a multiple reflection suppressing circuit 13.
FIG. 10 is a diagram illustrating a reflection diagram and a response waveform corresponding to FIG. 9. The voltage of the variable voltage source 134 is set to ground GND + 0.7V, and the voltage of the variable voltage source 137 is set to 5V-0.7V.
Assume that it is set to FIG. 2A shows the current I on the horizontal axis and the voltage V on the vertical axis as in FIG.
Is the response waveform 1 of the DUT 15 at the input end of the
0a is shown. The input characteristic 100 of the comparator 11, the characteristic impedance 101 of the transmission line, the DUT
The 15 output resistors 102 are the same as those in FIG. The voltage point of the response waveform 10a on the comparator 11 side of the output “H” of the DUT 15 is H, and the voltage point of “L” is L
It is.

Now, the provision of the multiple reflection suppression circuit 13 turns on the transistors 132 and 135.
Then, the same characteristic impedance as that of the transmission line 14 is added to the transmission line 14. Therefore, the input resistance at the input terminal of the comparator 11 is the sum of the input resistance of the comparator 11 and the input resistance of the multiple reflection suppressing circuit 13, and is shown in a graph 105. Here, as described above, the combined resistance value of the additional resistance and the ON resistance of the transistor in the multiple reflection suppressing circuit 13 is set above the “H” and below “L” of the DUT 15 and the characteristic impedance of the transmission line 14 is reduced. Do the same. Therefore, the output voltage of the DUT 15 does not undergo multiple reflection via the intersection of the characteristic impedance Zo of the transmission line 14 and the output characteristic of the DUT 15, and the response waveform 10 a is changed by the voltage of the variable voltage source 134 by turning on the transistor 132. The response waveform 10a is clamped by the ground GND to absorb multiple reflections. As a result, large ringing due to the next multiple reflection is suppressed, and the “L” level on the comparator 11 side is suppressed.
Settle at L point. Note that 1 Vf is a forward drop voltage between the base and the emitter, which is usually 0.7 V, and the voltage of the variable voltage source 134 is set to the ground GND + 0.7 V. It is clamped at the ground potential 0.7 V lower than the set voltage. As a result, "L"
become. As a result, as shown in FIG.
The response waveform 106 (= response waveform 10a) does not exceed the "L" determination voltage 103 of the comparator 11, so that erroneous determination due to ringing of multiple reflection does not occur.

The case where the output of the DUT 15 changes from "H" to "L" has been described above. Conversely, when the output of the DUT 15 changes from "L" to "H", the impedance of the transmission line is not affected. Matching is taken, and the response waveform 10a is clamped at 5V (= 4.3V + 0.7V) by the voltage of the variable voltage source 137, so that multiple reflections are absorbed here, and large ringing due to the next multiple reflection is suppressed, and ringing is suppressed. “H” is the High-side determination level 1 shown in FIG.
It does not decrease to less than 03h. in this way,
The multiple reflection suppression circuit 13 having clamp circuits on the “H” side and the “L” side suppresses ringing due to multiple reflections generated between the DUT 15 and the pin electronics 1, thereby obtaining a good test waveform.

FIG. 4 shows another example of the configuration of the multiple reflection suppressing circuit according to the embodiment of the present invention. In this example, Hi of FIG.
gh-side clamp circuit 131 and low-side clamp circuit 13
0, clamp voltage switching circuits 138 and 139 are provided, respectively, and the voltage of the variable voltage source 134 is set so as to clamp the response waveform from the transmission line 14 to, for example, the ground GND which is “L” of the DUT. , Variable voltage source 13
The voltage of 7 is set to be clamped to, for example, 5 V which is “H” of the DUT. Therefore, as described below, the low-side clamp setting voltage output 134a
Is 3Vf = 2.1V, and the set voltage output 137a of the High side lamp is 5V-3Vf = 2.9V. 3Vf is connected to the variable voltage source 13 with respect to the connection point N of the transmission line 14 by providing the clamp voltage switching circuit.
This is because the voltage application points of 4,137 are shifted by 3 Vf. 4, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted (the same applies to the following drawings). In the example of FIG. 4, the emitter of the transistor 132 is connected to the emitter of the transistor 135 without the resistor 136 of FIG. 1, and is connected to the connection point N via the resistor 133.

In FIG. 4, transistors 132, 1
In order to prevent a reverse voltage of a certain voltage or more from being applied between the base and the emitter of the 35, clamp voltage switching circuits 138 and 139 comprising current switching switches are connected to each transistor 1
It is inserted between the base of 32 and the variable voltage source 134 and between the base of the transistor 135 and the variable voltage source 137. When the response waveform 10a becomes higher or lower than a predetermined value and a large reverse withstand voltage is applied between the emitter and the base of each transistor, the voltage is applied to the clamp voltage switching circuit 13 via the buffer circuit 13a.
8 and one of the clamp voltage switching circuits 139 are applied to the input to switch the base input voltages of the transistors 132 and 135. That is, the clamp voltage switching circuit 1 composed of a current switching circuit
The set voltage of the variable voltage source 134 is applied to the other input of the variable voltage source 38, and the set voltage of the variable voltage source 137 is applied to the other input of the clamp voltage switching circuit 139. Therefore, when the voltage on the output side of the buffer circuit 13a input to one of them becomes higher or lower than the predetermined value, the base input voltage of the transistor 132 and the transistor 135 is set to the output of the buffer circuit 13a. In this case, the base input voltage of each of the transistors 132 and 135 is switched to a voltage corresponding to the voltage on the output side of the buffer circuit 13a.

Here, the buffer circuit 13a is a voltage follower, which outputs the voltage level of the response waveform 10a of the DUT 15, and the input side of which is a resistor 1a.
The output signal is connected to the connection point N via the output terminal 33 and is sent to the clamp voltage switching circuits 138 and 139. The clamp voltage switching circuits 138 and 139 compare the output voltage of the buffer circuit 13a with the voltages of the variable voltage sources 134 and 137 to determine the low clamp voltage switching circuits 138.
Is a current switching switch for switching the set voltage to a higher voltage, and a high-side clamp voltage switching circuit 139 is a current switch for switching the set voltage to a lower voltage.

The configuration of the low-side clamp voltage switching circuit 138 has npn-type differential transistors Q1 and Q2, the collector side of which is connected to the power supply line Vcc, and the emitter side of which is inserted in the forward direction. Via the diodes Da and Db, a common constant current source 138a (current value I
o), and the current outflow side of the constant current source 138a is connected to the negative power supply line Vee. Further, the emitter of the transistor Q1 and the emitter of the transistor Q2 are independent of the constant current source 138b (current value I1) and the constant current source 138c.
(Current value I1) and the constant current sources 138b, 138
The current outflow sides of c are respectively connected to the negative power supply line Vee. The base of the transistor 132 is connected to a point Na on the diode connection side of the common constant current source 138a, from which an output current is taken. Here, the diodes Da and Db are both connected on the cathode side to the constant current source 138a, and function as diode switches for selecting one of the input sides.

High-side clamp voltage switching circuit 139
Has pnp-type differential transistors Q3 and Q4, the collector side of which is connected to the negative power supply line Vee, and the emitter side of which is connected in common via diodes Dc and Dd inserted upstream in the forward direction, respectively. Constant current source 139
a (current value Io), and is connected to the outflow side of the constant current source 139.
a is connected to the power supply line Vcc. Further, the emitter of the transistor Q3 and the emitter of the transistor Q4 are independent of the constant current source 139b (current value I1),
Connected to the outflow side of the constant current source 139c (current value I1),
The current inflow sides of the constant current sources 139b and 139c are respectively connected to the power supply line Vcc. The base of the transistor 135 is connected to a point Nb on the diode connection side of the common constant current source 139a, from which an output current is taken. The diodes Dc and Dd are both connected on the anode side to the constant current source 138a, and function as diode switches for selecting one of the input sides. Clamp voltage switching circuit 1 having such a current switching switch
In the transistors 38 and 139, the transistors Q1 and Q2 or the transistors Q3 and Q4 both have an independent current source having a current value I1, and are therefore in an ON state. , The diode switch is turned ON / OFF to perform a switching operation.

In the clamp on the low side, the transistor 1
When the emitter of 32 becomes higher than the base, its breakdown voltage becomes a problem. Therefore, when the voltage becomes higher than the base setting voltage of the transistor 132 by +2 Vf, a voltage lower by a predetermined value (2 Vf in this example) than the voltage on the emitter side of the transistor 132 is applied to the transistor 1.
The switching to be applied to the base of 32 is the clamp voltage switching circuit 1.
38. That is, the clamp voltage switching circuit 1
At 38, when the voltage on the emitter side of the transistor 132 exceeds the set voltage and rises by 2 Vf or more and the base voltage of the differential transistor Q1 increases in response to this, the transistor 132 is connected to the emitter side of the differential transistor Q2 on the lower side. The diode Db is reverse-biased and turned off, and the diode Da connected to the emitter of the differential transistor Q1 having the higher base voltage is turned on, whereby current switching is performed. At this time, a voltage 2 Vf lower than the voltage on the emitter side of the transistor 132 is applied to the base of the transistor 132.

In the high-side clamp, when the emitter of the transistor 135 is lower than the base, the withstand voltage becomes a problem. Therefore, when the voltage becomes −2 Vf lower than the base setting voltage of the transistor 135, a voltage higher by a predetermined value (2 Vf in this example) than the voltage on the emitter side of the lowered transistor 135 is applied to the transistor 135.
Switching to be applied to the base of the clamp voltage switching circuit 139
Done through. That is, the clamp voltage switching circuit 139
, The differential transistor Q4 on the side where the base voltage is high
When the diode Dd connected to the emitter side of the differential transistor Q3 is reverse-biased and turned off, and the diode Dc connected to the emitter of the differential transistor Q3 having the lower base voltage is turned on, current switching is performed. At this time, transistor 1
A voltage 2 Vf higher than the voltage on the emitter side of the transistor 35 is applied to the base of the transistor 135. In the above case, the switching current of one of the differential transistors flows to the commonly connected current source 138a of the current value Io on the Low side, and the current source 1 of the current value Io on the High side.
Receives current from 39a. The connection point Na is clamped to a voltage lower by 2 Vf than the high emitter voltage of the transistor 132, and the connection point Nb is clamped to a voltage higher by 2 Vf than the low emitter voltage of the transistor 135.

Here, if it is assumed that the voltage drop of the resistor 133 is ignored, the low-side clamp voltage switching circuit 138
Then, the voltage at the connection point N on the transmission line 14 side is
4 when the voltage exceeds 2.1V, the voltage at the connection point N-2V
The voltage f is applied to the base of the transistor 132, and the transistor 132 is reverse-biased and turned off. Since the emitter side of the transistor 132 is connected to the connection point N, the reverse voltage between the base and the emitter of the transistor 132 is 2 Vf, and no further voltage is applied. In the high-side clamp voltage switching circuit 139, when the voltage at the connection point N becomes lower than the voltage 2.9V of the variable voltage source 137, the voltage of the connection point N + 2
A voltage of Vf is applied to the base of transistor 135,
The transistor 135 is reverse-biased and turned off. Since the emitter side of the transistor 135 is connected to the connection point N, the reverse voltage between the base and the emitter of the transistor 135 is 2 Vf, and no further voltage is applied. Therefore, in any case, the reverse withstand voltage of 2 Vf or more does not need to be applied. Thus, the transistors 132 and 135 do not need to be degraded or damaged due to the reverse voltage Veb. Note that the ignored resistor 13
The reverse withstand voltage can be adjusted in consideration of the voltage drop of No. 3. Of course, in the above case, the input side of the buffer circuit 13a may be directly connected to the connection point N.

Next, the overall operation will be described. The resistor 133 is used to make the ON resistance of the low-side clamp circuit 130 and the high-side clamp circuit 131 equal to the characteristic impedance of the transmission line 14. Are common to the low-side clamp and the high-side clamp. First, the voltage level of the response waveform 10a of the DUT 15 is always detected by the buffer circuit 13a (voltage follower) having a low input current with a voltage gain of 1 and is output to the clamp voltage switching circuits 138 and 139. The clamp voltage switching circuits 138 and 139
The operation is performed so that a reverse voltage of 2 Vf or more is not applied between the base and the emitter of the transistors 135. The buffer circuit 1
3a uses a buffer with a low input current in order to keep the input characteristics at a high resistance when the clamp circuit is OFF.

Next, the operation will be described by taking a specific voltage value as an example. As described above, in this example, the low clamp voltage is 0 V, and the high voltage is 5 V. When the ON voltage Vbe of the transistors 132 and 135 (base-emitter voltage at the time of ON) is 0.7 V, the ON voltage Vbe of the transistors is 0.7 V, so that the low-side clamp at the base of the transistor 132 is set. The voltage 132a is 0.7 V, and the setting voltage 135a of the High side clamp at the base of the transistor 135 is 4.
It will be set to 3V. Therefore, as described above, the voltage of the variable voltage source 134 is further added by 2 Vf to 2.1 V, and the voltage of the variable voltage source 137 is
The voltage further drops by 2 Vf from the above to 2.9 V. In this case, each of the diodes Da, Db, Dc,
If Dd is a Schottky diode, the voltage drop is about 0.3 V.
This is more convenient because it can be further reduced to about 1.0 V.

Here, the set voltage 132a (0.7V),
Assuming that the set voltage 135a (4.3V) is always input to the bases of the transistors 132 and 135 without the clamp voltage switching circuit, a reverse voltage is applied between the base and the emitter of the transistor 132 or the transistor 135 by the response waveform 10a of the DUT 15. Is done. For example, DU
When the output voltage 10a of T15 is 5V, the comparator 1
1 is 5V, and when the base input 132a of the low-side transistor 132 is 0.7V, which is the same potential as the low-side clamp setting voltage 134a, 4.3V is applied between the base and the emitter of the transistor 132. Will be applied. Similarly, the output voltage 10a of the DUT 15
Is 0 V, a reverse voltage of 4.3 V is applied between the base and the emitter of the transistor 135. Generally, the reverse breakdown voltage between the base and the emitter of a transistor is inversely proportional to the operating frequency limit of the transistor. The higher the operation speed, the smaller the reverse breakdown voltage. Also, the cut-off frequency f of the transistor
Since o is 10 GHz and the reverse withstand voltage between the base and the emitter is about 2.5 V, the reverse withstand voltage between the base and the emitter is required under any conditions for the high-speed operation of the clamp circuit and the expansion of the input voltage range. It is required not to exceed.

Therefore, in order to meet this demand, a configuration as shown in FIG. 4 may be adopted. The switching operation of the High-side clamp voltage will be described with reference to FIG.
A straight line indicated by a dotted line is the input voltage 10c input via the buffer circuit 13a. High side clamp setting voltage 1
37a is 4.3V. The high-side clamp voltage switching circuit 139 selects the lower one of the input voltage 10c and the high-side clamp setting voltage 137a by the switching operation of the current switch, and outputs a voltage output indicated by a thick solid line 2 Vf lower than the base voltage of the transistor 135. Output to Therefore, the transistor 135 is determined by the response waveform 10b.
Considering the case where the base voltage changes from -2 V to 5 V, when the input voltage 10b is 5 V, the base-emitter voltage of the high-side clamp transistor 135 becomes 0.7 V and turns on to absorb multiple reflection components. I do. On the other hand, when the input voltage 10b is 4.3 V to 5 V, a reverse voltage of 0.7 V at the maximum is applied to the transistor 135 to turn it off. When the input voltage 10b is 4.3 V or less, the same voltage as that on the emitter side is applied to the base of the transistor 135, and the transistor 135 is turned off.

Similarly, FIG. 5B is an explanatory diagram of the switching operation of the low-side clamp voltage, and the low-side clamp voltage switching circuit 138 has a higher one of the input voltage 10c and the low-side clamp setting voltage 134a. Is selected by the switching operation of the current switch, and a voltage output indicated by a thick solid line 2 Vf higher than that is output to the base of the transistor 132. Low-side clamped transistor 13 at 0 V or less
2 is turned on, and is operated to be turned off at a potential higher than 0 V in the same manner as described above. As a result, the multiple reflection suppressing circuit 13
Can be extended. In FIG. 4, both the low-side clamp circuit and the high-side clamp circuit are connected to the connection point N by a common resistor 133. However, in these clamp circuits, the resistor 132 may be connected to the transistor 132, the resistor 136 may be connected to the transistor 135, and each may be connected to the connection point N, as in the case of FIG. In particular, in this case, the input voltage of the buffer circuit 13a can be the voltage at the connection point N. Note that the input voltage of the buffer circuit 13a may be the voltage at the connection point N even in the case of FIG.

FIG. 6 shows a specific configuration example of a multiple reflection suppressing circuit using a current mirror circuit. The multiple reflection suppressing circuit 17 includes a low-side clamp circuit 170, a high-side clamp circuit 171, and an input resistance adjusting resistor 17n. In this embodiment, the voltages of the variable voltage sources 134 and 137 are one-side voltage adjustment in the positive direction. In the low-side clamp circuit 170, reference numeral 172 denotes an input-side pnp transistor of a current mirror, the emitter of which is connected to the power supply line Vcc. The input side pnp transistor 173 has its emitter connected to the collector of the transistor 172 via level shift diodes (diode-connected transistors) D1 and D2.
2 is a downstream input stage pnp transistor that draws a drive current from 2, and receives the voltage of the variable voltage source 134 at its base. Reference numeral 174 denotes a pnp transistor on the output side of the current mirror, the emitter of which is connected to the power supply line Vcc. An npn transistor 175 is provided downstream of the transistor 173 so as to correspond to the transistor 173, and the emitter of the transistor 174 is connected in series to the collector of the transistor 174. Downstream thereof, level shift diodes (diode-connected transistors) D3 and D4 are connected in series with this in the forward direction, and further connected to a connection point N via a resistor 17n.
And the potential levels of the input side and the output side are matched.

Similarly, in the high-side clamp circuit 171, reference numeral 176 denotes an input-side npn-type transistor of a current mirror, the emitter of which is connected to the negative power supply line Vee. Reference numeral 177 denotes an upstream input stage npn-type transistor which is connected to the collector of the transistor 176 through a level shift diode (diode-connected transistor) D5, D6 and applies a drive current to the transistor 176; To its base. 178 is the output side np of the current mirror.
An n-type transistor, the emitter of which is connected to the negative power supply line Vee. Transistor 17 upstream of this
7, an npn transistor 179 is provided, and the emitter of the transistor 178 is connected in series to the collector of the transistor 178. Upstream, a diode (diode-connected transistor) for level shifting in series with this
D7 and D8 are connected in the forward direction, and further connected to a connection point N via a resistor 17n, so that the potential levels on the input side and the output side are matched. The driving transistor 17
Collector sides of 3 and 177 are respectively connected to predetermined bias lines.

The feature of this clamp circuit is that the current ratio between the preceding and subsequent circuits can be changed because of the current mirror circuit configuration. Thus, the variable voltage source 1
34, 137 can be reduced. Further, since the voltage drop of the transistor Vbe is the same in the former-stage circuit and the latter-stage circuit, the clamp voltage and the set voltage of the variable voltage source can be the same, and the clamp voltage can be easily set. Further, since the reverse voltage between the base and the emitter of the transistor at the time of OFF is applied to the three-stage stacked transistor, the reverse voltage increases, and the reverse withstand voltage by the feedback circuit as shown in the embodiment of FIG. There is an advantage that the circuit can prevent multiple reflections in a wide voltage range without correcting the above.

FIG. 7 shows a specific configuration of the multiple reflection suppressing circuit based on the inverted Darlington system. The multiple reflection suppressing circuit 18 includes a low-side clamp circuit 180,
gh-side clamp circuit 181, input resistance adjustment resistor 18
7. In the low-side clamp circuit 180, reference numeral 183 denotes a pnp transistor on the input side of a current mirror, the emitter of which is connected to the power supply line Vcc. Reference numeral 181 denotes a downstream input-stage npn-type transistor whose collector is connected to the collector of the transistor 183 and which draws a drive current from the transistor 183.
To receive the voltage of the variable voltage source 134 at its base. Reference numeral 182 denotes a pnp transistor on the output side of the current mirror, which is an output transistor corresponding to the transistor 132 in FIG. The emitter is the power line V
cc, and the collector is further connected to a connection point N via a resistor 187. In addition, a switch circuit 184 is provided between the power supply line Vcc and a base of the current mirror connection transistors 182 and 183 connected to each other.

Similarly, in the high-side clamp circuit 190, reference numeral 193 denotes an npn-type transistor on the input side of a current mirror, the emitter of which is connected to the power supply line Vcc. Reference numeral 191 denotes an upstream input stage pnp transistor whose collector is connected to the collector of the transistor 193 and applies a drive current to the transistor 193. The emitter is further connected to the connection point N via a resistor 187. To the base voltage. 1
Reference numeral 92 denotes an npn transistor on the output side of the current mirror, which is an output transistor corresponding to the transistor 135 in FIG. The emitter is connected to the negative power supply line Vee, and the collector is further connected via a resistor 187 to a connection point N.
It is connected to the. In addition, the bases of the current mirror connected transistors 192 and 193 are connected to each other.
A switch circuit 194 is provided between the negative power supply line Vee.

The feature of this clamp circuit is that the transistor 18 is connected via the input transistor 183 of the current mirror.
1 and 182, which are formed by connecting transistors 181 and 182, and the transistors 191 and 192 which are connected via a current mirror input transistor 193. And an inverted Darling connection 195 composed of transistors 191 and 192. Since each is connected by an inverted Darlington, the current ratio between the first and second circuits can be increased. Therefore, the variable voltage source 134,
There is an advantage that the circuit current of 137 can be reduced and a variable voltage source can be easily configured. The switch circuits 184 and 194 are connected to the low-side clamp circuit 180 and Hi
This is a switch circuit that is turned ON when each operation of the gh-side clamp circuit 190 is stopped, and sets the transistor of the current mirror to an OFF state.

FIG. 8 is an explanatory diagram of a connection example for connecting a multiple reflection suppressing circuit. In this example, the driver 10 of the pin electronics 1 is connected to the transmission line 14 via three impedance matching resistors 200, 201, and 202 forming a T-type circuit. The output impedance of the driver 10 is matched to the characteristic impedance of the transmission line 14 by the resistors 200 and 201, and the input impedance of the multiple reflection suppression circuit 13 is
2 matches the characteristic impedance of the transmission line 14. At this time, the value of the matching resistor 200 is set to be the largest value. That is, when the output resistance of the driver circuit 10 is smaller than the input impedance of the multiple reflection suppression circuit 13, the resistance 202 is set to zero. On the contrary, when the output resistance of the driver 10 is larger than the input impedance of the multiple reflection suppression circuit 13, By setting the resistance 201 to zero, the multiple reflection preventing circuit 13
Can be provided. As a result, the deterioration of the output waveform of the driver circuit 10 due to the parasitic capacitance of the multiple reflection suppressing circuit 13 can be reduced.

As described above, the circuit shown in each embodiment is a basic or principle circuit, and each transistor is provided with a bias setting and an operation-specific adjustment in accordance with the adjustment.
It goes without saying that various resistors and capacitors may be connected or added. Further, various characteristic correction circuits may be provided. Further, although the example of the transistor is a bipolar transistor, it goes without saying that other transistors such as a MOS transistor may be used.

[0049]

As described above, according to the present invention, the transistors which are turned on in response to the change of the response waveform from the High level to the Low level or vice versa are provided. By connecting the internal impedance on the output side of the transistor, for example, the impedance between the collector and the emitter, to the transmission line, a circuit equivalent to providing a terminating resistor can be obtained. Thereby, multiple reflection of the response waveform can be suppressed. Furthermore, by using the transistors that are turned ON at each of the high level and the low level, the transmission path is voltage-clamped by the voltage of the voltage generation circuit, thereby absorbing the reflected wave and suppressing ringing. As a result, since the response waveform becomes accurate, erroneous determination of the comparator can be eliminated. Further, accurate timing measurement of a response waveform from the DUT can be performed. Further, since no current flows except when the reflected wave is absorbed, power consumption can be reduced. In addition, since it is not necessary to use a diode bridge that operates at high speed, a leak current is small, switching control is not required, and the circuit can be simplified and control can be simplified. Moreover, it is easy to make an IC.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram focusing on a pin electronics portion of an embodiment to which an IC tester according to the present invention is applied.

FIGS. 2A and 2B are explanatory diagrams for explaining the operation of the multiple reflection suppressing circuit of FIG. 1; FIG. 2A is a graph diagram of a reflection diagram thereof, and FIG. 2B is an explanatory diagram of a response waveform thereof; is there.

FIG. 3 is an overall configuration diagram of an IC tester provided with a multiple reflection suppressing circuit according to the present invention.

FIG. 4 is an explanatory diagram of another specific configuration example of the multiple reflection suppressing circuit according to the embodiment of the present invention.

5A and 5B are explanatory diagrams of an operation of switching a clamp voltage of a response waveform from a DUT, wherein FIG. 5A is an explanatory diagram of a switching operation of a high-side clamp voltage, and FIG.
FIG. 5 is an explanatory diagram of a switching operation of a side clamp voltage.

FIG. 6 is an explanatory diagram of a specific configuration example of a multiple reflection suppression circuit using a current mirror circuit.

FIG. 7 is an explanatory diagram of a specific configuration example of a multiple reflection suppressing circuit based on the inverted Darlington method.

FIG. 8 is an explanatory diagram of a connection example for connecting a multiple reflection suppression circuit.

FIG. 9 is a graph diagram of a reflection diagram illustrating the principle of multiple reflection and ringing generation in this type of IC tester, and FIG. 9B is a diagram illustrating a response waveform from the DUT.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Pin electronics, 2 ... Test signal generation / judgment part, 3 ... Control computer (or MPU), 4 ... Reference signal generator, 5 ... Timing generator, 6 ... Pattern generator, 7 ... Fail memory, 8 ... Digital Comparator, 9: Waveform formatter, 9a: Test waveform signal, 1
0 ... driver, 11 ... analog comparator, 12 ... reference voltage generator, 13, 17, 18 ... multiple reflection suppression circuit, 14 ... transmission line, 15, 151, 152, 15
3. DUT (semiconductor device under test).

Claims (12)

[Claims] An output of a predetermined test waveform from a driver provided in a pin electronics is applied to a semiconductor device under test via a transmission line, and a response waveform is received from the semiconductor device under test after a predetermined time via the transmission line. A semiconductor device testing apparatus for comparing the state of the response waveform with a predetermined voltage level by an analog comparator, wherein the response waveform is connected between the transmission path and an input terminal of the comparator, and the response waveform changes from a high level to a low level. A first switch circuit, which is turned on in response to the above and connects an impedance substantially equal to the characteristic impedance of the transmission line to the transmission line, and a first switch circuit connected between the transmission line and an input terminal of the comparator, The signal is turned on in response to the change of the waveform from the low level to the high level, A second switch circuit for connecting an impedance substantially equal to the characteristic impedance of the transmission line to the transmission line, and a voltage connected to the first switch circuit for clamping the response waveform at a low level; A semiconductor device test apparatus, comprising: a first voltage generation circuit; and a second voltage generation circuit connected to the second switch circuit and configured to generate a voltage for clamping the response waveform at a high level. 2. The circuit according to claim 1, wherein each of the first and second switch circuits comprises a transistor, and the impedance substantially equal to the characteristic impedance of the transmission line is an impedance including an internal impedance of the transistor. A semiconductor device test apparatus according to claim 1. 3. An output of a predetermined test waveform from a driver provided in the pin electronics is applied to the semiconductor device under test via a transmission line, and a response waveform is received from the semiconductor device under test after a predetermined time via the transmission line. In the semiconductor device test apparatus for comparing the state of the response waveform with a predetermined voltage level by an analog comparator, the response waveform changes from a high level to a low level and is connected between the transmission path and an input terminal of the comparator. And a first transistor which is turned on in response to the output side internal impedance or suppresses multiple reflection of the response waveform by a combination of this impedance and an impedance connected in series with the impedance. Connected to the input end of the response waveform a second transistor which is turned on in response to a change from the low level to the high level and suppresses multiple reflection of the response waveform by its internal impedance on the output side or a combination of this impedance and an impedance connected in series thereto And the response waveform connected to the first transistor is represented by a certain L
a first voltage generating circuit for generating a voltage for clamping at an ow level, a second voltage generating circuit connected to the second transistor for generating a voltage for clamping the response waveform at a high level, and A semiconductor device test apparatus comprising: 4. The circuit according to claim 1, wherein said comparator determines a level of said response waveform, and said first transistor is connected to a control electrode of said first voltage generating circuit, and said first low-level crank is connected to said low-level crank. The second transistor is connected to a control electrode of the second voltage generating circuit to form the high-level crank circuit, and the transmission line and the first and second transistors are connected to each other. 4. A semiconductor device test apparatus according to claim 3, wherein a resistance value is provided between said transmission line and said transistor and an ON resistance of said transistor is substantially equal to a characteristic impedance of said transmission line. 5. The first and second voltage generating circuits are variable power supplies whose generated voltages can be set from outside.
The first transistor is an NPN transistor;
The second transistor is a PNP transistor;
The semiconductor device test apparatus according to claim 4, wherein the control electrode is a base of these transistors, and the impedance connected in series with the internal impedance includes the resistance provided corresponding to each transistor. 6. A first switching circuit provided between a base of said first transistor and said first voltage generating circuit, and a base of said second transistor and said second voltage generating circuit. And a buffer circuit that receives the voltage of the connection point of the resistor or the voltage of the transmission line and outputs the voltage to the first and second switching circuits, A first switching circuit that, when at least an output voltage of the buffer circuit exceeds a voltage of the first voltage generation circuit, changes a base voltage of the first transistor from a voltage of the first voltage generation circuit to a voltage of the buffer; The second switching circuit switches the base voltage of the second transistor to the second voltage when at least the output voltage of the buffer circuit falls below the voltage of the second voltage generation circuit. The semiconductor device testing apparatus of claim 5, wherein switching from the voltage of the pressure generating circuit to the voltage of the buffer circuit. 7. The semiconductor device according to claim 5, further comprising first and second current mirror circuits, wherein said first and second transistors are output transistors of said first and second current mirror circuits, respectively. Semiconductor device test equipment. 8. An output of a predetermined test waveform from a driver provided in the pin electronics is applied to the semiconductor device under test via a transmission line, and a response waveform is received via the transmission line after a predetermined time from the semiconductor device under test. In the semiconductor device test apparatus for comparing the state of the response waveform with a predetermined voltage level by an analog comparator, the response waveform changes from a high level to a low level and is connected between the transmission path and an input terminal of the comparator. And a first transistor which is turned on in response to the output side internal impedance or suppresses multiple reflection of the response waveform by a combination of this impedance and an impedance connected in series with the impedance. Connected to the input end of the response waveform a second transistor which is turned on in response to a change from the low level to the high level and suppresses multiple reflection of the response waveform by its internal impedance on the output side or a combination of this impedance and an impedance connected in series thereto And a first generator connected to the first transistor for generating a voltage for clamping the response waveform at a predetermined low level.
And a second voltage generation circuit connected to the second transistor for generating a voltage for clamping the response waveform at a predetermined High level. 9. The circuit according to claim 1, wherein said comparator determines a level of said response waveform, and said first voltage generation circuit is connected to a control electrode of said first transistor, and said second voltage generation circuit is connected to a control electrode of said first transistor. The circuit is connected to a control electrode of the second transistor, includes a resistor between the transmission line and the first and second transistors, and calculates a resistance value of a sum of the resistance and an ON resistance of the transistor. 9. The multiple reflection suppressing circuit according to claim 8, wherein the characteristic impedance is set substantially equal to the characteristic impedance of the transmission line. 10. The first and second voltage generating circuits include:
The first transistor is an NPN transistor, the second transistor is a PNP transistor, the control electrode is the base of these transistors, and the internal impedance and the internal impedance The multiple reflection suppressing circuit according to claim 9, wherein the impedances connected in series include the resistors provided corresponding to the respective transistors. 11. A predetermined test waveform output from a driver provided in a pin electronics is applied to a semiconductor device under test via a transmission line, and a response waveform is received from the semiconductor device under test after a predetermined time via the transmission line. A method of testing the semiconductor device, wherein the state of the response waveform is determined by a comparator, wherein the first signal is connected between the transmission path and an input terminal of the comparator, and the first signal is changed according to a change from a high level to a low level of the response waveform. Is turned on to connect an impedance substantially equal to the characteristic impedance of the transmission line, and is connected between the transmission line and the input terminal of the comparator from the low level to the high level of the response waveform. The second switch circuit is turned on in accordance with the change in the characteristic impedance of the transmission line. The response waveform is clamped to a certain Low level when the response waveform falls below a certain Low level, and the response waveform is clamped to the certain Low level when the response waveform falls below the same. A method for testing a semiconductor device, wherein the response waveform is clamped to the certain High level when the threshold value is reached. 12. The first and second switch circuits,
12. The semiconductor device test apparatus according to claim 11, wherein each of the transistors is constituted by a transistor, and the impedance substantially equal to the characteristic impedance of the transmission line is an impedance including an internal impedance of the transistor.