JP2000294423A - Laminated ferrite inductor device and manufacture therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent improper insulation between outer terminal electrodes caused by expansion in plating by adjusting a ferrite surface between the outer terminal electrodes to have a specific surface roughness. SOLUTION: Printed ferrite green sheets are so laminated in a predetermined order as printed patterns on adjacent sheets to become an U letter form which faces each other, are heated and clamped, after that are cut to form a chip, are detached from a binder and are made heat treatment to form a sintered compact. After the sinter treatment the obtained chip is ground, metallic paste such as silver is applied at a predetermined part and outer terminal electrodes are formed by baking treatment. Next, the ferrite surface between the outer terminal electrodes is ground to adjust at a predetermined roughness, after that metallic coating treatment is made by electrolytic plating. In this case center line mean roughness (Ra) is adjusted to be in a range of 0.01 to 0.1 μm or preferably 0.02 to 0.05 μm.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is to prevent so-called plating spread when a metal film is plated on the surface of an external terminal electrode provided on a laminated ferrite inductor, thereby preventing insulation failure between adjacent terminals. The present invention relates to a high quality inductor device such as a ferrite chip inductor and an inductor array.

[0002]

2. Description of the Related Art A plurality of layers of a ferrite sheet on which a U-shaped silver conductor pattern is printed are formed by combining a U-shaped silver conductor pattern on an adjacent sheet, that is, a U-shape of a set of patterns 1,. And a coil-shaped laminated body sintered by electrically connecting the silver conductor pattern through through holes 3,... Formed in a ferrite sheet. As shown in FIG. 1, a surface mount type component, for example, a ferrite inductor array, in which inductors composed of are arranged in parallel inside a ferrite 4, is already known (Japanese Patent Publication No. 62-24923).

Recently, electronic devices have been significantly reduced in size, and accordingly, demands for miniaturization of components used have been increasing. For example, in chip capacitors, chip resistors, etc., 1005
(1 mm in length, 0.5 mm in width, 0.5 mm in height) is becoming a general specification, and the demand for an array equipped with a plurality of these elements is also increasing. However, in the chip inductor, since the complicated shape of the coiled internal conductor structure as described above must be formed inside the ferrite porcelain, there are various difficulties in downsizing and compared to the fields of capacitors and resistors. The response has been significantly delayed, and at present, the 1608 shape (1.6 mm in height, 0.8 mm in width, 0.8 mm in height) has been changed to the 3216 shape (3.2 mm in length, 1.6 mm in width, It is a fact that a four-circuit built-in type (1.6 mm) is being put to practical use.

Heretofore, a ferrite chip inductor array has been proposed in which the arrangement of internal conductors is modified to obtain a higher inductance with a smaller chip size (JP-A-5-32627).
0, JP-A-5-326271, 5-326
272). In addition, several methods for improving the interaction between circuits, that is, crosstalk, have been proposed (Japanese Patent Application Laid-Open Nos. Hei 6-338414 and Hei 7-2224).
No. 3, JP-A-8-250333, JP-A-8-250333
264320).

[0005] However, further miniaturization, 201
0 shape (2.0 mm long, 1.0 mm wide, 1.0 m high)
m) It has been found that the following four-circuit built-in type array causes troubles not seen in the conventional chip capacitors. That is, in a multilayer ferrite inductor device, a terminal electrode is provided by soldering, and a tin film is usually formed on the surface of the terminal electrode by electrolytic plating in order to smoothly perform the soldering.
By the way, in this case, if the solid resistance of the porcelain is low, a plating film is formed up to the porcelain portion other than the terminal electrode portion by the plating process, that is, a so-called spreading phenomenon occurs. In the conventional chip size, there is no particular problem because the distance between terminals is relatively large.
In the case of a compact type such as a 4-line type having a 2010 shape and a 4-line built-in type, insulation failure occurs because the distance between terminals is 0.5 mm or less.

[0006]

SUMMARY OF THE INVENTION An object of the present invention is to provide a high quality product by preventing insulation failure between external terminal electrodes due to plating spread in a small-sized multilayer ferrite inductor device. It is.

[0007]

The inventor of the present invention has conducted various studies on the behavior of plating applied to the surface of an external terminal electrode in a multilayer ferrite inductor device. The present inventors have found that the present invention is related to the present invention, and have accomplished the present invention based on this finding.

That is, the present invention relates to a multilayer ferrite inductor device comprising an internal conductor, a ferrite porcelain and an external terminal electrode, wherein the ferrite surface between the external terminal electrodes has a surface roughness of 0.01 to 0.1 μm. After drilling through holes in the inductor device and the ferrite green sheet, which are characterized by being adjusted,
A conductor forming paste is screen-printed to form a conductor pattern, and the through-hole is filled with the conductor paste.Then, a plurality of layers of the printed ferrite green sheet are laminated, heated and pressed, and then cut into arbitrary dimensions. In a method of manufacturing a multilayer ferrite inductor device by performing a sintering process as a chip shape to obtain a ferrite structure having a coil-shaped internal conductor, baking a terminal electrode, and plating a metal conductor film on a surface of the terminal electrode, A method comprising performing a polishing treatment between the baking step of the terminal electrode and the plating step of the surface thereof, and adjusting the surface roughness of the ferrite surface between the external terminal electrodes to 0.01 to 0.1 μm. To provide. In addition, the surface roughness in the present invention is the center line average roughness (R) measured by a measuring instrument specified in JIS B0651.
means a).

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION The ferrite porcelain used in the present invention can be arbitrarily selected from ferrite materials commonly used in conventional multilayer ferrite chip inductors, but it is easy to co-fire. In this respect, nickel copper zinc ferrite is particularly preferable. The structure of the multilayer ferrite inductor device of the present invention is not particularly different from a conventional one, for example, the structure shown in FIG.

Next, a method of manufacturing a multilayer ferrite chip inductor according to the present invention will be described with reference to the process chart of FIG.
That is, according to the method of the present invention, first, a slurry is prepared by mixing a ferrite powder or a raw material mixed powder for ferrite formation with a binder and an organic solvent, and the slurry is formed on a plastic film such as a polyethylene terephthalate film, for example, by a doctor. A ferrite green sheet is produced by applying and drying by a blade method.

Next, through holes are formed in the ferrite green sheet by mechanical punching, laser processing, or the like, and a paste containing silver or a silver-palladium alloy is screen-printed on the through-holes to form conductor patterns of internal conductors. At the same time, the paste is filled in through holes for electrically connecting the ferrite green sheets.

Next, the printed ferrite green sheets thus obtained are laminated in a predetermined order so that the printing patterns on the adjacent sheets are opposed to each other in a U-shape, heat-pressed, and cut into desired dimensions. Chip shape. Next, the green chip thus obtained is subjected to a binder removal treatment and then a heat treatment for firing to form a sintered body. The sintering temperature at this time is 860 to 96
A range of 0 ° C is chosen.

After the sintering process, the obtained chip is polished, a paste of a metal such as silver is applied to a predetermined portion, and baked to form external terminal electrodes. Next, the surface of the ferrite between the external terminal electrodes is polished,
If the surface is adjusted to a predetermined surface roughness and then subjected to electrolytic plating and metal coating, a chip inductor having a coil built in ferrite can be manufactured. By incorporating a plurality of such chip inductors, a chip inductor array as shown in FIG. 1 can be obtained.

For polishing the ferrite surface in the method of the present invention, abrasives such as silicon carbide, diamond, corundum, cubic boron nitride, and fused alumina are used, and silicon carbide is particularly preferred. These are fineness #
5000 to # 12000, preferably # 8000 to # 1
0000 powder. As the polishing method,
For example, barrel polishing is appropriate. Thus, the center line average roughness (Ra) is adjusted so as to be in the range of 0.01 to 0.1 μm, preferably 0.02 to 0.05 μm.

In the case where silicon carbide is used as the abrasive, if the particle size is # 5000 to # 12000, the surface roughness is in the range of 0.01 to 0.1 μm, and the plating elongation is 0.05 mm or less. A device without troubles can be obtained. If a material having a fineness greater than # 5000 is used, the surface roughness becomes 0.2 μm or more, the plating elongation becomes 0.1 mm or more, and # 12000
If a finer material is used, the surface roughness is 0.005μ.
m, the adhesive strength between the plating layer and the external terminal electrode is insufficient, and the plating film is easily peeled off.

The reason why the plating spread is reduced when the surface roughness is reduced is considered to be as follows. In other words, when the surface is relatively rough, plating adheres to the conductors of the terminal electrodes and also to the irregularities of the ferrite porcelain, but the adhesion between the ferrite porcelain and the plating layer is reduced by the surface roughness of the ferrite porcelain. The larger, the stronger. Then, at this time, the same adhesion occurs also in the plating unnecessary portion of the adjacent ferrite porcelain, and this is repeated as a unitary growth, resulting in plating elongation.
However, when the surface of the ferrite porcelain is flat, even if the plating is once adhered, the adhesion between the ferrite porcelain and the plating layer is small, and the ferrite porcelain is easily peeled off.

[0017]

Next, the present invention will be described in more detail with reference to examples. The surface roughness and plating spread in each example were measured as follows. (1) Surface roughness: measured using a Mitutoyo 620 SV surface roughness meter (manufactured by Mitutoyo Corporation), and the center line average roughness (R
a) was determined. (2) Plating elongation: The maximum distance in the unnecessary portion of plating on the surface of the ferrite porcelain was determined using an optical microscope.

Reference Example 49.5 mol% of iron oxide powder, 14.5 nickel oxide powder
Molar%, copper oxide powder 15 mole%, and zinc oxide powder 21 mole% were mixed with pure water in a ball mill, dried, and heat-treated at 720 ° C. for 4 hours to produce a ferrite having a spinel type crystal structure. Next, the ferrite was pulverized into a powder having a specific surface area of about 7 cm ² / g.

A mixture of ethyl alcohol, toluene and xylene (1: 1:
1) 100 parts by weight and 5 parts by weight of butyral resin were added to prepare a slurry, which was coated on a polyethylene terephthalate film by a doctor blade method and dried to obtain a ferrite green sheet having a thickness of 20 μm.

Next, a through hole having a diameter of 80 μm was formed by laser processing, and a silver conductor paste corresponding to the internal conductor was screen-printed on the sheet. The set chip size was a built-in one line of 1005 shape and four lines of 2010 shape, and the film thickness of the conductor at the time of printing and drying was about 10 μm. The conductor-printed sheets are stacked in a predetermined order, and 50
After pressure bonding under a pressure of 800 kg / cm ^{2 at} a temperature of 800 ° C., the material was cut, debindered, and fired at 900 ° C. for 2 hours to obtain a ferrite chip. In the fired body of this chip, the ferrite layer thickness was 15 μm and the electrode thickness was 8 μm. In this case, the volume resistance of the ferrite porcelain not including the internal conductor was 2 × 10 ⁷ Ωcm. Next, a ball medium having a diameter of 1 mm is filled to about 80% by volume of a barrel having a capacity of about 2 liters, 5 cm ³ of silicon carbide abrasive (GC # 250) is added, and a sufficient amount of water is added to add about 5 cm ³ of water. After polishing for 1 hour to produce 20,000 samples, an electrode paste was applied to each exposed portion of the internal conductor and baked at 670 ° C. to form external terminal electrodes.

Examples 1 to 5, Comparative Examples 1 and 2 20,000 samples obtained in Reference Examples were divided, and silicon carbide abrasives having different fineness in the range of # 3000 to # 15000 were used, and the same as in Reference Examples. Polishing was performed for 6 hours under the polishing conditions. Next, Watt bath (PH 4.2, bath temperature 50 ° C)
Nickel film 5μm by plating for 45 minutes using
And then plating using a Sn232 bath (PH7, bath temperature 20 ° C.) for 30 minutes to form a tin film 2
It was formed with a thickness of 0 μm. The surface roughness and plating spread of each sample thus obtained were measured and are shown in Table 1.

[0022]

[Table 1]

As is clear from this table, those having a surface roughness of 0.01 to 0.1 μm, particularly 0.02 to 0.05 μm, have a small plating elongation of 0.05 mm or less, and have a ferrite surface and a plating layer. Almost no peeling was observed.

[0024]

According to the present invention, it is possible to provide a high-quality inductor device that suppresses plating spread in an external terminal electrode and has no insulation failure between adjacent terminals.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a structural example of a multilayer ferrite inductor device.

FIG. 2 is a process chart of an example of the method of the present invention.

[Explanation of symbols]

 1,2 silver conductor pattern 3 through hole 4 ferrite

Claims (5)

[Claims] 1. A multilayer ferrite inductor device comprising an internal conductor, a ferrite porcelain and an external terminal electrode, wherein the surface roughness of the ferrite surface between the external terminal electrodes is adjusted to 0.01 to 0.1 μm. An inductor device, comprising: 2. A ferrite surface having a surface roughness of 0.02 to 0.02.
2. The inductor device according to claim 1, which is adjusted to 0.05 [mu] m. 3. After forming a through hole in a ferrite green sheet, a conductor forming paste is screen-printed to form a conductor pattern, the through hole is filled with a conductor paste, and then the printed ferrite green sheet is formed. After laminating a plurality of layers, after heating and compression, cut into arbitrary dimensions and subjected to a sintering process into a chip shape to obtain a ferrite structure having a coil-shaped internal conductor, and then bake the terminal electrode, on the surface of this terminal electrode In a method of manufacturing a multilayer ferrite inductor device by plating a metal conductor film, a polishing treatment is performed between a baking step of the terminal electrode and a plating step of the surface thereof to reduce the surface roughness of the ferrite surface between the external terminal electrodes. 0.0
A method comprising adjusting the thickness to 1 to 0.1 μm. 4. The ferrite surface has a surface roughness of 0.
4. The method according to claim 3, wherein the thickness is adjusted to 02 to 0.05 [mu] m. 5. The method according to claim 3, wherein the polishing is performed using fine silicon carbide powder.