JP2000295083A - Digital processing type signal extraction device - Google Patents

Abstract

(57) Abstract: A digital processing signal extraction circuit capable of easily extracting only desired data from an input signal by a digital circuit is provided. SOLUTION: When an input signal di is input, a noise signal is integrated by a first monostable multivibrator 3 using a set pulse width t to an H level, and NOT
The circuit 5 and the second monostable multivibrator 7 integrate using the pulse width t to make the H level. Regarding valid data, the first and second monostable multivibrators 3 and 7 detect rising and falling edges of valid data, and the OR circuit 11 determines the pulse width t corresponding to the falling and rising edges. The output signal C is generated, and the section corresponding to the noise component is at the L level in the D-flip-flop 9.
Sent as a level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital processing type signal extraction apparatus, and more particularly to an effective data removal apparatus for removing noise components when effective data is transmitted as an input signal at an interval through a signal line. The present invention relates to a digital processing type signal extraction device for easily extracting only data.

[0002]

2. Description of the Related Art Various filter circuits for extracting a signal having a frequency lower than a predetermined frequency have been proposed. For example, in optical communication, as shown in FIG. 4, data is generated on the transmission side, the data is demodulated for transmission, the laser LD is driven, and transmitted to the reception side via an optical fiber cable.

On the receiving side, a photodiode PD
And demodulated and used after filtering out unnecessary components of the received light signal.

In this filter, as shown in FIG. 5A, for example, a coil L and a capacitor are superposed. The coil L has a high resistance to high frequencies and a low resistance to low frequencies, and the capacitor C has a high resistance to low frequencies. On the other hand, by utilizing the fact that the resistance is low and the resistance becomes high with respect to the low frequency, the high frequency is blocked by the coil L and passed back through the capacitor C, thereby providing the low frequency as shown in FIG. In some cases, a low-pass filter that passes only the signal is used. That is, by using such a low-pass filter, unnecessary high-frequency noise can be removed and a normal signal component can be passed.

Further, as shown in FIG.
May be used. In this filter, a resistor R1, a resistor R2, a capacitor C1, and a capacitor C2 are connected to an operational amplifier AMP, a low-frequency component of an input signal is removed by the resistors R1, R2, and the capacitor C1, and a feedback signal from the operational amplifier AMP is removed. Coupling at C2, resistance R1 and resistance R
By returning to the connection point with No. 2, a sharp low-pass filter is formed.

[0006]

However, since the conventional filter circuit is an analog circuit, it is not easy to determine the values of the resistor, the capacitor and the like in order to remove unnecessary frequency components. was there.

Further, in designing an analog filter, the input / output impedance must be taken into consideration, so that there is a problem that the design cannot be made easily.

An input signal has a frequency band. To remove an unnecessary frequency band, it is necessary to determine a cutoff frequency and design a circuit. However, it is not easy to determine the cutoff frequency. There were challenges.

Further, to make a filter having very excellent filter characteristics, it is possible to mix an operational amplifier, a transistor, a resistor, a capacitor and the like, but the circuit becomes complicated.

In general, a filter often removes a weak signal noise, and when used in combination with a digital circuit, it cannot be mixed with a power supply circuit. There was a problem that the decision had to be made with due consideration.

On the other hand, when transmitting digital data from the transmitting side to the receiving side, the digital data is transmitted based on a predetermined communication protocol. That is, valid data is generally transmitted at intervals.

Therefore, as shown in FIG. 7, for example, it is desirable to remove unnecessary high frequency signals as noise on the receiving side and to extract only valid data.

In order to extract only the effective data, it is possible to remove unnecessary signal components by using a digital processor (DSP). However, the DSP is generally expensive and large. As a result, there is a problem that the circuit configuration on the printed circuit board becomes large.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a digital processing type signal extraction circuit capable of easily extracting only desired data from an input signal by a digital circuit.

[0015]

SUMMARY OF THE INVENTION The present invention relates to a digital processing type signal extracting apparatus for extracting valid data only from valid data transmitted at a fixed interval as an input signal and extracting only valid data from the input signal. Oscillating means receives an input signal, and oscillates as a first output signal a predetermined pulse width of the minimum pulse width of valid data every time the input signal is input.

At the same time, the second oscillating means inputs an input signal, and oscillates a second output signal having a pulse width different in phase with respect to the first output signal every time the input signal is input.

The OR means sends the OR of the first output signal from the first oscillating means and the second output signal from the second oscillating means, and the flip-flop means sends the OR signal from the OR means. An output signal obtained by ORing the input signal and an input signal are input. When the input signal is input, when an output signal obtained by ORing is input, the input signal is input until the output signal is input again. Output the logic state of the signal.

That is, when the frequency component of the input signal is equal to or less than the preset pulse width, the high frequency component is removed, and when the input signal exceeds the preset pulse width, it is regarded as valid data. Only this valid data is output.

[0019]

FIG. 1 is a schematic block diagram of a digital processing type signal extracting apparatus according to the present embodiment. The digital processing type signal extraction circuit 1 shown in FIG. 1 converts an input signal di composed of valid data Bi and unnecessary high frequency component noise Ai into
The signal is input to the first monostable multivibrator 3 which is retriggerable (retrigger function) at the rising of the input signal di to the trigger terminal, and the input signal di is inverted via the NOT circuit 5 to be retriggerable (retrigger function). Is input to the second monostable multivibrator 7. Further, the above-described input signal di is applied to the D flip-flop 9
Input to terminal (input terminal).

Further, the output signal A of the first monostable multivibrator 3 and the second monostable multivibrator 7
And an OR circuit 11 for sending a logical sum of the output signal B and the output signal B to the clock terminal of the D flip-flop 9 as an output signal C.

The first flip-flop circuit 3 inputs an input signal di to a trigger terminal, and when the rising of the output signal is detected, maintains the output at the H level for a predetermined time t. Further, when a rising is detected at the trigger terminal while the output is at the H level, the output is maintained at the H level for a predetermined time t from the time of detecting the rising, regardless of the previous pulse output.

The above-mentioned predetermined time t is the pulse width of the output, and the pulse width t = T / 2, where T: the minimum pulse width in the valid data Ai. The second monostable multivibrator 7 An input signal hi obtained by inverting the input signal di is input via the circuit 5, and when the rising of the input signal hi is detected, the output is maintained at the H level for a predetermined time t. Further, when a rising is detected at the trigger terminal while the output is at the H level, the output is maintained at the H level for a predetermined time t from the time of detecting the rising, regardless of the previous pulse output.

The above-mentioned predetermined time t is the pulse width of the output, and the pulse width t = T / 2, where T is the minimum pulse width in the valid data Ai. That is, the first monostable multivibrator 3 The second monostable multivibrator 7 is the same, and the NOT signal 5 and the second monostable multivibrator 7 use the input signal d.
A vibrator that changes the output to the H level when i falls is realized.

That is, by inserting the NOT circuit 5 in the preceding stage of the second monostable multivibrator 7, when the falling of the input signal di is detected, the output is maintained at the H level for a predetermined time t. Also, when a fall is detected at the trigger terminal while the output is at the H level, the output is maintained at the H level for a predetermined time t from the time when the fall is detected, regardless of the previous pulse output. ing.

The D flip-flop 9 is connected to the OR circuit 11
Inputs an output signal C, which is the logical sum of an output signal A of the first monostable multivibrator 3 and an output signal B of the second monostable multivibrator 7, to a clock terminal, and inputs an input signal di to a D terminal. Enter

That is, when the input signal di to the D terminal is at the H level, when the output signal C to the clock terminal is at the H level, the output is maintained at the H level, and the input signal di to the D terminal is at the H level. The output changes from H to L when the output signal C to the clock terminal rises to H level from the L level to the L level.

The operation of the digital processing type signal extraction circuit 1 configured as described above will be described below. FIG. 2 is a timing chart for explaining the operation of the digital processing type signal extraction circuit of the present embodiment.

For example, as shown in FIG. 2, it is assumed that valid data Ai is transmitted at intervals in the input signal di, and noise Bi of unnecessary high frequency components is contained in the interval. That is, the first half is an unnecessary part, and the second half is an effective part ((a) of FIG. 2).

The input signal di as shown in FIG.
Of the monostable multivibrator 3 and the second monostable multivibrator 7 are input to respective trigger terminals via NOT4 at the front end and to the input terminal D of the D flip-flop 9.

In the first monostable multivibrator 3,
The R and C circuits shown in FIG. 3 are externally provided, and an output signal having a pulse width determined by the resistor R and the capacitor C is transmitted.

That is, while the output pulse is at the H level,
When there is an input again, an output pulse having a pulse width determined by R and C is transmitted from the time when the second input is input regardless of the previous pulse output.

The pulse width t must satisfy the following condition: minimum pulse width T in the effective data Ai> output width t of the monostable multivibrator. It is assumed that t = T / 2.

Therefore, when an input signal di as shown in FIG. 2A is input to the first monostable multivibrator 3, the unnecessary rising frequency ka of the unnecessary high frequency component noise Bi at the first rising edge ka of FIG. As shown in (c), the output goes to H level, and is integrated by the R and C circuits externally attached to the first monostable multivibrator 3, and the H level of the pulse width t (t = T / 2) is obtained. Continue to output levels.

At this time, noise Bi having a very short cycle is input to the first monostable multivibrator 3.
Since the first monostable multivibrator 3 has a retriggerable function, every time the rising edge of the noise Bi is input to the reset terminal during this period, the output is integrated to an H level (pulse width t). As a result, as shown in FIG. 2C, the output keeps outputting the H level.

Immediately after the end of the noise Bi, the first monostable multivibrator 3 maintains the H level during the pulse width t at the rising edge Kn, and as shown in FIG. 2C. Even after the end of the noise Bi, the signal is delayed by the pulse width t to maintain the H level.

Each time the valid data Ai of the input signal di rises, the first monostable multivibrator 3 generates a pulse width t at its edge as shown in FIG.
Is output at the H level.

On the other hand, the above-mentioned input signal di is input to a NOT circuit 5, which inverts the input signal di as shown in FIG. Send out.

The second monostable multivibrator 7
Has a retriggerable function like the first monostable multivibrator 3.

Accordingly, the output signal hi of the NOT circuit 5 obtained by inverting the input signal di as shown in FIG.
Is input to the monostable multivibrator 7 at the first rising edge ha of the noise Bi of the unnecessary high frequency component as shown in FIG. Monostable multivibrator 7
The pulse width t (t
= T / 2).

At this time, noise Bi having a very short period is input to the second monostable multivibrator 7,
Since the monostable multivibrator 7 has a retriggerable function, every time a rising edge of the noise Bi is input to the reset terminal during this period, the integrated signal is integrated and the output becomes H level (pulse width t). As shown in FIG. 2D, the output continues to output the H level.

Immediately after the end of the noise Bi, at the rising edge hn, the second monostable multivibrator 7 maintains the H level for the pulse width t, so as shown in FIG. 2D. Even after the end of the noise Bi, the signal is delayed by the pulse width t to maintain the H level.

Each time the valid data Ai of the output signal hi of the NOT circuit 5 rises, the second monostable multivibrator 7 sets the H level of the pulse width t at its edge as shown in FIG. Sends the output of

That is, by the NOT circuit 5 and the second multivibrator 7, when the input signal di falls,
The output is maintained at the H level for a predetermined time t. Further, when a fall is detected at the trigger terminal while the output is at the H level, the output is maintained at the H level for a predetermined time t from the time of detection of the fall, regardless of the previous pulse output. Thus, the output signal B of the second monostable multivibrator 7 is set between the H level and the H level of the output signal A of the first monostable multivibrator 3.
The level is coming.

That is, the first monostable multivibrator 3 outputs the pulse width t at the rising edge of valid data.
, And the second monostable multivibrator 7 outputs an output signal B having a pulse width t at the falling edge of valid data.

Next, the OR circuit 11 performs an OR operation on the output signal A from the first monostable multivibrator 3 and the output signal B from the second monostable multivibrator 7 (FIG. 2E). Is output to the clock terminal of the D flip-flop 9.

That is, as shown in FIG. 2 (e), the output signal A and the output signal B are ORed to multiply the frequency by 2 to obtain a pulse corresponding to the rise and fall of the input signal di. An output signal C having a width t is transmitted.

Next, the D flip-flop 9 inputs the input signal di to the D terminal and inputs the output signal C from the OR circuit 11 to the clock terminal.

Since the output signal C from the OR circuit is input to the click terminal at the H level during the noise Bi of the input signal Di, even if the state at the D terminal repeats H and L at high speed due to the noise Bi. Since the clock has no change, the output of the D flip-flop keeps the previous state. Therefore, as shown in FIG. 2F, the output is maintained at H or L during the noise Bi. I do. It is desirable that the output be fixed at the L level during the input of the noise Bi.

Next, when the period of the valid data Ai of the input signal di comes and the output signal C from the OR circuit changes from L level to H level, the output becomes H level at the rising edge ga, and the input signal di. valid data Bi of di
Changes from the H level to the L level and the output signal C changes to the H level again, the output is inverted at the rising edge.

Therefore, the D flip-flop 9 is
(F), the valid data B of the input signal di
An output corresponding to the H level and L level of i is obtained.

That is, the output signal C, which is the OR of the output signal A of the first monostable multivibrator 3 and the output signal B of the second monostable multivibrator 7, is used as a clock, so that the input signal di Only valid data is extracted.

Therefore, when the digital processing type signal extraction device of the present embodiment is used for a filter for extracting a signal of an optical fiber, etc., the printed circuit board of the filter can be made small and inexpensive, and the signal transmitted by the optical fiber can be obtained. Only desired effective data can be easily extracted from the optical signal.

Although the input signal di is inverted by using the NOT circuit 5 in the above embodiment, the second monostable multivibrator changes the output to the H level when the input changes from the L level to the H level. In this case, the H level can be output at the falling edge of the input signal di.
The OT circuit 5 is unnecessary.

[0054]

As described above, according to the present invention, when an input signal composed of valid data and an unnecessary high-frequency noise signal is input, the noise signal is supplied to the first oscillation means and the second oscillation means in advance. Using the set pulse width (a predetermined amount of the minimum pulse width of valid data), the signal is integrated to the H level, and signals having a pulse width equal to or larger than the predetermined pulse width are set to the predetermined pulse width. , With the phase changed, and the logical sum is taken by the logical sum means.

That is, when the input signal is valid data having a pulse width equal to or greater than a preset pulse width, the rising and falling edges of the data are detected by the OR circuit.

Then, by the flip-flop means,
Between the rise and fall of valid data of the detected input signal, it is transmitted as H level.

Therefore, even if an input signal composed of valid data and an unnecessary high-frequency noise signal is input, it is possible to easily extract only valid data with a simple digital circuit. .

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a digital processing type signal extraction circuit of the present embodiment.

FIG. 2 is a timing chart illustrating an operation of the exemplary embodiment.

FIG. 3 is a configuration diagram of R and C circuits of the monostable multivibrator of the present embodiment.

FIG. 4 is a schematic configuration diagram of signal processing used for a conventional optical fiber.

FIG. 5 is a schematic configuration diagram of a conventional analog filter.

FIG. 6 is a schematic configuration diagram of a conventional analog filter using an operational amplifier.

FIG. 7 is an explanatory diagram for explaining a conventional problem.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Digital processing type signal extraction circuit 3 1st monostable multivibrator 5 NOT circuit 7 2nd monostable multivibrator 9 D flip-flop 11 OR circuit

Claims (4)

[Claims] 1. A digital processing type signal extraction device for extracting valid data only from valid data transmitted at regular intervals as an input signal and extracting the valid data from the input signal. A first oscillating means for oscillating a predetermined pulse width of the minimum pulse width of the valid data as a first output signal every time the input signal is input; A second oscillating means for oscillating a second output signal having the pulse width different in phase from the first output signal; a first output signal from the first oscillating means; AND means for transmitting a logical sum of the second output signal from the second oscillating means, an output signal obtained by performing a logical sum from the OR means, and the input signal, and the input signal is inputted. While typing,
A digital processing type signal extraction device, comprising: flip-flop means for outputting the logical state of the input signal when the output signal obtained by the logical sum is input until the output signal is input again. . 2. The first oscillating means inputs the input signal to a clock terminal, and when the state of the clock terminal changes from L level to H level, the first oscillating means outputs the first output signal of the pulse width. A first multivibrator having a retrigger function for transmitting, wherein the second oscillating means inputs a NOT circuit for inverting the input signal, and an inverted output of the NOT circuit to a trigger terminal; 2. A second monostable multivibrator having a retrigger function for sending a second output signal having the pulse width every time the state of the trigger terminal rises from L level to H level. Digital processing type signal extraction device. 3. The flip-flop circuit according to claim 1, wherein when the output signal from said OR circuit to said clock terminal changes from L level to H level after the logic of said input signal changes from H level to L level. 3. The digital processing type signal extraction device according to claim 1, wherein the output immediately maintains the output at the L level. 4. A pulse width set in the first and second oscillating means is equal to or smaller than a pulse width of the valid data and equal to or larger than a pulse width of a high frequency other than the valid data. 4. The digital processing type signal extraction device according to claim 1, 2 or 3.