JP2000295095A - Domino circuit with bipolar transistor - Google Patents

Abstract

(57) Abstract: A domino circuit capable of increasing the speed of a circuit, reducing the circuit area, making a domino circuit BiCMOS, and simplifying a process of mounting MOS and bipolar elements. A first p-type MOS transistor for precharging, a first n-type MOS transistor for logic configuration, a second p-type MOS transistor constituting an output inverter, and a second n-type MOS transistor. Connecting the bases of the respective bipolar transistors to the source electrodes of the second p-type and n-type MOS transistors 104a and 104b of the domino circuit having the MOS transistor 104b, connecting the emitters to third and fourth power supplies, The collector is the second p-type and n-type MOS transistor 104.
a, 104b are connected to the drain electrodes (output terminals).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a domino circuit using bipolar transistors and, more particularly, to a domino circuit using bipolar transistors which can be operated at high speed and reduced in area when integrated.

[0002]

2. Description of the Related Art Recently, a dynamic CMOS circuit (domino circuit) has been adopted as a main circuit of a processor to realize an operation speed of an operating frequency of 600 MHz to 1 GHz.
ISSCC'97 and ISSCC'98, and dynamic circuits have attracted attention. A dynamic circuit is a p-type MO
This is a circuit in which logic is constituted by several n-type MOS transistors for one S transistor. The dynamic circuit is
When viewed from the n-type MOS transistor, since the load is one p-type MOS transistor, the load capacity is small, and high-speed operation is possible as compared with the static CMOS circuit. Also,
A dynamic circuit has a feature that a circuit area can be reduced because the circuit can be configured with a small number of transistors. Conventional technologies related to basic domino circuits include, for example, the principle of CMOS VLSI design (Maruzen),
The technology described in 1997.1 4th edition, p141-144 and the like is known.

FIG. 2 is a diagram showing the configuration of a domino circuit according to the prior art, FIG. 3 is a diagram for explaining the delay time dependence of the gate width of a MOS transistor constituting an output inverter, and FIG.
FIG. 2 is a diagram for explaining the load dependence of the gate width and delay time of a MOS transistor constituting the entire domino circuit. Hereinafter, a domino circuit according to the prior art will be described with reference to FIGS. In FIG. 2, 001 is a domino circuit,
002 is a first pMOS transistor, 003 is a first nMOS transistor, 004 is an inverter, 011 is a load capacitance CL, 104a is a second pMOS transistor, and 104b is a second nMOS transistor.

The domino circuit 001 according to the prior art is shown in FIG.
As shown in the example, a first p-type MOS transistor 002 for precharging connected to first and second power supplies 006 and 007 for precharging and discharging.
And a plurality of first n-type MOS transistors 003 for logic configuration connected between the p-type MOS transistors not denoted by reference numerals and a second pMOS transistor 104a,
The output inverter 004 includes a second nMOS transistor 104b and a load capacitor CL011 connected to an output of the output inverter 104.

[0005] The domino circuit 001 according to the prior art configured as described above generally includes a first p-type MOS transistor 00 every 1/2 cycle of a CLK (clock) signal.
2 and the first n
The discharge by the logic of the type MOS transistor 003 is alternately performed. That is, the illustrated domino circuit 001
When the CLK signal (L level) is input to the first p-type MOS transistor 002, the first p-type MOS transistor
The dynamic node at the connection point between the S transistor 002 and the logic by the first n-type MOS transistor 003 is H
Become a level. This high-level signal is input to the output inverter 004, and as a result, the output of the domino circuit 001 goes low. After that, a data signal (H level) corresponding to the logic of the first n-type MOS transistor 003
Is input, the dynamic node goes low and the output of the inverter 004 goes high.

In the domino circuit, it is generally necessary to select an optimum gate width by tuning the gate width in order to maximize the performance. This will be described with reference to FIG. 3 illustrating the dependence of the gate width on the delay time.

FIG. 3 shows an example of the dependence of the gate width on the delay time. For example, the relationship between the gate width of the p-type MOS transistor constituting the output inverter and the delay time is determined by using the magnitude of the load capacitance (pF) as a parameter. It is shown. As can be seen from this figure, the relationship between the gate width of the p-type MOS transistor and the delay time is that the delay time does not decrease monotonically with the increase of the gate width, but the gate width with the shortest delay time is Exists. That is, there is a limit in increasing the speed of the domino circuit by increasing the gate width of the output inverter.

In order to further increase the speed of the domino circuit, it is necessary to increase the gate width of the entire domino circuit. The effectiveness of such a case will be described with reference to the characteristic diagram of the load dependency of the delay time shown in FIG.

In FIG. 4, the characteristics indicated by black circles indicate that the gate width of the p-type MOS transistor and the n-type MOS transistor of the domino logic unit is the standard width, and the gate width of the p-type MOS transistor forming the inverter is the standard width. 2
The characteristics of the delay time with respect to the load capacitance when the gate width of the n-type MOS transistor constituting the inverter is a standard width. The characteristics indicated by open triangles are the p-type MOS transistor and the n-type MOS transistor of the domino logic unit. Is twice the standard width, the gate width of the p-type MOS transistor forming the inverter is 4 times the standard width, and the gate width of the n-type MOS transistor forming the inverter is twice the standard width. 5 shows the characteristics of the delay time with respect to the load capacity of the first embodiment.

From the two characteristics described above, the delay time per unit capacitance (Ron resistance) is reduced to half when the gate width of the entire circuit is doubled compared to the standard gate width ( About twice as fast). However, in this case, the circuit area increases as the gate width increases.

In general, a CMOS circuit has a large delay time under a high load. Therefore, in order to transmit a signal at a high speed through a long distance wiring, a number of relay buffers (high load driving capacity inverters) are required. It is necessary to dispose them at millimeter intervals and transmit signals while shaping the waveform that has become dull due to the wiring load. The CMOS circuit enables high-speed signal propagation by such waveform shaping. But,
This arrangement of the relay buffer increases the circuit area.

On the other hand, a BiCMOS circuit having high integration of a CMOS circuit, low power consumption, and high speed of a bipolar transistor has also attracted attention. BiCMO
The S circuit is a circuit in which a bipolar element and a MOS element are mixedly mounted on the same substrate to have the functions of both elements. As a technique related to a conventional BiCMOS circuit, for example, a technique described in Japanese Patent Application Laid-Open No. 5-145402 is known. This prior art BiCM
The OS circuit uses a semiconductor circuit as a static CMOS circuit.
(Inverter) and PNP / NPN bipolar transistors to improve reliability and speed. The sectional structure of the bipolar transistor in this case is N (emitter), P (base), N
(Collector) has a vertical configuration.

[0013]

The above-described domino circuit according to the prior art has the following problems.

(1) In the domino circuit according to the prior art, the speed of the domino circuit is not sufficiently considered, and there is a limit to the speed of the circuit by setting the gate width of the output inverter of the domino circuit large. . That is, n-type MO
The discharge delay time by S logic and the H output delay time of the output inverter are in a trade-off relationship depending on the gate width of the inverter, so that the gate width of the inverter is large or small, and the input capacitance is large or small. ) And large or small drive capability (left and right delay time of the inverter). Prior art domino circuits, as a result,
There is a problem in that there is a gate width that minimizes the delay time, and it is difficult to increase the speed over a certain level. Further, the domino circuit according to the prior art has a problem that even if the gate width of the entire circuit is set twice as large as the standard, the delay time under a high load increases.

That is, the domino circuit according to the prior art is
There is a problem that it is difficult to increase the speed of the circuit by changing the gate width of the MOS transistor constituting the circuit.

(2) In the domino circuit according to the prior art, the area of the circuit is not sufficiently reduced, and when the speed of the circuit is increased by setting the gate width of the entire domino circuit large, the circuit area increases. In addition, the increase in signal transmission speed due to the arrangement of a relay buffer for transmitting a signal to a long-distance wiring also causes a problem that the circuit area increases.

That is, the domino circuit according to the prior art is
There is a problem in that the circuit area increases as the speed increases due to the increase in the gate width.

Also, the BiCMO according to the prior art described above is used.
The S circuit has a problem as described below.

(3) The BiCMOS circuit according to the prior art has a problem that consideration is not given to a combined circuit using a MOS transistor and a bipolar transistor in a dynamic circuit, and the high-speed performance of the bipolar transistor in the dynamic circuit is not utilized. And
There is a problem that high speed has not been achieved.

(4) In the prior art BiCMOS circuit, the process of mounting the CMOS element and the bipolar element on the same semiconductor substrate is not sufficiently considered, and the CMOS
The mounting process on the same substrate is complicated due to the difference between the transistor structure of the S element and the bipolar element between the horizontal type (drain, gate, source) and the vertical type (N emitter, P base, N collector). There is a problem, and there is a problem in the easiness of the mounting process on the same semiconductor substrate.

A first object of the present invention is to solve the above-mentioned problem (1) of the prior art and to provide a domino circuit combined with a bipolar transistor capable of increasing the speed of the domino circuit.

A second object of the present invention is to solve the above-mentioned problem (2) of the prior art and to provide a domino circuit combined with a bipolar transistor which can reduce the area of the domino circuit.

A third object of the present invention is to solve the above-mentioned problem (3) of the prior art and to provide a domino circuit combined with a bipolar transistor in a BiCMOS circuit, which makes full use of the high speed of the bipolar transistor. is there.

A fourth object of the present invention is to solve the above-mentioned problem (4) of the prior art and to combine a bipolar transistor with a MOS element and a bipolar element which can be easily mounted on the same semiconductor substrate. It is to provide a domino circuit.

[0025]

According to the present invention, the above-mentioned first method is provided.
A third object is to provide a first p-type MOS transistor for precharging whose source electrode is connected to a first power supply and a logic configuration for connecting a drain electrode of the first p-type MOS transistor. A first n-type MOS transistor;
The first p-type MOS transistor and the first n-type MO
The output signal at the connection point of the S transistor becomes the input signal,
A domino circuit including a second p-type MOS transistor and a second n-type MOS transistor, and an output inverter having a connection point between these MOS transistors as an output terminal, is used together with a bipolar transistor. In the domino circuit combined with bipolar transistors, the bipolar transistor is connected to a MOS transistor constituting the output inverter so as to amplify the output of the output inverter.

Specifically, the first to third objects are as follows: a first p-type MOS transistor for precharging whose source electrode is connected to a first power supply; A first n-type MOS transistor for logic configuration connected to the drain electrode;
An output signal at a connection point between the S transistor and the first n-type MOS transistor becomes an input signal, and includes a second p-type MOS transistor and a second n-type MOS transistor;
In a bipolar transistor combined domino circuit configured by using a bipolar transistor in combination with a domino circuit configured to include an output inverter having a connection point of these MOS transistors as an output terminal, the bipolar transistor includes the output inverter. The second that constitutes
PNP bipolar transistor and NPN bipolar transistor connected respectively to the p-type MOS transistor and the second n-type MOS transistor, and the base of the PNP bipolar transistor is the second p-type bipolar transistor.
The NPN bipolar transistor is connected to the source electrode of the N-type MOS transistor, the emitter is connected to the third power supply, and the collector is connected to the drain electrodes of the second p-type MOS transistor and the second n-type MOS transistor. Is connected to the source electrode of the second n-type MOS transistor, the emitter is connected to the fourth power supply, and the collector is the drain electrode of the second p-type MOS transistor and the second n-type MOS transistor. This is achieved by being connected to and configured.

According to the present invention, the fourth object is as follows.
This is achieved by forming the bipolar transistor by an SOI lateral bipolar transistor, and by forming the domino circuit formed by the bipolar transistor and the MOS transistor on the same semiconductor substrate.

Further, the fourth object is to form a MOS transistor and the bipolar transistor constituting the output inverter on the same semiconductor substrate, and
This is achieved by forming electrodes constituting each transistor in parallel with the semiconductor substrate to the same semiconductor diffusion thickness and by the same process.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a domino circuit using bipolar transistors according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram of a domino circuit with a bipolar transistor according to a first embodiment of the present invention.
In FIG. 1, 101 is a domino circuit, and 102 is a first p.
A MOS transistor, 103 is a first nMOS transistor, 104 is an output inverter, 105 is a bipolar transistor, 113 is a load capacitance CL, and other symbols are the same as those in FIG.

As shown in FIG. 1, a bipolar transistor combined domino circuit 101 according to a first embodiment of the present invention includes first and second precharge and discharge domino circuits.
A plurality of first n-type transistors for logic configuration connected between a first p-type MOS transistor 002 for precharging connected to the power supplies 106 and 107 of FIG. MOS transistor 103 and second
An output inverter 104 composed of a pMOS transistor 104a and a second nMOS transistor 104b;
NP / NPN bipolar transistors 105a, 10
5b and a load capacitance CL113.
In the illustrated domino circuit with bipolar transistors, a 3-AND circuit is constituted by a plurality of first n-type MOS transistors 103 for logic configuration.

In the circuit shown in FIG. 1, the p-type MOS transistor 102 has a source electrode 102a connected to a first power supply 106 for precharging, and an n-type MOS transistor 102.
The source electrode 103a of the lowermost transistor of the logic tree constituted by the OS transistor 103 is connected to a second power supply 107 for performing discharge via a p-type MOS transistor. P-type MOS transistor 104a and n-type MOS constituting output inverter 104
The source electrode of the transistor 104b is connected to a PNP or NPN bipolar transistor 10 for speeding up the circuit.
5a and 105b are connected to the base electrodes, respectively. Then, the p-type MO constituting the output inverter 104
S transistor 104a, n-type MOS transistor 10
The drain electrode 4b and the collector electrodes of the PNP and NPN bipolar transistors 105a and 105b are connected in common to form an output terminal.
Next, the operation of the domino circuit with bipolar transistors according to one embodiment of the present invention configured as described above will be described.

When the precharge CLK signal 108 is at the L level, the gate switch of the p-type MOS transistor 102 is turned on, and electric charges are accumulated in the dynamic node 109 from the first power supply VDD 106. Sufficient charges are accumulated in the dynamic node 109, and the dynamic node 109 becomes H level. With this H level signal, the n-type MOS transistor 104b of the output inverter 104 operates. n-type MOS transistor 104
By inputting an H level signal to the gate of b,
The gate is turned on, and the dynamic node 109 becomes N
Discharge is performed to the potential of the base of the PN transistor 105b, and an L-level signal is output.

When the discharge CLK signal 108 is at H level and the input data signals IN1, IN2, and IN3 are all at H level, all three gate switches of the n-type MOS transistor 103 are turned on and the second power supply is turned on. V
Since the SS 107 and the dynamic node 109 penetrate, the charge accumulated in the dynamic node 109 is extracted. When the charge of the dynamic node 109 is sufficiently extracted and the signal level becomes L, the output inverter 10
Four p-type MOS transistors 104a operate. When the signal L is input to the gate of the p-type MOS transistor 104a, the gate is turned on, the dynamic node 109 is charged to the potential of the base of the PNP transistor 105a, and an H-level signal is output.

PNP bipolar transistor 105a
Is operated by a switch of the output inverter 104, and p
When the type MOS transistor 104a is turned on,
Emitter and base currents flow from the third power supply VCC and turn on. Thereby, the bipolar transistor 105
The current a (emitter-collector) is amplified, and this current flows into the load capacitance CL113 to increase the charge accumulation speed. As a result, the operation speed of the circuit (inverter) can be increased. Bipolar transistor 10
5b also operates in the same manner as described above, increasing the discharge speed of the charge from the load capacitance CL113 and increasing the operation speed of the circuit (inverter).

The load dependency of the delay time of the bipolar transistor combined domino circuit according to the first embodiment of the present invention shown in FIG. 1 is shown as a characteristic curve by a black square in FIG. 4 described above.

As can be seen from the characteristic curve of the prior art shown in FIG. 4 and the characteristic curve of the embodiment of the present invention, the bipolar transistor combined domino circuit according to the first embodiment of the present invention reduces the gate width of the MOS transistor. Despite standard, delay time per unit capacitance (Ron resistance)
It can be seen that, compared to the prior art in which the gate width of the entire circuit is doubled, the load is about 15% smaller at high load and the delay time is shorter.

FIG. 5 is a diagram showing a cross-sectional structure of the domino circuit using bipolar transistors according to the first embodiment of the present invention described with reference to FIG. 1. This will be described below. In FIG. 5, reference numeral 201 denotes a semiconductor substrate. , 202 is S
iO2 film, 203 is thin silicon, 204 is p-type MOS
A transistor, 205 is a PNP bipolar transistor, 206 is a source, 207 is a gate, 208 is a drain, 209 is a collector, 210 is a base, 211 is an emitter, and 212 is an insulating film.

The cross-sectional structure shown in FIG. 5 corresponds to p-type MOS transistor 10 forming output inverter 104 shown in FIG.
4A and a cross section of an NPN bipolar transistor 105a. FIG. 5 shows a p-type MOS transistor 204 and a PNP bipolar transistor 205 in FIG.
Are the p-type MOS transistors 10 shown in FIG.
4a and the NPN bipolar transistor 105a. The n-type MOS transistor 104b and the PNP bipolar transistor 105b constituting the output inverter 104 have the same structure. Other parts are the same as in the case of the prior art. Next, the manufacturing method and structure will be described.

First, an SiO 2 film 2 is formed on a semiconductor substrate 201.
02, and a thin film silicon 203 is formed thereon. Next, the thin film silicon 203 formed on the SiO 2 film 202 is etched to form a MOS transistor 204.
, And a diffusion region for a bipolar element, which is a bipolar transistor 205.
Thereafter, impurities are introduced into silicon by ion implantation and annealing to form a source 206, a gate 207, a drain 208 of the MOS element 204, a collector 209, a base 210, and an emitter 211 of the bipolar element 205. Further, a metal electrode is formed to be ohmic-connected to these device electrodes. A metal electrode is attached to the gate 207 of the MOS element 204 via a gate insulating film.

As described above, when the circuit structure according to the first embodiment of the present invention is formed on a semiconductor substrate, the same structure except for the difference between the gate structure of the MOS element 204 and the base structure of the bipolar element 205 is obtained. Can be formed,
It can be formed by almost the same process. As a result, the MOS element and the bipolar element formed on the silicon substrate for diffusion can be formed with the same thickness, so that the bipolar transistor has a collector, a base, and an emitter arranged in parallel with the surface of the silicon substrate for diffusion. Will be formed.

As described above, in the first embodiment of the present invention, the first p-type MOS transistor for precharging whose source electrode is connected to the first power supply and the first p-type MOS transistor are provided.
A first n-type MOS transistor for logic configuration connected to the drain electrode of the S transistor;
The output signal at the connection point between the p-type MOS transistor and the first n-type MOS transistor becomes an input signal, and the second p-type M
A bipolar transistor comprising a domino circuit having an OS transistor and a second n-type MOS transistor and comprising an output inverter having a connection point between these MOS transistors as an output terminal and a bipolar transistor In the combined domino circuit, the bipolar transistors are a PNP bipolar transistor and an NPN bipolar transistor respectively connected to a second p-type MOS transistor and a second n-type MOS transistor constituting the output inverter; The base of the PNP bipolar transistor is connected to the source electrode of the second p-type MOS transistor, the emitter is connected to a third power supply, and the collectors are the second p-type MOS transistor and the second n-type MOS transistor. Drain with The NPN bipolar transistor has a base connected to a source electrode of the second n-type MOS transistor, an emitter connected to a fourth power supply, and a collector connected to the second p-type MOS transistor and the second p-type MOS transistor. Is connected to the drain electrode of the n-type MOS transistor.

According to the first embodiment of the present invention having such a configuration, since the current amplification characteristics of the bipolar transistor can be used, the amount of current supplied to the output load capacitor CL can be increased, and the electric charge can be increased. Can be increased, so that the speed of the domino circuit can be increased.

According to the first embodiment of the present invention,
By using the standard gate width without setting the gate width of the entire circuit large, the current amplification characteristics of the bipolar transistor are equivalent to the load characteristics when the gate width is set to twice the standard gate width. (15%
Since the above (high speed) performance can be obtained, the gate width does not need to be set larger than necessary, and an increase in circuit area can be prevented.

Furthermore, according to the first embodiment of the present invention, even if a relay buffer is not used, the high-speed operation under a high load due to the combined use of the bipolar transistors enables the 2 mm
If the distance is about the same (equivalent to CL = 0.4 pF), a sufficiently high-speed transmission of the signal is possible, so that the relay buffer can be eliminated and the circuit area can be reduced accordingly. .

According to the first embodiment of the present invention,
The bipolar element used in the first embodiment of the present invention is:
By using the SOI lateral bipolar transistor, the MOS device and the bipolar device can be formed with the same thickness in the diffusion silicon substrate.
Since the collector, base, and emitter can be formed in parallel with the surface of the silicon substrate for diffusion, the MOS transistor and the bipolar transistor can be mounted on the same semiconductor substrate, thereby facilitating the mounting process. Becomes

Further, according to the first embodiment of the present invention, the process of forming the bipolar element and the domino circuit constituted by the MOS transistors on the same semiconductor substrate can be integrated. The frequency of manufacturing in separate processes can be reduced, and the mounting process can be facilitated. Further, according to the first embodiment of the present invention, since a circuit can be formed by an integrated process on the same semiconductor substrate, it is possible to arrange the MOS element and the bipolar element at very close positions. Thus, the wiring distance can be shortened, and high-speed circuit can be achieved.

As described above, the first aspect of the present invention described above
According to the embodiment, the speed of the domino circuit can be improved, the circuit area can be prevented from increasing due to the speeding up of the circuit, and the MOS element and the bipolar element can be easily mounted on the same substrate. The effect of being able to be mounted on a vehicle can be obtained.

FIG. 6 is a diagram showing a configuration of a bipolar combined domino circuit according to a second embodiment of the present invention. In FIG. 6, reference numeral 301 denotes a domino circuit combined with a bipolar transistor;
Is a first p-type MOS transistor, 303 is a first n-type MOS transistor for logic configuration, 304 is an output inverter, 304a is a second p-type MOS transistor, 30
4b is a second n-type MOS transistor, and 305a is a PN
P bipolar transistor and 305b are NPN bipolar transistors.

In the domino circuit 301 with bipolar circuit according to the second embodiment of the present invention shown in FIG. 6, the first n-type MOS transistor 303 for logic configuration has 3 wide 3-3.
The configuration is the same as that of the first embodiment of the present invention shown in FIG. 1 except for the configuration of the −3 AND-OR circuit, and the circuit operation is the same as that of the first embodiment.

According to the second embodiment of the present invention, the same effects as those of the first embodiment of the present invention described above can be obtained. In particular, in the case of complex logic, the number of n-type MOSs for logic configuration increases, and therefore, in the prior art, the gate width obtained by doubling the entire circuit and the standard gate width are approximately 2 in terms of area. Although a double difference occurs, according to the second embodiment of the present invention, it is possible to obtain an effect that it is possible to further prevent an increase in the circuit area due to an increase in the speed of the circuit.

[0052]

As described above, according to the present invention, P
The bases of the bipolar transistors NP and NPN are respectively connected to p-type and n-type M
By connecting to the source electrode of the OS transistor,
It is possible to obtain an effect that the load characteristics of the circuit can be improved (higher speed) and an increase in the circuit area can be prevented.

Further, according to the present invention, by forming the bipolar element with an SOI lateral bipolar transistor, the process for mounting the MOS element and the bipolar element on the same semiconductor substrate can be simplified. By forming the element and the domino circuit composed of the MOS transistors on the same semiconductor substrate, it is possible to obtain an effect that the easiness of the process and the high-speed operation of the circuit can be maintained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a domino circuit combined with a bipolar transistor according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a domino circuit according to the related art.

FIG. 3 is a diagram illustrating the delay time dependency of the gate width of a MOS transistor constituting an output inverter.

FIG. 4 is a diagram for explaining load dependence of a gate width and a delay time of a MOS transistor constituting the entire domino circuit;

FIG. 5 is a diagram showing a cross-sectional structure of the domino circuit combined with bipolar transistors according to the first embodiment of the present invention described with reference to FIG. 1;

FIG. 6 is a diagram illustrating a configuration of a domino circuit using bipolar transistors according to a second embodiment of the present invention;

[Explanation of symbols]

001 Conventional domino circuit 101, 301 Bipolar combined domino circuit 002, 102, 302 First p-type MOS transistor 102a Source electrode 102b Drain electrode 003, 103, 303 First n-type MOS transistor 004, 104, 304 Output inverter 004a , 104a, 304a Second p-type MOS transistor 004b, 104b, 304b Second n-type MOS transistor 105a, 305a PNP bipolar transistor 105b, 305b NPN bipolar transistor 006, 106, 306 First power supply (VDD) 007, 107, 307 Second power supply (VSS) 008, 108, 308 CLK signal 009, 109, 309 Dynamic node 010, 110, 310 Data signal 111, 311 Third power supply VCC) 112, 312 Fourth power supply (VEE) 011, 113, 313 Load capacitance CL 012, 114, 314 Output terminal, 201 Semiconductor substrate 202 SiO2 203 Thin-film silicon for diffusion 204 P-type MOS transistor 205 Bipolar transistor 206 Source 207 Gate 208 Drain 209 Collector 210 Base 211 Emitter 210 Insulating film

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03K 17/04 H01L 29/78 614 17/567 H03K 17/56 E 19/08 (72) Inventor Onuchi Kyohiro 1-280 Higashi-Koigakubo, Kokubunji-shi, Tokyo In the Central Research Laboratory, Hitachi, Ltd. AB10 AC05 BA16 BC15 CA04 DA13 DA14 DA15 5F110 AA01 AA04 BB03 BB20 CC01 DD05 DD13 FF02 GG02 GG13 HK09 HK14 NN62 NN80 5J055 AX02 AX44 BX16 CX10 CX26 DX04 DX05 DX13 DX14 DX22 DX56 DX79 EX07 G19 EZ21 EZ21 EZ21 CC20 DD05 DD13 DD36 DD40 DD51 EE11 EE13 FF01 FF10 GG04 GG14 HH01 KK02 KK03

Claims (5)

[Claims] A first p-type MOS transistor having a source electrode connected to a first power supply and a first p-type MOS transistor for logic configuration connected to a drain electrode of the first p-type MOS transistor; N-type MOS transistor, the first p-type MOS transistor and the first n-type MOS transistor.
The output signal at the connection point of the S transistor becomes the input signal,
A domino circuit including a second p-type MOS transistor and a second n-type MOS transistor, and an output inverter having a connection point between these MOS transistors as an output terminal, is used together with a bipolar transistor. In the domino circuit combined with a bipolar transistor, the bipolar transistor is connected to a MOS transistor forming the output inverter so as to amplify the current of the output of the output inverter. circuit. 2. A first p-type MOS transistor for precharging having a source electrode connected to a first power supply, and a first p-type MOS transistor for logic configuration connected to a drain electrode of the first p-type MOS transistor. N-type MOS transistor, the first p-type MOS transistor and the first n-type MOS transistor.
The output signal at the connection point of the S transistor becomes the input signal,
A domino circuit including a second p-type MOS transistor and a second n-type MOS transistor, and an output inverter having a connection point between these MOS transistors as an output terminal, is used together with a bipolar transistor. In the domino circuit combined with a bipolar transistor, the bipolar transistor comprises a second p-type MOS transistor and a second n-type M which constitute the output inverter.
A PNP bipolar transistor and an NPN bipolar transistor connected to the OS transistor, respectively, wherein the base of the PNP bipolar transistor is the second
Is connected to the source electrode of the p-type MOS transistor, the emitter is connected to the third power supply, and the collector is connected to the drain electrodes of the second p-type MOS transistor and the second n-type MOS transistor. The base of the bipolar transistor is the second
, The emitter is connected to the fourth power supply, and the collector is connected to the drain electrodes of the second p-type MOS transistor and the second n-type MOS transistor. A domino circuit combined with a bipolar transistor. 3. The method according to claim 1, wherein the bipolar transistor is an SOI.
3. The domino circuit combined with a bipolar transistor according to claim 1, wherein the domino circuit is a lateral bipolar transistor. 4. The bipolar transistor and the MO
4. The domino circuit combined with a bipolar transistor according to claim 1, wherein the domino circuit composed of S transistors is formed on the same semiconductor substrate. 5. The MOS transistor constituting the output inverter and the bipolar transistor are formed on the same semiconductor substrate, and the electrodes constituting each transistor have the same semiconductor diffusion thickness in parallel with the semiconductor substrate. 5. The domino circuit with bipolar transistors according to claim 1, wherein the domino circuits are formed by the same process.