JP2000299319A - Electrode pad for semiconductor element, semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To operate at high frequencies and implement low noise figure by providing electrode pads with a function of either suppressing the propagation of thermal noise voltage generated by a substrate resistor or suppressing the generation of thermal noise voltage. SOLUTION: An electrode pad 27 is provided via an insulating film 23 directly under a region where a semiconductor element 22 is not formed on a semiconductor substrate 21, and a metallic layer or a silicide film 24 is provided right under the pad 27 via the film 23 between the substrate 21 and the pad 27. In addition, the metallic layer or the film 24 is held at a predetermined potential. Therefore, this arrangement utilizes the properties that a resistor generates a thermal noise voltage and the magnitude of the thermal noise voltage increases with the increasing resistance value, and that a capacitor does not generate thermal noise. In this case, rather than the capacitance between the pad 27 and the substrate 21 being not reduced, the thermal noise voltage attributable to the conductivity of the substrate 21 is suppressed by applying a predetermined voltage to the metallic layer or the film 24.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a low noise MOSFE.
The present invention relates to a structure of an electrode pad for realizing T.

[0002]

2. Description of the Related Art A compound FET has been used as a transistor for a low noise amplifier. This is because these transistors have excellent low noise characteristics. However, in order to reduce the cost, Si-MOSF transistors widely used in LSIs are used as transistors.
It is preferable to use ET (hereinafter abbreviated as MOSFET) as a transistor for low noise.

However, the low-noise characteristics of MOSFETs are about 1 dB worse than compound FETs, and are currently not used. That is, the main cause of the poor noise characteristics of the MOSFET is that the Si substrate used is conductive. In other words, the wiring and the electrode pad form a parasitic capacitance with the conductive substrate, and a parasitic circuit network of a parasitic capacitance-substrate resistance-ground is connected to the input portion of the gate via the parasitic capacitance. Furthermore, since the resistance of the substrate generates thermal noise, the thermal noise voltage of the substrate is input to the gate through the parasitic circuit network. Therefore, the original noise figure is degraded by this amount.

Therefore, in order to improve the noise figure of the MOSFET, it is only necessary to reduce the influence of the parasitic circuit network or to adopt a structure in which the thermal noise of the substrate is not transmitted. For this purpose, as one method, the parasitic capacitance of the wiring and the electrode pad, particularly, the parasitic capacitance of the electrode pad may be reduced because the latter has a large influence. Another method is to provide a conductive layer between the pad and the substrate and fix it at a constant potential so that the thermal noise voltage of the substrate is not transmitted.

On the other hand, the conventional pad structure forms an electrode pad on a semiconductor substrate via an insulating film.
This is a method widely used in ordinary LSI,
Since the parasitic capacitance between the conductive substrate and the conductive substrate is large, the influence of the thermal noise of the conductive substrate is unavoidable, which is not preferable for low noise applications. JP-A-59-43536 is known as another method proposed in the conventional pad structure.

That is, in the publication, a metal film which completely covers an element region via an interlayer insulating film is formed, an electrode pad is formed thereon, and a hole for electrically connecting the pad and the element is formed. It has been proposed to open a metal film for wiring. In this case, the purpose is not to eliminate the influence of thermal noise of the substrate, but to form a pad on the element to reduce the IC area by the amount of the pad, and change the voltage of the pad to electrically affect the element. This is to prevent it.

FIG. 5 shows the structure. That is, FIG.
As shown in the cross-sectional view of FIG. 5A, a transistor 52 is formed near the surface of a substrate 51, and a metal film 54 is formed so as to cover these transistors via an insulating film 53. The connection of the wiring to the electrode pad 56 is performed by forming a contact plug 55 by making a hole in a part of the metal film 54. Further, as shown in the plan view of FIG. 5B, the metal film 54 covers most of the substrate.

[0008]

However, simply forming an electrode pad on an Si substrate via an interlayer insulating film as in the above-mentioned conventional method results in a large parasitic capacitance between the substrate and the substrate, and noise. The index is large. Also, in the method in which a metal film is formed on most of the substrate, the thermal noise of the substrate can be reduced even with this structure, but the original purpose is to prevent the voltage change of the pad from affecting the transistor. For this reason, the metal film is formed over a wide area, the parasitic capacitance between the electrode pad and the transistor is large, and there is a serious problem that it is difficult to operate at a high frequency.

In addition, Japanese Patent Application Laid-Open No. 2-296348 discloses a semiconductor device in which a conductive film is formed under an electrode pad with an interlayer insulating film interposed therebetween. There is no description of the suppression technology.
Japanese Patent Application Laid-Open No. 7-97602 discloses that when an organic coating film is used between an electrode pad and an internal wiring portion, a groove or a hole is provided in the electrode pad so that a step is not generated. However, there is no description about a technique for suppressing a thermal noise voltage.

Further, Japanese Patent Application Laid-Open No. 7-106524 describes a semiconductor integrated circuit in which a high impurity concentration diffusion layer grounded in an alternating current is formed in a surface region of a semiconductor substrate below an electrode pad. However, there is no description about the technique for suppressing the thermal noise voltage in the same manner as described above. on the other hand,
Japanese Patent No. 2550248 discloses a configuration of an electrode pad formed on the surface of an insulating film containing boron. Japanese Patent Application Laid-Open No. Hei 10-247664 discloses a structure in which an interlayer insulating film including a spin-on glass film is interposed. Although a configuration in which an electrode pad is formed is described, none of the publications describes a technique for suppressing a thermal noise voltage.

Accordingly, it is an object of the present invention to provide an electrode pad for a semiconductor device, which can solve the above-mentioned disadvantages of the prior art, can operate at a high frequency, and can realize a low noise figure, and a method of manufacturing the same.

[0012]

The present invention employs the following technical configuration to achieve the above object. That is, according to a first aspect of the present invention, there is provided an electrode pad formed on an insulating film which is connected to a semiconductor element formed on a semiconductor substrate via an insulating film. A semiconductor element electrode pad provided with a function of suppressing propagation of a thermal noise voltage generated by a substrate resistance or suppressing the generation of the thermal noise voltage. An electrode pad formed on the insulating film and connected to the semiconductor element formed on the insulating film via the insulating film, and a part of the electrode pad has a mesh structure. It is.

According to a third aspect of the present invention, there is provided an electrode pad formed on an insulating film which is connected to a semiconductor element formed on a semiconductor substrate via an insulating film. This is a semiconductor element electrode pad in which a metal layer or a silicide film is disposed directly below the electrode pad via the insulating film. Further, as a fourth aspect according to the present invention, a step of forming an appropriate semiconductor element on a semiconductor substrate, a step of forming an interlayer insulating film on the substrate, a step of forming the semiconductor element and one end thereof on the interlayer insulating film Forming a contact plug whose parts are electrically connected and the other end of which is located near the surface of the interlayer insulating film, forming an electrode pad having a mesh structure at least partially on the surface of the interlayer insulating film And a step of connecting the electrode pad and an end of the contact plug. A fifth aspect of the present invention is a method for manufacturing an electrode pad for a semiconductor element. Forming a metal layer or a silicide layer in a region other than a region where the semiconductor element is formed on the substrate; forming an interlayer on the substrate; Forming a Enmaku, forming a contact plug the other end with one end portion and the semiconductor element to the interlayer insulating film are electrically connected are positioned in the vicinity of the surface of the interlayer insulating film,
Forming an appropriate electrode pad on the surface of the interlayer insulating film and facing the metal layer or the silicide layer; and connecting the electrode pad to an end of the contact plug. This is a method for manufacturing the configured electrode pad for a semiconductor element.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The electrode pad for a semiconductor element and the method of manufacturing the same according to the present invention employ the above-mentioned technical configuration, so that the thermal noise caused by the conductive silicon (Si) substrate is reduced. The amount entering the input section can be greatly reduced, and as a result, it has become possible to obtain a semiconductor device electrode pad which can operate the semiconductor device at a high frequency and realize a low noise figure.

[0015]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a semiconductor device according to an embodiment of the present invention; That is, FIG. 1 is a plan view showing the outline of the configuration of a specific example of the electrode pad for a semiconductor element according to the present invention.
For example, the electrode pad 4 is formed on the insulating film 6 and is connected to the semiconductor element 2 which is a transistor via the insulating film 6. The electrode pad 4 has a thermal noise voltage generated by the substrate resistance. The semiconductor device electrode pad 4 is shown to be provided with a function of suppressing propagation or suppressing the generation of the thermal noise voltage, and a more detailed configuration of the specific example includes the electrode pad 4. At least partially has the network structure 7.

In this embodiment, the electrode pad 4
Is connected to the semiconductor element 2 via an appropriate wiring 3 formed on the insulating film 6, a contact plug 5 formed in the insulating film 6, and the wiring 3 connected to the contact plug 5. ing. That is, according to the specific example of the present invention, the electrode pad 4 is formed on the semiconductor substrate 1 with the insulating film 6 interposed therebetween. Can be substantially reduced, and the capacitance between the pad and the substrate is reduced, thereby increasing the impedance of this portion.

For this reason, when the thermal noise voltage due to the resistance of the substrate 1 reaches the element via this capacitance, the noise voltage transmitted by the larger impedance can be reduced. Therefore, if such a mesh structure 7 is used, the area covered by the outer periphery is almost the same as that of the conventional electrode pad, so that the difficulty in bonding the package and the electrode pad with the metal wire does not increase as compared with the related art.

Next, another specific example of the semiconductor device electrode pad 4 according to the present invention will be described with reference to FIG.
That is, in this specific example, the semiconductor element 22 composed of a transistor or the like and the insulating film 23 formed on the semiconductor substrate 21 are formed.
An electrode pad 27 formed on the insulating film 23 connected via the insulating film 23 via the insulating film 23 directly below the electrode pad 27.
Reference numeral 4 denotes a semiconductor device electrode pad on which the semiconductor device is disposed.

In this embodiment, it is desirable that the metal layer or the silicide film 24 is maintained at a constant potential. The connection between the semiconductor element 22 formed on the substrate 21 and the electrode pad 27 may be the same as the connection method in the above specific example. That is, in this specific example, the semiconductor element 22 on the semiconductor substrate 21
An electrode pad 27 is provided via an insulating film 23 directly above an area where no pad is formed, and a metal layer or a silicide film 24 is provided between the semiconductor substrate 1 and the pad 27 via the insulating film 23. The metal layer or the silicide film 24 is provided immediately below, and is maintained at a constant potential.

Accordingly, in the semiconductor device electrode pad 27 having the above configuration, it is the resistance that generates the thermal noise voltage, and the magnitude of the thermal noise voltage increases with the resistance value. The capacitor utilizes the characteristic that thermal noise does not occur. In this case, instead of reducing the capacitance between the electrode pad 27 and the substrate 21,
The object is to suppress a thermal noise voltage caused by the conductivity of the substrate by applying a constant voltage to the metal film or the silicide film 24.

Although the metal film or the silicide film 24 itself slightly generates thermal noise, the noise is not a problem because the resistance is much smaller than that of the substrate 21. Since the metal film or the silicide film 24 has a low resistance and is kept at a constant voltage, the influence of the thermal noise of the substrate 21 is cut off here. As a result, the parasitic circuit connected to the transistor 22 is eventually only the parasitic capacitance and the metal film or the silicide film 24,
No thermal noise enters the transistor from this circuit.

Further, since the metal film or the silicide film 24 is not formed directly above the transistor 22, no parasitic capacitance is formed between the transistor 22 and the transistor. Furthermore, since the metal film or the silicide film 24 has the same area as the electrode pad, the capacitance between them is not so large, and the high-frequency characteristics of the transistor are only slightly deteriorated.

Further, according to this embodiment, the semiconductor substrate 21
An electrode pad 27 is provided directly above a region where the semiconductor element 22 is not formed via an insulating film 23, and a silicide layer or a metal film 24 is provided immediately below the pad 27. Metal layer or silicide film 24
May be provided on the surface of the semiconductor substrate 21 and maintained at a constant potential.
May be disposed inside the insulating film 23 at a distance from the surface and kept at a constant potential.

In any of the configurations, only the manufacturing process is different, and the function as the semiconductor device electrode pad is the same. Which configuration is adopted is arbitrary. In this specific example, when the silicide layer 24 is formed, it can be formed by simultaneously silicifying the substrate surface immediately below the pad when the gate, source and drain are silicided. When forming the metal film 24,
If any part is formed of metal at the time of transistor formation, they can be formed at the same time. If metal is not used for the transistor part, it is necessary to add a separate metal forming step.

Next, another specific example of the semiconductor device electrode pad according to the present invention will be described in detail with reference to FIG. That is, in this specific example, a configuration substantially the same as the configuration in the above specific example is adopted, except that at least one of the electrode pad 27 or the metal layer or the silicide film 24 is used. At least a part of the semiconductor element electrode pad 27 having the network structure 7.

This configuration assumes that the inside of both the electrode pad 27 and the metal film or the silicide film 24 is uniform, but the electrode pad 27 and one or both of the metal film and the silicide film 24 are meshed. By adopting the structure, the parasitic capacitance itself between them can also be reduced. Further, when the metal film side or the silicide film 24 has a network structure, the electrical connection with the substrate can be made slightly, so that the noise characteristic is slightly deteriorated, but this is not a serious problem. By reducing the capacity, it is possible to use up to high frequencies.

As still another specific example of the present invention,
This is a semiconductor device having an electrode pad having the structure shown in each of the above specific examples. Next, a more specific example of the semiconductor device electrode pad of the present invention will be described in the form of an example. FIG. 1 is a plan view showing a structure of an electrode pad according to a first specific example of the present invention.

A MOSFET is formed as a transistor 2 near the surface of a P-type silicon substrate 1 and an interlayer insulating film 6 is formed.
The wiring 3 is connected to the gate electrode portion by using. The electrode pad 4 connected to the wiring 3 formed on the surface of the interlayer insulating film 6 is formed in a mesh shape with aluminum, and has an outer shape of 50 μm square. The details of the structure of the mesh are, in this specific example, rectangular aluminum having a width of about 4 μm and a length of 50 μm arranged vertically and horizontally at intervals of 4 μm.

The width and the interval can be freely set up to the limit of the aluminum forming technology (miniaturization). Further, the thickness of the electrode pad 4 and the wiring 3 is 1 μm here, but may be thinner or thicker. The material of the electrode pad 4 is aluminum in this embodiment, but may be other metal such as copper. The transistor here is a MOSFET
However, another element such as a bipolar transistor may be used.

The method for forming the electrode pads having a mesh structure in this embodiment can use, for example, a patterning technique used in forming a normal wiring. Also, in this specific example, in order to show the features of the present invention, the wiring 3 and the MO 3 are assumed to be connected to the electrode pads 4.
The SFET 2 is illustrated in a simplified manner. However, other transistors, passive elements such as inductors and capacitors, wells, and elements that are not directly related to the present invention, such as element isolation, are not shown.

Next, the second embodiment of the present invention will be described with reference to FIG. 2. FIG. 2A is a sectional view showing the structure of an electrode pad 27 as this embodiment. FIG. 2 (B) is a plan view thereof. P-type silicon substrate 21
A MOSFET is formed as a transistor 22 near the surface of the contact plug 25 using an interlayer insulating film 23.
The wiring 26 is connected to the gate electrode section through the gate.

The electrode pad 27 is connected to the wiring 26. The electrode pad 27 is formed in a place where there is no transistor below in the substrate. Metal layer 24 is formed in interlayer insulating film 23 and directly below electrode pad 27.
This metal layer is formed with the same area as the electrode pad 27, and has a size slightly protruding from the electrode pad 27 in a plan view.

In this specific example, the wiring 26 and the electrode pad 27
Is about 1 μm, and the thickness of the metal layer 24 is 0.5 μm.
But These thicknesses can be any thickness as long as they are not extremely thin (on the order of 100 angstroms). Further, the relationship between the area of the electrode pad 27 and the area of the metal layer 24 is preferably the same. However, even if the area is different by several times, there is no significant problem unless an element is provided directly below the metal layer 24.

In this specific example, the wiring 26, the electrode pad 27
The metal layers 24 are all made of aluminum, but may be made of metal such as copper. Further, in this specific example, in order to show the features of the present invention, wirings and MOSFETs are shown in a simplified manner as being connected to electrode pads. However, other transistors, passive elements such as inductors and capacitors, wells, and elements that are not directly related to the present invention, such as element isolation, are not shown.

Next, a third embodiment according to the present invention will be described in detail with reference to FIG. 3. FIG. 3 shows an example in which the electrode pad 27 and the metal pad in the embodiment shown in FIG. Layer 24
One or both of them have a mesh structure 7. FIG.
In FIG. 2, only the electrode pads 27 having the mesh structure 7 are shown, and the mesh-shaped electrode pads 27 are connected to the wiring 26.

The details of the structure of the mesh are, in this embodiment, rectangular aluminum having a width of about 4 μm and a length of 50 μm arranged vertically and horizontally at intervals of 4 μm. These widths and intervals can be freely set up to the limit of the aluminum forming technology (miniaturization). In addition, the network structure may have various other shapes. In short, the network structure may have a size capable of reducing the capacity by forming a gap in the inside and having good reproducibility for bonding the wiring from the package.

On the other hand, FIG. 4A is a sectional view showing the structure of an electrode pad according to a fourth embodiment of the present invention.
(B) is a plan view thereof. In the figure, a MOSFET as a transistor 42 is provided near the surface of a silicon substrate 41.
Is formed, and a wiring 46 is connected to the gate electrode portion via a contact plug 45 using an interlayer insulating film 43.

An electrode pad 47 is connected to the wiring 46. The electrode pad 47 is formed in a place where there is no transistor below in the substrate. The metal layer or the silicide layer 44 is formed on the surface of the substrate 41 and directly below the electrode pad 47. The area of this layer is formed to be approximately the same as the area of the electrode pad 47, and is slightly larger than the electrode pad 47 in a plan view.

In this specific example, the wiring 46 and the electrode pad 47
Is about 1 μm, and the thickness of the metal layer, the silicide film or the silicide layer 44 is 0.1 μm. These thicknesses can be any thickness as long as they are not extremely thin (on the order of 100 angstroms). Further, the relationship between the area of the electrode pad 47 and the area of the metal layer or the silicide layer 44 is preferably the same, but even if greatly different, there is no significant problem. In this embodiment, the wiring 46, the electrode pad 47 and the metal layer 44 are all made of aluminum, but may be made of metal such as copper. Although the silicide layer is made of Co silicide, it may be made of silicide with titanium or platinum.

Also, in this embodiment, in order to show the features of the present invention, the wiring and the M are assumed to be connected to the electrode pads.
The OSFET is illustrated in a simplified manner. However, other transistors, passive elements such as inductors and capacitors, wells, and elements that are not directly related to the present invention, such as element isolation, are not shown. Further, in the present invention, in the fourth specific example described above, one or both of the electrode pad 47 and the metal layer or the silicide layer 44 can have the mesh structure 7.

As the details of the mesh structure 7, in this specific example, a rectangular shape having a width of about 4 μm and a length of 50 μm may be arranged vertically and horizontally at intervals of 4 μm. These widths and intervals can be freely set up to the limit of the aluminum forming technology (miniaturization). In addition, the network structure may have various other shapes. In short, the network structure may have a size capable of reducing the capacity by forming a gap in the inside and having good reproducibility for bonding the wiring from the package.

As is evident from the specific examples of the semiconductor device electrode pad according to the present invention described above, the method for manufacturing the semiconductor device electrode pad according to the present invention includes, for example, Forming a semiconductor element, forming an interlayer insulating film on the substrate, electrically connecting one end of the semiconductor element to the interlayer insulating film, and connecting the other end to the surface of the interlayer insulating film. Forming an electrode pad having a network structure at least in part on the surface of the interlayer insulating film, and connecting the electrode pad to an end of the contact plug. It is desirable to be comprised from.

In the method of manufacturing an electrode pad for a semiconductor element according to the present invention, the electrode pad is provided on the surface of the interlayer insulating film corresponding to the position of the semiconductor element formed on the substrate. It is desirable that it be formed in a region excluding the region. Further, as another configuration example of the method for manufacturing a semiconductor element electrode pad according to the present invention, a step of forming an appropriate semiconductor element on a semiconductor substrate, a region other than a region where the semiconductor element is formed on the substrate Forming a metal layer or a silicide layer in a region, forming an interlayer insulating film on the substrate, electrically connecting one end of the semiconductor element to the interlayer insulating film and the other end of the semiconductor element. Forming a contact plug located in the vicinity of the surface of the interlayer insulating film, forming an appropriate electrode pad on the surface of the interlayer insulating film and facing the metal layer or the silicide layer, and It is also desirable that the method comprises a step of connecting the electrode pad and an end of the contact plug.

Similarly, as another specific example of the method of manufacturing the electrode pad for a semiconductor element according to the present invention, a step of forming an appropriate semiconductor element on a semiconductor substrate and a step of forming an interlayer insulating film on the substrate are described. Forming a metal layer or a silicide layer on the interlayer insulating film in a region other than the region where the semiconductor element is formed on the substrate; forming another interlayer insulating film on the interlayer insulating film Forming a contact plug in which one end of the semiconductor element is electrically connected to the interlayer insulating film and the other end is located near the surface of the interlayer insulating film; A step of forming an appropriate electrode pad on the upper side and facing the metal layer or the silicide layer, and a step of connecting the electrode pad to an end of the contact plug. It is also preferred to have been made.

In the above specific example of the method for manufacturing the electrode pad for a semiconductor element, the electrode pad excludes the interlayer insulating film surface region corresponding to the arrangement position of the semiconductor element formed on the substrate. It is desirable to be formed in the area.

[0046]

According to the structure of the electrode pad of the present invention, the amount of thermal noise caused by the conductive Si substrate entering the input portion of the transistor can be greatly reduced.
When a μm MOSFET was used, the noise figure was reduced by about 1 dB at 6 GHz as compared with the conventional pad structure.

[Brief description of the drawings]

FIG. 1A is a plan view of a structure of a semiconductor device using an electrode pad according to a first embodiment of the present invention, and FIG. 1B is a cross-sectional view thereof.

FIG. 2A is a sectional view of a structure of a semiconductor device using an electrode pad according to a second embodiment of the present invention, and FIG.
(B) is a plan view thereof.

FIG. 3A is a sectional view of a structure of a semiconductor device using an electrode pad according to a third embodiment of the present invention;
(B) is a plan view thereof.

FIG. 4A is a cross-sectional view of a structure of a semiconductor device using an electrode pad according to a fourth embodiment of the present invention.
(B) is a plan view thereof.

FIG. 5 is a schematic cross-sectional view and a plan view of a structure of a conventional semiconductor device.

[Explanation of symbols]

 1, 21, 41, 51 ... substrate 2, 22, 42, 52 ... transistor 3, 26, 46 ... wiring 4, 27, 47, 56 ... electrode pad 5, 25, 45, 55 ... contact plug 6, 23, 43 , 53: Interlayer insulating film 7: Network structure 24, 44, 54: Metal layer or silicide layer

Claims (12)

[Claims] 1. An electrode pad formed on an insulating film connected to a semiconductor element formed on a semiconductor substrate via an insulating film, wherein the electrode pad is formed by heat generated by substrate resistance. An electrode pad for a semiconductor element, which has a function of suppressing propagation of a noise voltage or suppressing generation of the thermal noise voltage. 2. An electrode pad formed on an insulating film which is connected to a semiconductor element formed on a semiconductor substrate via the insulating film, and at least a part of the electrode pad has a mesh structure. The electrode pad for a semiconductor element according to claim 1, wherein: 3. An electrode pad formed on the insulating film, which is connected to a semiconductor element formed on the semiconductor substrate via the insulating film, and directly below the electrode pad via the insulating film. 2. The electrode pad for a semiconductor device according to claim 1, wherein a metal layer or a silicide film is disposed. 4. The electrode pad for a semiconductor device according to claim 3, wherein the metal layer or the silicide film is maintained at a constant potential. 5. The electrode pad for a semiconductor element according to claim 3, wherein at least a part of the electrode pad or at least one of the metal layer and the silicide film has a mesh structure. 6. The electrode pad, the metal layer, or the silicide film, a position in the insulating film layer corresponding to a position immediately above a position where the semiconductor element formed on the semiconductor substrate is not arranged, or 6. The electrode pad for a semiconductor element according to claim 1, wherein said electrode pad is provided at a position of an upper surface portion of said insulating film. 7. A semiconductor device comprising the electrode pad according to any one of claims 1 to 6. 8. A step of forming an appropriate semiconductor element on a semiconductor substrate, a step of forming an interlayer insulating film on the substrate,
A step of forming a contact plug in which the semiconductor element and one end thereof are electrically connected to the interlayer insulating film and the other end is located near the surface of the interlayer insulating film, at least on the surface of the interlayer insulating film; A method for manufacturing an electrode pad for a semiconductor element, comprising: a step of forming an electrode pad having a network structure in part; and a step of connecting the electrode pad to an end of the contact plug. 9. The semiconductor device according to claim 8, wherein said electrode pad is formed in a region excluding a surface region of said interlayer insulating film corresponding to an arrangement position of a semiconductor element formed on said substrate. The manufacturing method of the electrode pad for semiconductor elements as described in the above. 10. A step of forming an appropriate semiconductor element on a semiconductor substrate, a step of forming a metal layer or a silicide layer in a region other than a region where the semiconductor element is formed on the substrate, Forming an interlayer insulating film, forming a contact plug in which one end of the semiconductor element is electrically connected to the interlayer insulating film and the other end is located near the surface of the interlayer insulating film, A step of forming an appropriate electrode pad on the surface of the interlayer insulating film and facing the metal layer or the silicide layer; and a step of connecting the electrode pad to an end of the contact plug. A method for manufacturing an electrode pad for a semiconductor device, comprising the steps of: 11. A step of forming an appropriate semiconductor element on a semiconductor substrate, a step of forming an interlayer insulating film on the substrate, and the semiconductor element on the substrate is formed on the interlayer insulating film. Forming a metal layer or a silicide layer in a region other than the region, forming another interlayer insulating film on the interlayer insulating film, electrically connecting the semiconductor element and one end thereof to the interlayer insulating film, Forming a contact plug, the other end of which is located near the surface of the interlayer insulating film, and a suitable electrode pad on the surface of the interlayer insulating film and opposed to the metal layer or the silicide layer. Forming an electrode pad, and connecting the electrode pad to an end of the contact plug. 12. The electrode pad according to claim 10, wherein said electrode pad is formed in a region excluding a surface region of said interlayer insulating film corresponding to an arrangement position of a semiconductor element formed on said substrate. Or the method for producing an electrode pad for a semiconductor element according to item 11.