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JP2000208536A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method

Info

Publication number
JP2000208536A
JP2000208536A JP11005834A JP583499A JP2000208536A JP 2000208536 A JP2000208536 A JP 2000208536A JP 11005834 A JP11005834 A JP 11005834A JP 583499 A JP583499 A JP 583499A JP 2000208536 A JP2000208536 A JP 2000208536A
Authority
JP
Japan
Prior art keywords
circuit board
semiconductor elements
resin composition
printed circuit
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11005834A
Other languages
Japanese (ja)
Inventor
Makoto Kuwamura
誠 桑村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nitto Denko Corp
Original Assignee
Nitto Denko Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitto Denko Corp filed Critical Nitto Denko Corp
Priority to JP11005834A priority Critical patent/JP2000208536A/en
Publication of JP2000208536A publication Critical patent/JP2000208536A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

(57)【要約】 【課題】配線回路基板上に複数の半導体素子を一度に樹
脂封止することができる生産効率の高い半導体装置の製
法を提供する。 【解決手段】配線回路基板2の配線電極3に、所定間隔
に位置決めされた複数の半導体素子5の電極部7を当接
させて上記配線回路基板2に上記複数の半導体素子5を
搭載した半導体素子5搭載済み配線回路基板2を準備す
る。ついで、封止用樹脂組成物である円柱状のペレット
8を上記複数の半導体素子5の間に載置して加熱溶融す
ることにより、上記配線回路基板2と上記複数の半導体
素子5との空隙に、上記溶融状態の封止用樹脂組成物を
充填し硬化させ、上記配線回路基板2と複数の半導体素
子5で形成される個々の空隙をそれぞれ樹脂封止する。
An object of the present invention is to provide a method of manufacturing a semiconductor device with high production efficiency, in which a plurality of semiconductor elements can be resin-sealed at a time on a printed circuit board. A semiconductor having a plurality of semiconductor elements mounted on the wiring circuit board by contacting electrode portions of the plurality of semiconductor elements positioned at predetermined intervals with wiring electrodes of the wiring circuit board. The wired circuit board 2 on which the element 5 is mounted is prepared. Next, a columnar pellet 8 which is a sealing resin composition is placed between the plurality of semiconductor elements 5 and heated and melted to form a gap between the printed circuit board 2 and the plurality of semiconductor elements 5. Then, the sealing resin composition in the molten state is filled and cured, and the individual voids formed by the printed circuit board 2 and the plurality of semiconductor elements 5 are each resin-sealed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、複数の半導体素子
をフェースダウン構造でマザーボード、あるいはドータ
ーボードに一度に多数個樹脂封止することのできる半導
体装置の製法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which a plurality of semiconductor elements can be resin-sealed at a time on a mother board or a daughter board in a face-down structure.

【0002】[0002]

【従来の技術】近年、半導体デバイスの性能向上に伴う
要求として、半導体素子をフェースダウン構造で、配線
回路が形成されたマザーボード、あるいはドーターボー
ドに実装される方法(フリップチップ方式、ダイレクト
チップアタッチ方式等)が注目されている。このような
方法により得られる半導体装置は、1枚の配線回路基板
に1個の半導体素子を載置した後、上記配線回路基板と
半導体素子との空隙を、液状樹脂材料や固形樹脂材料等
の各種封止材料で封止することにより製造していた。
2. Description of the Related Art In recent years, there has been a demand for improvement in the performance of semiconductor devices, in which a semiconductor element is mounted on a mother board or a daughter board having a wiring circuit formed in a face-down structure (flip chip method, direct chip attach method). Etc.) are attracting attention. In a semiconductor device obtained by such a method, after one semiconductor element is mounted on one printed circuit board, a gap between the printed circuit board and the semiconductor element is filled with a liquid resin material or a solid resin material. It was manufactured by sealing with various sealing materials.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、各配線
回路基板に1個の半導体素子を搭載して樹脂封止すると
いう上記のような従来の製法は、生産効率が低く、その
作業性等に問題があり、より効率良く半導体装置を製造
する方法が要望されている。
However, the above-mentioned conventional manufacturing method, in which one semiconductor element is mounted on each wiring circuit board and sealed with a resin, has low production efficiency and has problems in workability and the like. Therefore, there is a demand for a more efficient method for manufacturing a semiconductor device.

【0004】本発明は、このような事情に鑑みなされた
もので、配線回路基板上に複数の半導体素子を一度に樹
脂封止することができる高効率の半導体装置の製法の提
供をその目的とする。
The present invention has been made in view of such circumstances, and an object of the present invention is to provide a method of manufacturing a highly efficient semiconductor device capable of sealing a plurality of semiconductor elements on a printed circuit board at a time. I do.

【0005】[0005]

【課題を解決するための手段】上記の目的を達成するた
め、本発明の半導体装置の製法は、配線回路基板の配線
電極に、所定間隔で位置決めされた複数の半導体素子の
電極部を当接させて上記基板に上記複数の半導体素子を
搭載した半導体素子搭載済み配線回路基板を準備し、常
温で固体の封止用樹脂組成物を上記複数の半導体素子の
うちの任意の半導体素子の間に載置して加熱溶融するこ
とにより、上記配線回路基板と上記複数の半導体素子と
の空隙に、上記溶融状態の封止用樹脂組成物を充填し硬
化させ、少なくとも、上記配線回路基板と複数の半導体
素子で形成される個々の空隙をそれぞれ樹脂封止すると
いう構成をとる。
In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises the steps of contacting electrode portions of a plurality of semiconductor elements positioned at predetermined intervals with wiring electrodes of a printed circuit board. A semiconductor element-mounted wiring circuit board is prepared by mounting the plurality of semiconductor elements on the substrate, and a solid sealing resin composition at room temperature is interposed between any of the plurality of semiconductor elements. By mounting and melting by heating, the gap between the printed circuit board and the plurality of semiconductor elements is filled with the molten sealing resin composition and cured, and at least the printed circuit board and the plurality of semiconductor elements are cured. A configuration is adopted in which individual voids formed in the semiconductor element are each resin-sealed.

【0006】すなわち、本発明は、配線回路基板の配線
電極に、所定間隔で位置決めされた複数の半導体素子の
電極部を当接させて上記基板に上記複数の半導体素子を
搭載した半導体素子搭載済み配線回路基板を準備する。
ついで、常温で固体の封止用樹脂組成物を上記複数の半
導体素子のうちの任意の半導体素子の間に載置して加熱
溶融することにより、上記配線回路基板と上記複数の半
導体素子との空隙に、上記溶融状態の封止用樹脂組成物
を充填し硬化させ、少なくとも、上記配線回路基板と複
数の半導体素子で形成される個々の空隙をそれぞれ樹脂
封止する。このようにして基板上に複数の半導体素子が
搭載されたものを、半導体素子毎に切断することにより
半導体装置を製造するものである。このため、多数の半
導体素子を一度に樹脂封止することができ、生産効率が
向上する。
That is, according to the present invention, there is provided a semiconductor device having a plurality of semiconductor elements mounted on the substrate by bringing the electrode portions of a plurality of semiconductor elements positioned at predetermined intervals into contact with the wiring electrodes of the printed circuit board. Prepare a printed circuit board.
Then, by placing a sealing resin composition that is solid at normal temperature between any of the plurality of semiconductor elements and melting by heating, the wiring circuit board and the plurality of semiconductor elements are bonded together. The voids are filled with the molten sealing resin composition and cured, and at least individual voids formed by the printed circuit board and the plurality of semiconductor elements are each resin-sealed. In this way, a semiconductor device is manufactured by cutting a semiconductor device having a plurality of semiconductor elements mounted on a substrate for each semiconductor element. For this reason, many semiconductor elements can be resin-sealed at once, and the production efficiency is improved.

【0007】また、本発明の半導体装置の製法では、上
記溶融状態の封止用樹脂組成物が、上記配線回路基板と
複数の半導体素子で形成される個々の空隙を充填すると
ともに、上記複数の半導体素子間の隙間も充填して、上
記配線回路基板と複数の半導体素子で形成される個々の
空隙と、上記複数の半導体素子間の隙間をそれぞれ樹脂
封止することも容易となる。
In the method of manufacturing a semiconductor device of the present invention, the sealing resin composition in the molten state fills the individual voids formed by the printed circuit board and the plurality of semiconductor elements, and forms the plurality of semiconductor elements. Filling the gaps between the semiconductor elements also facilitates resin sealing of the individual gaps formed by the printed circuit board and the plurality of semiconductor elements and the gaps between the plurality of semiconductor elements.

【0008】そして、本発明の半導体装置の製法では、
上記常温で固体の封止用樹脂組成物が、上記配線回路基
板と複数の半導体素子で形成される個々の空隙と、複数
の半導体素子間の隙間を充填しうる量である場合、上記
空隙および隙間の樹脂封止が容易かつ確実になされるよ
うになる。
In the method of manufacturing a semiconductor device according to the present invention,
The solid-state sealing resin composition at room temperature, the individual gaps formed by the wiring circuit board and the plurality of semiconductor elements, when the amount can fill the gap between the plurality of semiconductor elements, the gap and The resin sealing of the gap is easily and reliably performed.

【0009】本発明の半導体装置の製法において、予
め、上記配線回路基板の外周縁に溶融状態の封止用樹脂
組成物流出防止用の枠を設けるとともに、上記配線回路
基板と半導体素子との空隙に溶融状態の封止用樹脂組成
物を充填した後、配線回路基板から上記枠を取り除く工
程を備えることにより、溶融状態の封止用樹脂組成物
が、上記配線回路基板と複数の半導体素子で形成される
個々の空隙の充填、および、上記複数の半導体素子間の
隙間の充填を均一に行うことができるようになる。
In the method for manufacturing a semiconductor device according to the present invention, a frame for preventing the molten sealing resin composition from flowing out is provided in advance on an outer peripheral edge of the wiring circuit board, and a gap between the wiring circuit board and the semiconductor element is provided. After filling the sealing resin composition in the molten state, the step of removing the frame from the wiring circuit board, the sealing resin composition in the molten state, the wiring circuit board and a plurality of semiconductor elements It is possible to uniformly fill the formed voids and the gaps between the plurality of semiconductor elements.

【0010】そして、上記常温で固体の封止用樹脂組成
物が、150℃でのゲルタイムが5〜30分間という特
性(X)を有することにより、硬化反応がゆるやかに生
起し、配線回路基板と半導体素子間の空隙に封止用樹脂
組成物が均一に充填されるようになる。また、封止作業
の条件設定を容易に行うことができるようになる。
[0010] Since the encapsulating resin composition which is solid at room temperature has a characteristic (X) of a gel time at 150 ° C of 5 to 30 minutes, a curing reaction occurs slowly, and the resin composition for the wiring circuit board is formed. The gap between the semiconductor elements is uniformly filled with the sealing resin composition. Further, it is possible to easily set the conditions for the sealing operation.

【0011】[0011]

【発明の実施の形態】つぎに、本発明の実施の形態を詳
しく説明する。
Next, embodiments of the present invention will be described in detail.

【0012】本発明の半導体装置の製法において、少な
くとも配線回路基板と半導体素子との空隙を樹脂封止す
る際に用いられる封止用樹脂組成物としては、特に限定
するものではなく各種の封止材料が用いられるが、一般
には、エポキシ樹脂組成物があげられる。
In the method of manufacturing a semiconductor device according to the present invention, the sealing resin composition used for sealing at least the gap between the wiring circuit board and the semiconductor element with a resin is not particularly limited, and various sealing methods are used. Although a material is used, an epoxy resin composition is generally used.

【0013】上記エポキシ樹脂組成物は、エポキシ樹脂
(a成分)と、硬化剤(b成分)と、無機質充填剤(c
成分)とを用いて得られるものであり、常温で固体を示
し、例えば、圧延シート化したものを所望の各種形状に
打ち抜きペレットとして供される。なお、上記常温と
は、具体的に20℃をいう。
The epoxy resin composition comprises an epoxy resin (a component), a curing agent (b component), and an inorganic filler (c
Component) and shows a solid at normal temperature. For example, a rolled sheet is punched into various desired shapes and provided as pellets. In addition, the said normal temperature specifically means 20 degreeC.

【0014】上記エポキシ樹脂(a成分)としては、特
に限定するものではなく従来公知の各種エポキシ樹脂が
あげられるが、なかでも、結晶性エポキシ樹脂、常温で
固体の2官能エポキシ樹脂を用いることが好ましく、特
に好ましくは、低溶融粘度という観点から、下記の一般
式(1),式(2),式(3)で表される構造のエポキ
シ樹脂があげられる。これらは単独でもしくは2種以上
併せて用いられる。
The epoxy resin (component (a)) is not particularly limited, and includes various conventionally known epoxy resins. Among them, a crystalline epoxy resin and a bifunctional epoxy resin that is solid at room temperature are used. Preferably, particularly preferably, from the viewpoint of low melt viscosity, an epoxy resin having a structure represented by the following general formulas (1), (2), and (3) is exemplified. These may be used alone or in combination of two or more.

【0015】[0015]

【化1】 Embedded image

【0016】[0016]

【化2】 Embedded image

【0017】[0017]

【化3】 Embedded image

【0018】上記式(1)〜(3)で表される構造のエ
ポキシ樹脂において、特にエポキシ当量150〜230
g/eqで、融点60〜160℃のものを用いることが
好ましい。
In the epoxy resin having the structure represented by the above formulas (1) to (3), the epoxy equivalent is preferably 150 to 230.
It is preferable to use those having a melting point of 60 to 160 ° C. in g / eq.

【0019】上記エポキシ樹脂(a成分)とともに用い
られる硬化剤は、上記エポキシ樹脂の硬化剤として作用
するものであって、酸無水物系硬化剤、フェノール樹脂
等が用いられ、なかでもフェノール樹脂が好適に用いら
れる。
The curing agent used together with the epoxy resin (component (a)) acts as a curing agent for the epoxy resin, and includes an acid anhydride-based curing agent, a phenol resin and the like. It is preferably used.

【0020】上記フェノール樹脂としては、特に限定す
るものではなく通常用いられているものが用いられ、特
に低粘度のものを用いることが好ましく、具体的にはノ
ボラック型フェノール樹脂が好ましく用いられる。そし
て、上記ノボラック型フェノール樹脂のなかでも、水酸
基当量が80〜200g/eqで、軟化点が80℃以下
のものを用いることが好ましい。より好ましくは、水酸
基当量90〜180g/eqで、軟化点50〜70℃で
ある。特に好ましくは水酸基当量100〜170g/e
qで、軟化点55〜65℃である。
The phenol resin is not particularly limited, and a commonly used phenol resin is preferably used. In particular, a low-viscosity phenol resin is preferably used, and specifically, a novolak-type phenol resin is preferably used. And among the above novolak-type phenol resins, it is preferable to use those having a hydroxyl equivalent of 80 to 200 g / eq and a softening point of 80 ° C. or lower. More preferably, the hydroxyl group equivalent is 90 to 180 g / eq and the softening point is 50 to 70 ° C. Particularly preferably, the hydroxyl equivalent is 100 to 170 g / e.
In q, the softening point is 55-65 ° C.

【0021】上記エポキシ樹脂(a成分)と硬化剤(b
成分)の配合割合は、硬化剤としてフェノール樹脂を用
いる場合、エポキシ樹脂中のエポキシ基1当量に対しフ
ェノール樹脂中の水酸基当量を0.5〜1.6の範囲に
設定することが好ましい。より好ましくは0.8〜1.
2の範囲に設定することである。
The epoxy resin (a component) and the curing agent (b)
When a phenol resin is used as a curing agent, the mixing ratio of the component) is preferably set such that the hydroxyl group equivalent in the phenol resin is in the range of 0.5 to 1.6 with respect to 1 equivalent of the epoxy group in the epoxy resin. More preferably 0.8-1.
2 is set.

【0022】上記a成分およびb成分とともに用いられ
る無機質充填剤(c成分)としては、特に限定するもの
ではなく従来公知の各種無機質充填剤が用いられ、例え
ば、シリカ粉末、タルク、アルミナ粉末等があげられ、
これら単独でもしくは2種以上併せて用いられる。なか
でも、シリカ粉末、とりわけ、溶融シリカ粉末を用いる
ことが好ましく、特に球状溶融シリカ粉末を用いること
が好ましい。そして、上記球状溶融シリカ粉末におい
て、平均粒径が0.2〜20μmのものを用いることが
好ましく、特に好ましくは0.2〜5μmである。さら
に、最大粒径が75μm以下のものを用いることが好ま
しい。特に好ましくは最大粒径が5〜24μmである。
すなわち、最大粒径が75μmを超えると、配線回路基
板と半導体素子間〔封止用樹脂組成物を用いて樹脂封止
される空隙〕の充填が不可能になる場合があるからであ
る。また、このような観点から、この無機質充填剤(c
成分)の最大粒径は、配線回路基板と半導体素子間〔封
止用樹脂組成物を用いて樹脂封止される空隙〕の距離の
1/2以下に設定することが好ましい。より好ましくは
1/10〜1/3である。すなわち、最大粒径を1/2
以下に設定することにより、上記基板と半導体素子間へ
の溶融状態の封止用樹脂組成物の充填が、ボイド等が生
じず良好になされるようになるからである。
The inorganic filler (component c) used together with the components a and b is not particularly limited, and various conventionally known inorganic fillers can be used. Examples thereof include silica powder, talc, and alumina powder. Given
These may be used alone or in combination of two or more. Among them, it is preferable to use silica powder, especially fused silica powder, and it is particularly preferable to use spherical fused silica powder. The spherical fused silica powder preferably has an average particle size of 0.2 to 20 μm, particularly preferably 0.2 to 5 μm. Further, it is preferable to use one having a maximum particle size of 75 μm or less. Particularly preferably, the maximum particle size is 5 to 24 μm.
That is, if the maximum particle size exceeds 75 μm, it may not be possible to fill the space between the printed circuit board and the semiconductor element (a void that is resin-sealed using the sealing resin composition). From such a viewpoint, the inorganic filler (c
The maximum particle size of the component is preferably set to be not more than 以下 of the distance between the printed circuit board and the semiconductor element (the gap to be resin-sealed using the sealing resin composition). More preferably, it is 1/10 to 1/3. That is, the maximum particle size is reduced to 1/2.
This is because the setting described below allows the filling of the sealing resin composition in a molten state between the substrate and the semiconductor element to be performed favorably without generating voids or the like.

【0023】上記無機質充填剤(c成分)の含有量は、
封止用樹脂組成物全体の50重量%以上80重量%未満
の範囲に設定することが好ましい。特に好ましくは60
重量%〜75重量%の範囲である。すなわち、無機質充
填剤(c成分)の含有量が50重量%未満では、封止用
樹脂硬化物の特性、特に線膨張係数との差が大きくなっ
て、樹脂硬化物や半導体素子にクラック等の欠陥を発生
させる。また、80重量%以上では、封止用樹脂の溶融
粘度が高くなることから充填性が悪くなるからである。
The content of the inorganic filler (component (c)) is as follows:
It is preferable to set the content within a range of 50% by weight or more and less than 80% by weight of the entire sealing resin composition. Particularly preferably 60
% By weight to 75% by weight. That is, when the content of the inorganic filler (component (c)) is less than 50% by weight, the difference between the properties of the cured resin for sealing, particularly the linear expansion coefficient, becomes large, and cracks and the like are caused on the cured resin and the semiconductor element. Generate defects. On the other hand, if the content is 80% by weight or more, the meltability of the encapsulating resin is increased, so that the filling property is deteriorated.

【0024】本発明に用いられる封止用樹脂組成物に
は、上記a〜c成分以外に、必要に応じて、各種シリコ
ーン化合物(側鎖エチレングライコールタイプジメチル
ポリシロキサン等)等の低応力化剤、難燃剤、ポリエチ
レン系ワックスやカルナバワックス等のワックス、各種
シランカップリング剤(γ−グリシドキシプロピルトリ
メトキシシラン等)等のカップリング剤等を適宜に配合
してもよい。
In the sealing resin composition used in the present invention, in addition to the above components a to c, if necessary, various types of silicone compounds (such as side chain ethylene glycol type dimethylpolysiloxane) can be used to reduce stress. Agents, flame retardants, waxes such as polyethylene wax and carnauba wax, and coupling agents such as various silane coupling agents (such as γ-glycidoxypropyltrimethoxysilane) may be appropriately blended.

【0025】上記難燃剤としては、ブロム化エポキシ樹
脂等があげられ、これに三酸化二アンチモン等の難燃助
剤等が用いられる。
Examples of the flame retardant include a brominated epoxy resin, and a flame retardant aid such as diantimony trioxide is used.

【0026】本発明に用いられる封止用樹脂組成物は、
例えばつぎのようにして得られる。すなわち、前記a成
分、b成分およびc成分を外部より加熱可能な金属容器
の中で150℃で30分〜1時間混合し、120℃に温
度を下げた後、反応性調整のための触媒を添加し、均一
混合する。ついで、上記均一混合した後圧延シート化
し、これを所望の形状に打ち抜いてペレット化すること
により得られる。
The sealing resin composition used in the present invention comprises:
For example, it is obtained as follows. That is, the component a, the component b, and the component c are mixed at 150 ° C. for 30 minutes to 1 hour in a metal container that can be externally heated, and the temperature is reduced to 120 ° C. Add and mix homogeneously. Then, the mixture is uniformly mixed and then formed into a rolled sheet, which is punched into a desired shape and pelletized.

【0027】上記反応性調整のために配合される触媒と
しては、特に限定するものではなく従来から硬化促進剤
として用いられるものがあげられる。例えば、トリフェ
ニルホスフィン、テトラフェニルホスホニウムテトラフ
ェニルボレート、2−メチルイミダゾール等があげられ
る。
The catalyst blended for the above-mentioned adjustment of the reactivity is not particularly limited, and may be a catalyst conventionally used as a curing accelerator. For example, triphenylphosphine, tetraphenylphosphonium tetraphenylborate, 2-methylimidazole and the like can be mentioned.

【0028】上記各成分の混合およびペレットの作製方
法については上記方法に限定するものではなく、例え
ば、上記混合においては、2軸ロール、3軸ロール等を
用いることも可能である。また、上記ペレットの作製方
法についても、シート状にした後に打ち抜く以外に、注
型法等の方法を用いることができる。
The method of mixing the above components and producing pellets is not limited to the above method. For example, in the above mixing, a biaxial roll, a triaxial roll, or the like may be used. As for the method of producing the pellets, a method such as a casting method can be used instead of punching after forming into a sheet.

【0029】上記ペレットの形状については、特に限定
するものではなく、立方体、円柱等、その目的、配線回
路基板および半導体素子の大きさ形状等に応じて適宜に
設定される。
The shape of the pellet is not particularly limited, and may be appropriately set according to the purpose, the size and shape of the printed circuit board and the semiconductor element, and the like.

【0030】つぎに、本発明の半導体装置の製法を、図
面に基づいて説明する。
Next, a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.

【0031】まず、図1(A)および(B)に示すよう
に、片面に配線回路が形成された配線回路基板2上の配
線電極3に、所定間隔で位置決めされた複数の半導体素
子5の下面に形成された金属製の電極(バンプ)7を当
接させ、複数の半導体素子5と配線回路基板2とを接合
することにより配線回路基板2に複数の半導体素子5を
それぞれ搭載する。なお、図1(A)では、配線回路基
板2上に16個の半導体素子5が配設されているがこの
数に限定するものではなく2個以上適宜設定される。
First, as shown in FIGS. 1A and 1B, a plurality of semiconductor elements 5 positioned at predetermined intervals on wiring electrodes 3 on a wiring circuit board 2 having a wiring circuit formed on one side. The plurality of semiconductor elements 5 are mounted on the printed circuit board 2 by bringing the metal electrodes (bumps) 7 formed on the lower surface into contact with each other and joining the plurality of semiconductor elements 5 to the printed circuit board 2. In FIG. 1A, sixteen semiconductor elements 5 are provided on the printed circuit board 2; however, the number is not limited to this, and two or more elements are appropriately set.

【0032】上記半導体素子5の下面に形成された電極
(バンプ)7の形成材料としては、低融点半田、高融点
半田、金のスタッドバンプ、金、銀、銅、アルミニウ
ム、ニッケル、クロム、錫等があげられる。また、上記
配線回路基板2に形成された配線電極3の形成材料とし
ても、上記電極(バンプ)7の形成材料と同様の材質の
ものがあげられる。
As a material for forming the electrodes (bumps) 7 formed on the lower surface of the semiconductor element 5, low melting point solder, high melting point solder, gold stud bumps, gold, silver, copper, aluminum, nickel, chromium, tin And the like. The material for forming the wiring electrodes 3 formed on the wiring circuit board 2 may be the same as the material for forming the electrodes (bumps) 7.

【0033】つぎに、円柱状のペレット8を用いて、図
2(A)および(B)に示すように、2本の一点鎖線Q
で分割される4つの各領域内にそれぞれ配設された4個
の半導体素子5の中心部分となる配線回路基板2上に上
記封止用樹脂組成物からなるペレット8をそれぞれ載置
する。そして、ペレット8を載置した後、全体を加熱し
てペレット8を溶融し、毛管現象を利用して各半導体素
子5と配線回路基板2とで形成される個々の空隙内に溶
融状態の封止用樹脂組成物を充填し、さらに好ましくは
上記空隙内とともに半導体素子5間の隙間を充填して硬
化させることにより樹脂封止する。このようにして、図
3に示すような、半導体装置を製造する。図3におい
て、6は封止用樹脂組成物を用いて封止することにより
形成された封止樹脂層である。
Next, as shown in FIGS. 2A and 2B, two dashed lines Q
The pellets 8 made of the above-mentioned sealing resin composition are respectively mounted on the printed circuit board 2 which is the central part of the four semiconductor elements 5 disposed in the four regions divided by the above. Then, after the pellets 8 are placed, the whole is heated to melt the pellets 8, and the molten state is sealed in the respective voids formed by each semiconductor element 5 and the printed circuit board 2 by utilizing the capillary phenomenon. Resin sealing is performed by filling a resin composition for stopping, and more preferably, by filling and curing the gap between the semiconductor elements 5 together with the space. Thus, a semiconductor device as shown in FIG. 3 is manufactured. In FIG. 3, reference numeral 6 denotes a sealing resin layer formed by sealing using a sealing resin composition.

【0034】上記各半導体素子5と配線回路基板2との
空隙および半導体素子5間の隙間を樹脂封止した後、図
4に示すように、これを各半導体素子5単位毎に切断す
る。このようにして半導体装置を製造する。なお、上記
切断方法としては、特に限定するものではなく、例え
ば、ブレード・ダイシング法、ダイヤモンド・スクライ
バ法、レーザ・スクライバ法等があげられる。
After the gaps between the semiconductor elements 5 and the printed circuit board 2 and the gaps between the semiconductor elements 5 are sealed with a resin, as shown in FIG. Thus, a semiconductor device is manufactured. The cutting method is not particularly limited, and examples thereof include a blade dicing method, a diamond scriber method, and a laser scriber method.

【0035】上記製法では、封止用樹脂組成物として、
図2(A)および(B)に示すように、4個の半導体素
子5の中心部分となる空間内に収容載置可能な大きさの
円柱状のペレット8を用いているが、上記ペレット8の
形状は円柱状に限定するものではなく、円錐形状を有す
るものであってもよく、4個の半導体素子5の中心部分
となる空間内に収容載置可能なものであればその形状や
大きさは問わない。
In the above method, the encapsulating resin composition is
As shown in FIGS. 2A and 2B, a columnar pellet 8 having a size that can be accommodated and placed in a space that is a central portion of four semiconductor elements 5 is used. Is not limited to a columnar shape, and may have a conical shape, as long as the shape and size can be accommodated and placed in a space that is a central portion of the four semiconductor elements 5. It doesn't matter.

【0036】さらに、図5に示すように、2本の一点鎖
線Q′で分割される4つの各領域内にそれぞれ配設され
た4個の半導体素子5により形成される十字状の空間の
うち、一方の直線状の空間に収容可能な大きさの棒状の
ペレット8bを用いてもよい。この棒状のペレット8b
の形状は特に限定するものではなく、断面が円状(楕円
状等を含む)のもの、三角形や四角形等の多角形状のも
の等各種断面形状の棒状ペレットを適宜に用いることが
できる。
Further, as shown in FIG. 5, among the cross-shaped spaces formed by the four semiconductor elements 5 respectively disposed in the four regions divided by the two-dot chain line Q '. Alternatively, a rod-shaped pellet 8b large enough to be accommodated in one of the linear spaces may be used. This rod-shaped pellet 8b
The shape of is not particularly limited, and rod-shaped pellets having various cross-sectional shapes such as a circular cross-section (including an elliptical shape), a polygonal shape such as a triangular or quadrangular shape can be appropriately used.

【0037】そして、このような封止用樹脂組成物であ
るペレットとしては、少なくとも上記配線回路基板2と
複数の半導体素子5で形成される個々の空隙を充填する
ことが可能な量であるとともに、複数の半導体素子5間
の隙間の充填や各半導体素子5表面を樹脂組成物が被覆
することが可能となる量であってもよい。
The pellets as the sealing resin composition have such an amount that at least individual voids formed by the wiring circuit board 2 and the plurality of semiconductor elements 5 can be filled. Alternatively, the amount may be such that the resin composition can fill gaps between the plurality of semiconductor elements 5 and cover the surface of each semiconductor element 5.

【0038】また、上記製法では、配線回路基板2は、
樹脂封止された後、各半導体素子5単位毎に適宜の大き
さに切断されるが、このように一枚ものに限定するもの
ではなく、予め個々の半導体素子5が搭載可能な配線回
路基板を複数枚組み合わせた集合体からなるものを用い
てもよい。
In the above manufacturing method, the printed circuit board 2 is
After being sealed with resin, each semiconductor element 5 is cut into an appropriate size for each unit. However, the present invention is not limited to this one, and a wiring circuit board on which individual semiconductor elements 5 can be mounted in advance. May be used.

【0039】上記半導体装置の製法において、予め、上
記配線回路基板2の外周縁に溶融状態の封止用樹脂組成
物流出防止用の枠を設けてもよい。すなわち、上記枠を
設けた後、上記配線回路基板2と半導体素子5で形成さ
れる個々の空隙と、複数の半導体素子5間の空隙を溶融
状態の封止用樹脂組成物で充填した場合、溶融樹脂が配
線回路基板2の外周縁から流出することを防止できると
ともに、半導体素子5間の隙間の充填が均一に行うこと
ができるようになる。そして、上記枠は溶融状態の封止
用樹脂組成物による上記空隙および隙間の充填を終えた
後、配線回路基板2から取り除かれる。
In the method of manufacturing the semiconductor device, a frame for preventing the molten sealing resin composition from flowing out may be provided on the outer peripheral edge of the printed circuit board 2 in advance. That is, after the frame is provided, the individual gaps formed by the printed circuit board 2 and the semiconductor element 5 and the gaps between the plurality of semiconductor elements 5 are filled with the sealing resin composition in a molten state. The molten resin can be prevented from flowing out of the outer peripheral edge of the printed circuit board 2, and the gap between the semiconductor elements 5 can be uniformly filled. The frame is removed from the printed circuit board 2 after the filling of the voids and gaps with the sealing resin composition in a molten state.

【0040】上記常温で固体の封止用樹脂組成物からな
るペレット8を溶融状態とする際の加熱温度としては、
半導体素子5および配線回路基板2の劣化等を考慮して
70〜250℃の範囲に設定することが好ましい。さら
に、充填した後硬化する際の加熱温度条件としては、1
20〜200℃の範囲に設定することが好ましい。上記
加熱方法としては、赤外線リフロー炉、乾燥機、温風
機、熱板等があげられる。
The heating temperature at which the pellets 8 made of the encapsulating resin composition which are solid at ordinary temperature are melted is as follows.
The temperature is preferably set in the range of 70 to 250 ° C. in consideration of the deterioration of the semiconductor element 5 and the printed circuit board 2 and the like. Further, the heating temperature conditions for curing after filling are as follows.
It is preferable to set the temperature in the range of 20 to 200 ° C. Examples of the heating method include an infrared reflow oven, a dryer, a hot air blower, and a hot plate.

【0041】上記のようにして製造された半導体装置に
おいて、各半導体素子5の大きさは、通常、幅5〜20
mm×長さ5〜20mm×厚み0.1〜1.0mmのも
のが使用される。そして、溶融状態の封止用樹脂組成物
が充填される、各半導体素子5と配線回路基板2の空隙
の両者間の距離は、通常、10〜120μmである。特
に、本発明に用いられる封止用樹脂組成物の特性等を考
慮すると、上記両者間の距離は、10〜100μmに設
定することが好ましい。
In the semiconductor device manufactured as described above, the size of each semiconductor element 5 is usually 5 to 20 in width.
Those having a size of mm × length 5 to 20 mm × thickness 0.1 to 1.0 mm are used. The distance between each semiconductor element 5 and the gap between the wiring circuit board 2 and the gap where the molten sealing resin composition is filled is usually 10 to 120 μm. In particular, in consideration of the characteristics of the sealing resin composition used in the present invention, the distance between the two is preferably set to 10 to 100 μm.

【0042】上記製法に用いた封止用樹脂組成物(ペレ
ット8)としては、そのペレット密度が真密度に対して
98%以上〔特性(Y)〕であることが好ましく、特に
好ましくは99%以上である。すなわち、ペレット密度
が真密度に対して98%以上という高真密度に設定する
ことにより、ペレット内部の空気が硬化物に持ち込ま
れ、この空気がボイドを形成する原因となることを防止
することが可能となるからである。なお、上記ペレット
密度(%)は下記の式にて算出される値である。
The sealing resin composition (pellet 8) used in the above-mentioned production method preferably has a pellet density of 98% or more [property (Y)] with respect to the true density, particularly preferably 99%. That is all. That is, by setting the pellet density to a high true density of 98% or more with respect to the true density, it is possible to prevent the air inside the pellets from being brought into the cured product and to prevent the air from forming voids. It is possible. The pellet density (%) is a value calculated by the following equation.

【0043】[0043]

【数1】ペレット密度(%)=〔(ペレットの比重)/
(硬化物の比重)〕×100
## EQU1 ## Pellet density (%) = [(specific gravity of pellet) /
(Specific gravity of cured product)] × 100

【0044】そして、上記封止用樹脂組成物(ペレット
8)としては、通常、150℃でのゲルタイム〔特性
(X)〕が5〜30分間であり、特に150℃でのゲル
タイムが5〜15分間であることが好ましい。すなわ
ち、封止用樹脂組成物のゲルタイムが上記範囲内である
ことにより、硬化反応がゆるやかに生起し配線回路基板
と半導体素子間の空隙に封止用樹脂組成物が均一に充填
され、封止作業の条件設定が容易であるとともに硬化時
間の短縮が可能となる。なお、上記ゲルタイムは熱板キ
ャビティー法にて測定した。
The encapsulating resin composition (pellet 8) usually has a gel time at 150 ° C. [property (X)] of 5 to 30 minutes, particularly a gel time at 150 ° C. of 5 to 15 minutes. Minutes. That is, when the gel time of the sealing resin composition is within the above range, the curing reaction occurs slowly and the gap between the wiring circuit board and the semiconductor element is uniformly filled with the sealing resin composition, and the sealing is performed. Work conditions can be easily set and the curing time can be shortened. The gel time was measured by a hot plate cavity method.

【0045】さらに、上記封止用樹脂組成物として、下
記の特性(Z)を有する必要がある。すなわち、上記封
止用樹脂組成物の形成材料を用い、上記方法に従って断
面積1mm×2mmの角柱状ペレットを作製する。そし
て、上記角柱状ペレットを150℃で10分間加熱溶融
し、100μmの空隙を有する2枚の鏡面ガラス板間に
溶融侵入させ、その際の侵入距離が15mm以上となる
特性〔特性(Z)〕を有していなければならない。より
好ましくは侵入距離が18mm以上である。また封止用
樹脂組成物を用いて封止することにより形成された封止
樹脂層6、すなわち、上記封止用樹脂組成物としては、
各使用温度での溶融粘度が1〜100poise、その
硬化物としては、線膨脹係数が14〜40ppm/℃で
あることが好ましい。特に好ましくは溶融粘度が1〜3
0poise、線膨脹係数が14〜30ppm/℃であ
る。これは、界面ジョイントである半田等の導電性接着
材料の線膨張係数に界面封止樹脂の線膨張係数を合わせ
ることが応力集中を無くし、導通信頼性を向上させるこ
とによるものである。すなわち、溶融粘度が上記範囲内
に設定されることにより、充填性が良好となる。さら
に、線膨脹係数が上記範囲内に設定されることにより、
樹脂硬化物や半導体素子にクラック等の応力による欠陥
防止が可能となる。なお、上記溶融粘度は、コーンプレ
ート粘度計により測定した。また、線膨脹係数は、熱機
械分析(Thermal Mechanical Analysis:TMA)によ
り測定した。
Further, it is necessary that the sealing resin composition has the following property (Z). That is, a prism-shaped pellet having a cross-sectional area of 1 mm × 2 mm is prepared by using the material for forming the sealing resin composition according to the above method. Then, the prismatic pellets are heated and melted at 150 ° C. for 10 minutes, and are melted and penetrated between two mirror-surface glass plates having a gap of 100 μm, and the penetration distance at that time becomes 15 mm or more [Characteristic (Z)] Must have. More preferably, the penetration distance is 18 mm or more. The sealing resin layer 6 formed by sealing with the sealing resin composition, that is, the sealing resin composition includes:
The melt viscosity at each use temperature is preferably 1 to 100 poise, and the cured product thereof preferably has a linear expansion coefficient of 14 to 40 ppm / ° C. Particularly preferably, the melt viscosity is 1 to 3.
0 poise, and the coefficient of linear expansion is 14 to 30 ppm / ° C. This is because matching the linear expansion coefficient of the interfacial sealing resin with the linear expansion coefficient of the conductive adhesive material such as solder, which is an interface joint, eliminates stress concentration and improves conduction reliability. That is, the filling property is improved by setting the melt viscosity within the above range. Further, by setting the linear expansion coefficient within the above range,
Defects due to stresses such as cracks in the cured resin or semiconductor element can be prevented. In addition, the said melt viscosity was measured with the cone plate viscometer. The coefficient of linear expansion was measured by thermomechanical analysis (Thermal Mechanical Analysis: TMA).

【0046】つぎに、実施例について比較例と併せて説
明する。
Next, examples will be described together with comparative examples.

【0047】まず、実施例に先立って、下記に示す各成
分を準備した。
First, prior to the examples, the following components were prepared.

【0048】〔エポキシ樹脂a〕結晶性エポキシ樹脂
〔前記式(1)で表されるエポキシ樹脂(油化シェル社
製、YX−4000H)〕(エポキシ当量192、融点
110℃)
[Epoxy resin a] Crystalline epoxy resin [Epoxy resin represented by the above formula (1) (YX-4000H, manufactured by Yuka Shell Co., Ltd.)] (epoxy equivalent 192, melting point 110 ° C.)

【0049】〔エポキシ樹脂b〕結晶性エポキシ樹脂
〔前記式(2)で表されるエポキシ樹脂(東都化成社
製、YDC1312)〕(エポキシ当量175、融点1
40℃)
[Epoxy resin b] Crystalline epoxy resin [Epoxy resin represented by the formula (2) (YDC1312, manufactured by Toto Kasei Co., Ltd.)] (epoxy equivalent: 175, melting point: 1)
40 ℃)

【0050】〔エポキシ樹脂c〕結晶性エポキシ樹脂
〔前記式(3)で表されるエポキシ樹脂(新日鉄化学社
製、ESLV−80XY)〕(エポキシ当量195、融
点80℃)
[Epoxy resin c] Crystalline epoxy resin [Epoxy resin represented by the formula (3) (ESLV-80XY, manufactured by Nippon Steel Chemical Co., Ltd.)] (epoxy equivalent: 195, melting point: 80 ° C.)

【0051】〔硬化剤a〕ノボラック型フェノール樹脂
(水酸基当量104g/eq、軟化点59℃)
[Curing agent a] Novolak type phenol resin (hydroxyl equivalent: 104 g / eq, softening point: 59 ° C.)

【0052】〔硬化剤b〕フェノールアラルキル樹脂
(水酸基当量170g/eq、軟化点65℃)
[Curing agent b] Phenol aralkyl resin (hydroxyl equivalent 170 g / eq, softening point 65 ° C.)

【0053】〔シリカ粉末〕球状溶融シリカ粉末(平均
粒径5μm、最大粒径24μm)
[Silica powder] Spherical fused silica powder (average particle size 5 μm, maximum particle size 24 μm)

【0054】〔触媒〕トリフェニルホスフィン[Catalyst] Triphenylphosphine

【0055】〔難燃剤〕ブロム化エポキシフェノールノ
ボラック
[Flame retardant] Brominated epoxy phenol novolak

【0056】〔難燃助剤〕三酸化二アンチモン[Flame retardant aid] diantimony trioxide

【0057】〔ワックス〕ポリエチレン系ワックス[Wax] Polyethylene wax

【0058】〔シリコーン化合物〕側鎖エチレングライ
コールタイプジメチルポリシロキサン
[Silicone compound] Side chain ethylene glycol type dimethyl polysiloxane

【0059】〔カップリング剤〕γ−グリシドキシプロ
ピルトリメトキシシラン
[Coupling agent] γ-glycidoxypropyltrimethoxysilane

【0060】[0060]

【実施例1〜8】〔封止用ペレットの作製〕上記各成分
を用い、下記の表1に示す割合で各成分を混合した。こ
れを直接シート化し、冷却後打ち抜くことにより円柱状
ペレット(高さ10mm×断面積54mm2 )を作製し
た。なお、得られたペレットの密度は、いずれも真密度
に対して98%以上であった。
Examples 1 to 8 [Preparation of sealing pellets] Each of the above-mentioned components was mixed at the ratios shown in Table 1 below. This was directly formed into a sheet, and punched after cooling to produce a cylindrical pellet (height: 10 mm × cross-sectional area: 54 mm 2 ). The density of each of the obtained pellets was 98% or more of the true density.

【0061】[0061]

【表1】 [Table 1]

【0062】上記各ペレットを用い、つぎのようにして
半導体装置を製造した。すなわち、まず、図1(A)お
よび(B)に示すように、片面に配線回路が形成された
配線回路基板2上の低融点半田からなる配線電極3に、
一定間隔(4mm)で位置決めされた16個の半導体素
子5の下面に形成された高融点半田からなる電極(バン
プ)7を当接し複数の半導体素子5と配線回路基板2と
を接合した。
Using each of the above pellets, a semiconductor device was manufactured as follows. That is, first, as shown in FIGS. 1A and 1B, a wiring electrode 3 made of low melting point solder is placed on a wiring circuit board 2 having a wiring circuit formed on one surface.
Electrodes (bumps) 7 made of high melting point solder formed on the lower surfaces of the sixteen semiconductor elements 5 positioned at regular intervals (4 mm) were brought into contact with each other, and the plurality of semiconductor elements 5 and the printed circuit board 2 were joined.

【0063】つぎに、円柱状のペレット8を用いて、図
2(A)および(B)に示すように、2本の一点鎖線Q
で分割される4つの各領域内にそれぞれ配設された4個
の半導体素子5の中心部分となる配線回路基板2上に上
記封止用樹脂組成物からなるペレット8をそれぞれ合計
4個載置した。そして、上記ペレット8を載置した後、
乾燥機により全体を加熱(条件:150℃)してペレッ
ト8を溶融して、各半導体素子5と配線回路基板2で形
成される個々の空隙を溶融状態の封止用樹脂組成物で充
填した。続いて、全体を加熱(条件:150℃×5時間
キュアー)して封止用樹脂組成物を硬化させることによ
り、上記個々の空隙を樹脂封止した。このようにして、
図3に示すような、半導体装置を製造した。図3におい
て、6は封止用樹脂組成物を用いて封止することにより
形成された封止樹脂層である。
Next, as shown in FIGS. 2A and 2B, two dashed lines Q
A total of four pellets 8 made of the above-mentioned sealing resin composition are placed on the printed circuit board 2 which is the central part of the four semiconductor elements 5 respectively disposed in the four regions divided by the above. did. And, after placing the above-mentioned pellets 8,
The whole was heated by a dryer (condition: 150 ° C.) to melt the pellets 8, and individual voids formed by each semiconductor element 5 and the printed circuit board 2 were filled with the sealing resin composition in a molten state. . Subsequently, the entire gap was resin-sealed by heating the entire body (condition: curing at 150 ° C. × 5 hours) to cure the sealing resin composition. In this way,
A semiconductor device as shown in FIG. 3 was manufactured. In FIG. 3, reference numeral 6 denotes a sealing resin layer formed by sealing using a sealing resin composition.

【0064】つぎに、上記各半導体素子5と配線回路基
板2で形成される個々の空隙および半導体素子5間の隙
間を樹脂封止した後、図4に示すように、これを各半導
体素子5単位毎にダイシングにより切断した。このよう
にして目的とする半導体装置を製造した。
Next, after the individual gaps formed between the semiconductor elements 5 and the wiring circuit board 2 and the gaps between the semiconductor elements 5 are sealed with a resin, as shown in FIG. Each unit was cut by dicing. Thus, the intended semiconductor device was manufactured.

【0065】このようにして得られた半導体装置は、封
止樹脂層6部分にボイド等が形成されず、また、通電試
験による結果も良好であることから、信頼性の高いもの
が得られたことがわかる。なお、上記通電試験は、つぎ
のようにして行った。すなわち、デーシチェーンの評価
テグを使い、初期導通不良評価および−55℃/5分〜
125℃/5分の1000サイクルにおける熱サイクル
テスト(TCT)後の導通不良評価を行った。その結
果、いずれの導通評価においても導通不良(10パッケ
ージ中)は発生しなかった。
In the semiconductor device thus obtained, no voids were formed in the sealing resin layer 6 and the result of the current test was good, so that a highly reliable device was obtained. You can see that. The energization test was performed as follows. That is, the initial conduction failure evaluation and the evaluation at −55 ° C./5 min.
Conduction failure evaluation after a thermal cycle test (TCT) at 1000 cycles of 125 ° C./5 minutes was performed. As a result, no conduction failure (out of 10 packages) occurred in any conduction evaluation.

【0066】つぎに、22mm×60mm×厚み1mm
の鏡面ガラス板を2枚準備し、100μmのスペーサー
を介して5mm程度長手方向にずらして接着したものを
準備した。そして、上記鏡面ガラス板の張り合わせのず
らした部分に、断面積1mm×3mm×長さ20mmの
角柱状ペレットを置き、つぎに、これを温度150℃の
オーブンに10分間放置し、上記ペレットを溶融して毛
管現象によって封止用樹脂組成物を充填させることによ
り2枚の鏡面ガラス板界面(空隙100μm)を樹脂封
止した。このように封止した結果、溶融した樹脂が界面
に対し侵入した距離を測定し示した。目安としては15
mmが汎用的に使用する上で要求される値と考える。
Next, 22 mm × 60 mm × 1 mm thick
Were prepared and bonded by being shifted about 5 mm in the longitudinal direction via a 100 μm spacer. Then, a prism having a cross-sectional area of 1 mm × 3 mm × 20 mm in length is placed on the mirror glass plate where the lamination is displaced, and then left in an oven at a temperature of 150 ° C. for 10 minutes to melt the pellet. Then, the interface between the two mirror glass plates (void 100 μm) was sealed with a resin by filling the sealing resin composition by capillary action. As a result of the sealing, the distance at which the molten resin entered the interface was measured and shown. As a guide, 15
mm is considered to be a value required for general use.

【0067】また、上記各ペレットを加熱溶融して硬化
(条件:150℃×20分+150℃×300分)する
ことにより線膨脹係数を熱機械分析(TMA)により測
定した。また、それぞれの溶融粘度およびゲルタイムを
前述の方法に従って測定した。これらの評価・測定結果
を下記の表2に併せて示した。
The above-mentioned pellets were heated and melted and cured (conditions: 150 ° C. × 20 minutes + 150 ° C. × 300 minutes), and the coefficient of linear expansion was measured by thermomechanical analysis (TMA). In addition, the respective melt viscosities and gel times were measured according to the methods described above. The evaluation and measurement results are shown in Table 2 below.

【0068】[0068]

【表2】 [Table 2]

【0069】上記表2の結果、各半導体装置は、通電試
験結果が良好であり、信頼性の高い半導体装置が得られ
たことがわかる。また、半導体装置を製造するに際して
用いた各ペレットの特性をみた場合、150℃でのゲル
タイムが5〜30分、溶融時(150℃)での最低溶融
粘度が1〜30poise、線膨張係数が14〜40p
pm/℃であることが好ましい。
From the results shown in Table 2, it can be seen that the results of the conduction test of each semiconductor device were good, and that a highly reliable semiconductor device was obtained. When the characteristics of each pellet used in manufacturing the semiconductor device were examined, the gel time at 150 ° C. was 5 to 30 minutes, the minimum melt viscosity at melting (150 ° C.) was 1 to 30 poise, and the coefficient of linear expansion was 14. ~ 40p
pm / ° C.

【0070】[0070]

【発明の効果】以上のように、本発明は、配線回路基板
の配線電極に、所定間隔で位置決めされた複数の半導体
素子の電極部を当接させて上記基板に上記複数の半導体
素子を搭載した半導体素子搭載済み配線回路基板を準備
する。ついで、常温で固体の封止用樹脂組成物を上記複
数の半導体素子のうちの任意の半導体素子の間に載置し
て加熱溶融することにより、上記配線回路基板と上記複
数の半導体素子との空隙に、上記溶融状態の封止用樹脂
組成物を充填し硬化させ、少なくとも、上記配線回路基
板と複数の半導体素子で形成される個々の空隙をそれぞ
れ樹脂封止するという製法を備えている。このようにし
て基板上に複数の半導体素子が搭載されたものを、各半
導体素子毎に切断することにより、半導体装置を製造す
ることができる。このため、多数の半導体素子の樹脂封
止を一度に行うことができる。したがって、半導体装置
の生産効率が向上する。
As described above, the present invention mounts the plurality of semiconductor elements on the substrate by bringing the electrode portions of the plurality of semiconductor elements positioned at predetermined intervals into contact with the wiring electrodes of the printed circuit board. The prepared wiring circuit board on which the semiconductor element is mounted is prepared. Then, by placing a sealing resin composition that is solid at normal temperature between any of the plurality of semiconductor elements and melting by heating, the wiring circuit board and the plurality of semiconductor elements are bonded together. A method is provided in which the gap is filled with the molten sealing resin composition and cured, and at least individual gaps formed by the printed circuit board and the plurality of semiconductor elements are each resin-sealed. A semiconductor device can be manufactured by cutting a semiconductor element mounted on a substrate into a plurality of semiconductor elements in this manner. Therefore, resin sealing of many semiconductor elements can be performed at once. Therefore, the production efficiency of the semiconductor device is improved.

【0071】また、本発明の半導体装置の製法では、上
記溶融状態の封止用樹脂組成物が、上記配線回路基板と
複数の半導体素子で形成される個々の空隙を充填すると
ともに、上記複数の半導体素子間の隙間も充填して、上
記配線回路基板と複数の半導体素子で形成される個々の
空隙と、上記複数の半導体素子間の隙間をそれぞれ樹脂
封止することも容易となる。
In the method for manufacturing a semiconductor device according to the present invention, the sealing resin composition in the molten state fills the individual voids formed by the wiring circuit board and the plurality of semiconductor elements, and forms the plurality of semiconductor elements. Filling the gaps between the semiconductor elements also facilitates resin sealing of the individual gaps formed by the printed circuit board and the plurality of semiconductor elements and the gaps between the plurality of semiconductor elements.

【0072】そして、本発明の半導体装置の製法では、
上記常温で固体の封止用樹脂組成物が、上記配線回路基
板と複数の半導体素子で形成される個々の空隙と、複数
の半導体素子間の隙間を充填しうる量である場合、上記
空隙および隙間の樹脂封止が容易かつ確実になされるよ
うになる。
In the method of manufacturing a semiconductor device according to the present invention,
The solid-state sealing resin composition at room temperature, the individual gaps formed by the wiring circuit board and a plurality of semiconductor elements, when the amount can fill the gap between the plurality of semiconductor elements, the gap and The resin sealing of the gap is easily and reliably performed.

【0073】本発明の半導体装置の製法において、予
め、上記配線回路基板の外周縁に溶融状態の封止用樹脂
組成物流出防止用の枠を設けるとともに、上記配線回路
基板と半導体素子との空隙に溶融状態の封止用樹脂組成
物を充填した後、配線回路基板から上記枠を取り除く工
程を備えることにより、溶融状態の封止用樹脂組成物
が、上記配線回路基板と複数の半導体素子で形成される
個々の空隙の充填、および、上記複数の半導体素子間の
隙間の充填を均一に行うことができるようになる。
In the method of manufacturing a semiconductor device according to the present invention, a frame for preventing the outflow of the molten sealing resin composition is provided in advance on the outer peripheral edge of the printed circuit board, and a gap between the printed circuit board and the semiconductor element is provided. After filling the sealing resin composition in the molten state, the step of removing the frame from the wiring circuit board, the sealing resin composition in the molten state, the wiring circuit board and a plurality of semiconductor elements It is possible to uniformly fill the formed voids and the gaps between the plurality of semiconductor elements.

【0074】そして、上記常温で固体の封止用樹脂組成
物が、150℃でのゲルタイムが5〜30分間という特
性(X)を有することにより、硬化反応がゆるやかに生
起し、配線回路基板と半導体素子間の空隙に封止用樹脂
組成物が均一に充填されるようになる。また、封止作業
の条件設定を容易に行うことができるようになる。
Since the encapsulating resin composition which is solid at room temperature has a characteristic (X) of a gel time at 150 ° C. of 5 to 30 minutes, a curing reaction occurs slowly, and the resin composition for the wiring circuit board is formed. The gap between the semiconductor elements is uniformly filled with the sealing resin composition. Further, it is possible to easily set the conditions for the sealing operation.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(A)は本発明の半導体装置の製法の一例を示
す斜視図であり、(B)はその部分断面図である。
FIG. 1A is a perspective view showing an example of a method for manufacturing a semiconductor device of the present invention, and FIG. 1B is a partial sectional view thereof.

【図2】(A)は本発明の半導体装置の製法の一例を示
す斜視図であり、(B)はその平面図である。
FIG. 2A is a perspective view showing an example of a method for manufacturing a semiconductor device of the present invention, and FIG. 2B is a plan view thereof.

【図3】本発明の半導体装置の製法の一例を示す部分断
面図である。
FIG. 3 is a partial cross-sectional view illustrating an example of a method for manufacturing a semiconductor device of the present invention.

【図4】本発明の半導体装置の製法の一例を示す部分断
面図である。
FIG. 4 is a partial cross-sectional view showing one example of a method for manufacturing a semiconductor device of the present invention.

【図5】本発明の半導体装置の製法に用いられる他の形
状のペレットを用いた例を示す平面図である。
FIG. 5 is a plan view showing an example using pellets of another shape used in the method of manufacturing a semiconductor device of the present invention.

【符号の説明】[Explanation of symbols]

2 配線回路基板 3 配線電極 5 半導体素子 6 封止樹脂層 7 電極 8 ペレット 2 wiring circuit board 3 wiring electrode 5 semiconductor element 6 sealing resin layer 7 electrode 8 pellet

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 配線回路基板の配線電極に、所定間隔で
位置決めされた複数の半導体素子の電極部を当接させて
上記基板に上記複数の半導体素子を搭載した半導体素子
搭載済み配線回路基板を準備し、常温で固体の封止用樹
脂組成物を上記複数の半導体素子のうちの任意の半導体
素子の間に載置して加熱溶融することにより、上記配線
回路基板と上記複数の半導体素子との空隙に、上記溶融
状態の封止用樹脂組成物を充填し硬化させ、少なくと
も、上記配線回路基板と複数の半導体素子で形成される
個々の空隙をそれぞれ樹脂封止することを特徴とする半
導体装置の製法。
1. A printed circuit board with a semiconductor element mounted thereon, wherein the plurality of semiconductor elements are mounted on the substrate by contacting electrode portions of a plurality of semiconductor elements positioned at predetermined intervals with wiring electrodes of the printed circuit board. Prepare, by placing a solid sealing resin composition at room temperature between any of the plurality of semiconductor elements and heating and melting, the wiring circuit board and the plurality of semiconductor elements Semiconductor, characterized in that the gap is filled with the molten sealing resin composition and cured, and at least individual gaps formed by the printed circuit board and the plurality of semiconductor elements are each resin-sealed. Equipment manufacturing method.
【請求項2】 予め、上記配線回路基板の外周縁に溶融
状態の封止用樹脂組成物流出防止用の枠を設けるととも
に、上記配線回路基板と半導体素子との空隙に溶融状態
の封止用樹脂組成物を充填した後、配線回路基板から上
記枠を取り除く工程を備えた請求項1記載の半導体装置
の製法。
2. A molten resin sealing frame for preventing leakage of a molten sealing resin composition is provided in advance on an outer peripheral edge of the printed circuit board, and a molten sealing resin is formed in a gap between the printed circuit board and the semiconductor element. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of removing the frame from the printed circuit board after filling the resin composition.
【請求項3】 上記常温で固体の封止用樹脂組成物が、
下記の特性(X)を有している請求項1または2記載の
半導体装置の製法。 (X)150℃でのゲルタイムが、5〜30分間。
3. The sealing resin composition which is solid at room temperature,
3. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device has the following characteristic (X). (X) The gel time at 150 ° C. is 5 to 30 minutes.
JP11005834A 1999-01-12 1999-01-12 Semiconductor device manufacturing method Pending JP2000208536A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11005834A JP2000208536A (en) 1999-01-12 1999-01-12 Semiconductor device manufacturing method

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006196657A (en) * 2005-01-13 2006-07-27 New Japan Radio Co Ltd Manufacturing method of semiconductor device
WO2008072491A1 (en) * 2006-12-11 2008-06-19 Sharp Kabushiki Kaisha Ic chip mounting package and process for manufacturing the same
JP2011091257A (en) * 2009-10-23 2011-05-06 Stanley Electric Co Ltd Method of manufacturing led light source device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006196657A (en) * 2005-01-13 2006-07-27 New Japan Radio Co Ltd Manufacturing method of semiconductor device
WO2008072491A1 (en) * 2006-12-11 2008-06-19 Sharp Kabushiki Kaisha Ic chip mounting package and process for manufacturing the same
US8193627B2 (en) 2006-12-11 2012-06-05 Sharp Kabushiki Kaisha IC chip mounting package provided with IC chip located in device hole formed within a package base member
JP2011091257A (en) * 2009-10-23 2011-05-06 Stanley Electric Co Ltd Method of manufacturing led light source device

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