JP2000208913A - Manufacture of printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a printed wiring board, wherein an IC chip and a printed wiring board are surely joined, while a positioning mark is printed clearly. SOLUTION: After the formation of solder bumps 76U and 76D, the contamination on the surface of them and an oxide film layer on the surface of a solder resist layer 70 are removed by plasma for enhanced wettability of the solder resist layer. Thus, an underfill is connected firmly to a multilayer printed wiring board 10, and a target mark is printed clearly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board for forming a package substrate or the like on which an integrated circuit chip is mounted via solder bumps.

[0002]

2. Description of the Related Art Generally, the surface layer of a printed wiring board is an IC.
In order to mount chips and the like, solder bumps and the like are formed, and a solder resist layer is provided so that these solder bumps do not fuse with each other. Specifically, a solder resist layer is provided on a solder pad made of a conductor circuit, a nickel plating layer and a gold plating layer are provided in the opening, and a solder paste or the like is printed and reflowed to form a solder bump. After that, the target mark is printed. Then, positioning is performed with reference to the target mark, and the IC
After mounting the chip, an underfill (resin for sealing) is filled between the IC chip and the printed wiring board in order to increase the connection reliability between the solder bump and the IC chip. Currently, a method is also employed in which a solder paste is directly printed on a conductor circuit without passing through the above-described nickel plating layer and gold plating layer to form a solder bump.

[0003]

Here, when an IC chip is attached to the printed wiring board, a mounting failure may occur in which the solder bumps on the IC chip cannot be joined to the solder pads on the IC chip. Was.

In order to maintain the bonding reliability between the IC chip and the printed wiring board for a long period of time, it is necessary to increase the adhesion between the underfill and the solder resist layer during mounting. That is, if the adhesiveness between the underfill and the solder resist layer is low, moisture infiltrates from the interface between the two and solder migration from solder bumps (a phenomenon in which lead ions diffuse in the solder resist layer) occurs. Mutual short circuits occur. In addition, it expands at a high temperature during operation, and applies stress to the solder bump and the junction of the IC, which may cause cracking and destruction to cause disconnection. However, the surface of the solder resist layer was formed with an oxide film layer in a solder bump forming step exposed to a high temperature, and the wettability was reduced, so that sufficient adhesion could not be obtained.

Further, since the surface of the solder resist has low wettability, it has not been possible to clearly print a positioning mark such as a target mark. For this reason, the target mark cannot be optically detected accurately, and there has been a problem in a subsequent process such as an inability to properly mount the IC chip.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and its main objects are to ensure that an IC chip and a printed wiring board can be bonded and that a positioning mark can be printed clearly. In proposing a method for manufacturing a printed wiring board,

[0007]

The inventors of the present invention have studied the causes of the decrease in the connection reliability of the solder bumps as described above.
It was concluded that the contamination of the surface of the solder bump on the printed wiring board side reduced the wettability of the molten metal ball of the solder bump, and the flux on the surface of the metal ball, and reduced the connection reliability. . Here, it is considered that the contamination of the surface of the solder bumps is caused by the adhesion of grease when the metal inspection probe is pressed in the checker process for checking short-circuit and disconnection after the formation of the solder bumps. Then, the inventors found that the solder bumps deteriorated the wettability of the surface of the solder bumps due to the contamination, repelled the metal balls and the flux on the IC chip side, and caused defective mounting.

As described above, it is necessary to improve the adhesion between the underfill that protects the metal balls and the solder resist. However, during and after the formation of the solder bump, an oxide layer is formed on the surface of the solder resist. The contact angle increases and the wettability deteriorates, which causes the adhesion to decrease.

Therefore, a method of dissolving the oxide film layer on the surface of the solder resist by an acid treatment or removing the oxide film layer by a polishing machine or the like to change the contact angle and improve the wettability with a resin or the like is also proposed. I can think.
However, even if dissolved in the oxide film layer by acid treatment,
The oxide film layer cannot be removed uniformly. Also, if the oxide film layer is physically removed by a polishing machine or the like, the solder resist layer may be peeled off, which is not practical.

The present inventors have sought to remove contamination on the surface of the solder bump and the oxide film layer on the surface of the solder resist layer, and to find a method that can withstand the solder resist layer and the solder bump at the time of removal. After forming the solder bump, the plasma can remove the contamination of the solder bump surface and the oxide film layer on the surface of the solder resist layer by plasma, and also remove the oxide film layer of the solder resist layer and reliably remove the contamination of the solder bump. Further, the present invention has a method of increasing the wettability of a solder resist layer and printing a positioning mark clearly. That is, the gist configuration of the invention is as follows.

After a solder resist layer is formed and a solder bump is formed in the opening, a surface treatment of the solder resist layer by gas plasma is performed. The processing method is that the printed wiring board on which the solder bumps are formed is placed in an apparatus in a vacuum state, and oxygen, or nitrogen, carbon dioxide, or plasma of four-hooker carbon is released, thereby contaminating the solder bump surface of the opening, Further, the oxide film layer on the surface of the solder resist layer was removed.

The optimum conditions for removing the contamination of the solder bumps by the plasma treatment and reducing the defective mounting are as follows: the plasma emission amount is 500 to 1000 W, and the gas supply amount is 100 to 1000 W.
500 sec. / M, the processing time is preferably 1 to 15 minutes. In addition, by removing the oxide film layer on the surface of the solder resist layer by plasma treatment, and removing the oxide film layer on the surface of the solder resist layer, the underfill without damaging the solder resist layer and the solder bumps. And the adhesiveness with the adhesive can be improved. Further, it is possible to enhance the wettability of the solder resist layer and print the positioning mark clearly.

Here, when the processing time is 1 minute or less,
The dirt on the solder bumps cannot be sufficiently removed, and the contact angle cannot be reduced due to the roughening of the solder resist layer.
On the other hand, if the time exceeds 15 minutes, oxidation occurs on the surface of the solder bump, and the connection reliability is rather lowered. Therefore, the processing time is preferably 1 to 15 minutes as described above.

The contact angle was determined by dropping a single water droplet on the surface of the solder resist layer and measuring the contact angle of the water droplet. The contact angle of the solder resist layer is desirably 40 ° or less. If the contact angle exceeds 40 °, the wettability will be reduced, and the adhesion between the underfill and the solder resist will be reduced. Water easily penetrates from the interface, and the destruction of solder bumps starts early. On the other hand, even if plasma treatment is performed on the solder resist layer within a range that does not cause oxidation of the surface of the above-mentioned solder bump, the contact angle becomes 8 °.
It is difficult to make it below the degree. For this reason, the contact angle is desirably in the range of 8 to 40 °.

As a result of the AFM measurement, the maximum height (Rj) of the solder resist surface was determined. It has been found that a range of 1 to 100 nm is desirable. That is, when the maximum height (Rj) is less than 0.1 nm, the contact angle is 4
Beyond 0 °, causing the aforementioned problems. The other maximum height (R
j) Even when the thickness exceeds 100 nm, oxidation occurs and the connection reliability decreases.

In addition to the solder bump forming step, there are a checker step for inspecting the continuity of the substrate, a character printing step on the surface of the solder resist layer, a cutting step for cutting into packages of an appropriate size, a cleaning step, and the like. When forming a target mark for process recognition in the character printing process, it is most desirable to manufacture a printed wiring board through a solder bump process, a plasma process, and a character printing process.
Thereby, the wettability of the solder resist layer is improved, so that the characters of the character printing become clear, and the target mark for the process recognition becomes clear, so that the adverse effect on the next process can be suppressed. In this case, in order to prevent contamination of the solder bumps due to ink scattering, it is preferable to perform character printing after masking the solder bumps or to perform plasma processing again. Here, the method using masking can be performed at low cost, and the method using plasma can completely remove contamination.

On the other hand, it is also possible to perform solder bump formation and printing after performing the plasma processing. Also in this case, since the wettability of the solder resist layer can be increased,
The target mark can be printed clearly, and the adhesion with the underfill can be improved.

The checker step may be performed between any steps after forming the solder bumps. In particular, it is desirable to carry out before the plasma process. This is because there is no influence on the quality of the judgment due to contamination of the solder bump. In addition, in the cutting step and the cleaning step, the wettability of the solder resist layer does not decrease, so it is possible to perform the step between essentially any steps.However, in order to eliminate the influence of cutting dust and debris, a plasma step It is desirable to perform before.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a printed wiring board according to the present invention will be described. The following method is based on the semi-additive method, but may use the full-additive method.

First, a wiring board having a conductor circuit formed on the surface of the board is prepared. As the substrate, an adhesive layer for electroless plating is formed on a resin insulating substrate such as a glass epoxy substrate, a polyimide substrate, a bismaleimide-triazine resin substrate, a copper-clad laminate, a ceramic substrate, a metal substrate, and the like. The surface of the agent layer is roughened to a roughened surface, a thin electroless plating is applied to the entire roughened surface, a plating resist is formed, and a thick electrolytic plating is applied to a portion where no plating resist is formed. It is performed by a method of removing a resist, performing an etching treatment, and forming a conductor circuit including an electrolytic plating film and an electroless plating film. The conductor circuit is preferably a copper pattern.

On the substrate on which the conductor circuit is formed, a recess is formed by the conductor circuit or through hole. A resin filler is applied to fill the recess, and after drying, the unnecessary resin filler is ground by polishing to expose the conductive circuit, and then the resin filler is fully cured.

Next, a roughened layer is provided on the exposed conductor circuit. The formed roughened layer is etched, polished,
It is desirable that the surface be a roughened surface or a plating film of copper formed by an oxidation treatment or an oxidation-reduction treatment.

The adhesive for electroless plating used in the present invention comprises a cured heat-resistant resin particle which is soluble in an acid or an oxidizing agent contained in an uncured heat-resistant resin which is hardly soluble in an acid or an oxidizing agent. What is dispersed is optimal. By treating with an acid or an oxidizing agent, the heat-resistant resin particles are dissolved and removed, and a roughened surface composed of an octopus-shaped anchor can be formed on the surface.

In the above-mentioned adhesive for electroless plating, the heat-resistant resin particles which have been particularly hardened include a heat-resistant resin powder having an average particle diameter of 10 μm or less, and an average particle diameter of 2 μm.
Aggregated particles obtained by aggregating the following heat-resistant resin powder, a heat-resistant powder resin powder having an average particle size of 2 to 10 μm and an average particle size of 2 μm
m and a mixture with a heat-resistant resin powder having a mean particle size of 2 or less.
Pseudo particles obtained by adhering at least one of a heat-resistant resin powder or an inorganic powder having an average particle diameter of 2 μm or less to the surface of a 10 μm heat-resistant resin powder, and an average particle diameter of 0.1 to
0.8μm heat resistant resin powder and average particle size 0.8μ
m, and a mixture with a heat-resistant resin powder of less than 2 μm,
It is desirable to use a heat-resistant resin powder having an average particle size of 0.1 to 1.0 μm. This is because they can form more complex anchors.

The heat-resistant resin hardly soluble in an acid or an oxidizing agent is selected from a “resin composite composed of a thermosetting resin and a thermoplastic resin” or a “resin composite composed of a photosensitive resin and a thermoplastic resin”. It is desirable to become. This is because the former has high heat resistance, and the latter can form an opening for a via hole by photolithography.

As the thermosetting resin, epoxy resin, phenol resin, polyimide resin and the like can be used. In the case of photosensitization, methacrylic acid, acrylic acid, or the like is subjected to an acrylate reaction with a thermosetting group. Particularly, acrylate of epoxy resin is most suitable. As the epoxy resin, novolak type epoxy resins such as phenol novolak type and cresol novolak type, and alicyclic epoxy resin modified with dicyclopentadiene can be used. As the thermoplastic resin, polyether sulfone (PES), polysulfone (PSF), polyphenylene sulfone (PPS), polyphenylene sulfide (PPES), polyphenyl ether (PPE), polyetherimide (PI) and the like can be used.

The mixing ratio of the thermosetting resin (photosensitive resin) and the thermoplastic resin is preferably thermosetting resin (photosensitive resin) / thermoplastic resin = 95/5 to 50/50. High toughness can be ensured without impairing heat resistance. The mixing ratio of the heat-resistant resin particles is preferably 5 to 50% by weight, and more preferably 10 to 40% by weight, based on the solid content of the heat-resistant resin matrix. The heat-resistant particles are preferably an amino resin (melamine resin, urea resin, guanamine resin), an epoxy resin, or the like. The adhesive may be composed of two layers having different compositions.

Next, while curing the interlayer insulating resin layer,
The interlayer resin layer is provided with an opening for forming a via hole.

When the resin matrix of the adhesive for electroless plating is a thermosetting resin, the interlayer insulating resin layer is perforated by using laser light, oxygen plasma or the like, and is cured by a photosensitive resin. In this case, the holes are formed by exposure and development. In addition,
In the exposure and development process, a photomask (a glass substrate is preferable) on which a circular pattern for forming a via hole is drawn is placed on the photosensitive interlayer resin insulating layer such that the circular pattern side is in close contact with the photomask. After placing, exposure and development are performed.

Next, the surface of the interlayer resin insulating layer (adhesive layer for electroless plating) provided with openings for forming via holes is roughened. In particular, in the present embodiment, the surface of the adhesive layer is roughened by dissolving and removing the heat-resistant resin particles present on the surface of the adhesive layer for electroless plating with an acid or an oxidizing agent. At this time, a roughened layer is formed on the interlayer insulating resin layer.

For the acid treatment, phosphoric acid, hydrochloric acid, sulfuric acid, or an organic acid such as formic acid or acetic acid can be used.
In particular, it is desirable to use an organic acid. This is because the metal conductor layer exposed from the via hole is hardly corroded when the roughening treatment is performed. For the oxidation treatment, it is desirable to use chromic acid or permanganate (such as potassium permanganate).

The roughened layer has a maximum roughness Rmax of 0.1 to
20 μm is preferred. If the thickness is too large, the roughened layer itself is easily damaged and peeled off, and if the thickness is too small, the adhesiveness is reduced. Particularly, in the semi-additive method, the thickness is preferably 0.1 to 5 μm. This is because the electroless plating film can be removed while ensuring adhesion.

Next, a thin electroless plating film is formed on the entire surface of the interlayer insulating resin provided with the roughened catalyst nuclei. This electroless plating film is preferably formed by electroless copper plating, and has a thickness of 1 to 5 μm, more preferably 2 to 3 μm. As the electroless copper plating solution, those having a liquid composition employed in a usual manner can be used. For example, copper sulfate: 29 g / l, sodium carbonate: 25 g / l, EDTA: 140 g / l, sodium hydroxide : 40g / l, 37% formaldehyde: 150m
1, a liquid composition consisting of (PH = 11.5) is preferred.

Next, a photosensitive resin film (dry film) is laminated on the electroless plating film thus formed by laminating.
And a photomask (preferably a glass substrate) on which a plating resist pattern is drawn on the photosensitive resin film.
Are placed in close contact with each other, exposed, and developed to form a non-conductive portion on which a plating resist pattern is provided.

Next, an electrolytic plating film is formed on the electroless copper plating film other than the non-conductive portion, and a conductor circuit and a conductor portion serving as a via hole are provided. As the electrolytic plating, it is desirable to use electrolytic copper plating, and its thickness is preferably 10 to 20 μm.

Next, after removing the plating resist of the non-conductive circuit portion, the plating resist is further added to a mixed solution of sulfuric acid and hydrogen peroxide or an etching solution such as sodium persulfate, ammonium persulfate, ferric chloride and cupric chloride. To remove the electroless plating film,
An independent conductor circuit and a via hole having two layers of an electroless plating film and an electrolytic plating film are obtained. The palladium catalyst nuclei on the roughened surface exposed to the non-conductive portion are dissolved and removed with chromic acid, sulfuric acid and hydrogen peroxide.

Next, a roughened layer is formed on the surface conductor circuit. The formed roughened layer is etched, polished,
It is desirable that the surface be a roughened surface of copper formed by an oxidation treatment or a redox treatment or a roughened surface formed by a plating film.

Next, a solder-resist layer is formed on the conductor circuit. The thickness of the solder resist layer in the present embodiment is preferably 5 to 40 μm. If it is too thin it will not function as a solder dam, if it is too thick it will be difficult to open,
This is because the contact with the solder body causes cracks to occur in the solder body. Various resins can be used as the solder resist layer, for example, bisphenol A type epoxy resin,
A resin obtained by curing an acrylate of a bisphenol A type epoxy resin, a novolak type epoxy resin, or an acrylate of a novolak type epoxy resin with an amine curing agent, an imidazole curing agent, or the like can be used. In particular, when forming an opening in the solder resist layer to form a solder bump,
What consists of "novolak type epoxy resin or acrylate of novolak type epoxy resin" and contains "imidazole hardener" as a hardener is preferable.

The solder resist layer having such a structure is as follows.
There is an advantage that migration of lead (phenomenon in which lead ions diffuse in the solder resist layer) is small. Moreover, this solder resist layer is a resin layer obtained by curing an acrylate of a novolak type epoxy resin with an imidazole curing agent, has excellent heat resistance and alkali resistance, does not deteriorate even at a temperature at which solder is melted (around 200 ° C.), and does not deteriorate. It is not decomposed by a strongly basic plating solution such as plating or gold plating. However, since such a solder resist layer is formed of a resin having a rigid skeleton, peeling is likely to occur. The roughened layer formed on the conductor circuit is effective for preventing such peeling.

Here, as the acrylate of the novolak type epoxy resin, an epoxy resin obtained by reacting glycidyl ether of phenol novolak or cresol novolak with acrylic acid, methacrylic acid or the like can be used. The imidazole curing agent is desirably liquid at 25 ° C. This is because a liquid can be uniformly mixed. As such a liquid imidazole curing agent, 1-benzyl-2-methylimidazole (product name: 1B2MZ
), 1-cyanoethyl-2-ethyl-4-methylimidazole (product name: 2E4MZ-CN), and 4-methyl-2-ethylimidazole (product name: 2E4MZ). The addition amount of the imidazole curing agent is desirably 1 to 10% by weight based on the total solid content of the solder resist composition. The reason for this is that if the added amount is within this range, uniform mixing is easy.

The composition before curing of the solder resist is as follows:
It is desirable to use a glycol ether-based solvent as the solvent. The solder resist layer using such a composition does not generate free oxygen and does not oxidize the copper pad surface. It is also less harmful to the human body. As such a glycol ether solvent, one having the following structural formula, particularly preferably at least one selected from diethylene glycol dimethyl ether (DMDG) and triethylene glycol dimethyl ether (DMTG) is used. This is because these solvents can completely dissolve benzophenone and Michler's ketone as reaction initiators by heating at about 30 to 50 ° C. CH ₃ O— (CH ₂ CH ₂ O) _n —CH ₃ (n = 1 to 5) The glycol ether solvent is preferably 10 to 40% by weight based on the total weight of the solder resist composition.

In addition to the solder resist composition described above, various antifoaming agents and leveling agents, thermosetting resins for improving heat resistance and base resistance and imparting flexibility,
A photosensitive monomer or the like can be added to improve the resolution. For example, as the leveling agent, one made of a polymer of an acrylate ester is preferable. The initiator is preferably Irgacure I907 manufactured by Ciba-Geigy, and the photosensitizer is DETX-S manufactured by Nippon Kayaku.

Further, a dye or a pigment may be added to the solder resist composition. This is because the wiring pattern can be hidden. It is desirable to use phthalocyanine green as this dye.

As the thermosetting resin as an additional component, a bisphenol type epoxy resin can be used. This bisphenol type epoxy resin includes a bisphenol A type epoxy resin and a bisphenol F type epoxy resin, and when importance is attached to base resistance, the former is required to reduce viscosity (when importance is attached to coating properties). The latter is better.

As the above-mentioned photosensitive monomer as an additional component, a polyvalent acrylic monomer can be used.
This is because the polyvalent acrylic monomer can improve the resolution. For example, polyacrylic monomers such as Nippon Kayaku's DPE-6A or Kyoeisha Chemical's R-604 are desirable. These solder resist compositions are more desirably 0.5 to 10 Pa · s at 25 ° C. Is preferably 1 to 10 Pa · s. This is because the viscosity is easy to apply with a roll coater. After the formation of the solder resist, an opening is formed. The opening is formed by exposure and development processing.

Thereafter, a nickel plating layer is formed on the opening by electroless plating after the formation of the solder-resist layer.
Nickel sulfate 4.5 as an example of the composition of the nickel plating solution
g / l, sodium hypophosphite 25 g / l, sodium citrate 40 g / l, boric acid 12 g / l, thiourea 0.1 g.
There is 1 g / l (PH = 11). With a degreasing solution, the opening of the solder-resist layer, the surface is washed, a catalyst such as palladium is applied to the conductor portion exposed in the opening, activated, and immersed in a plating solution to form a nickel plating layer. Was. The thickness of the nickel plating layer is 0.5 to 20 μm,
Particularly, a thickness of 3 to 10 μm is desirable. If the thickness is less than 0.5 μm, it is difficult to establish a connection between the solder bump and the nickel plating layer. If the thickness is more than 20 μm, the solder bump formed in the opening cannot be completely accommodated and peels off.

After forming the nickel plating layer, a gold plating layer is formed by gold plating. The thickness is 0.03 μm.
By applying gold plating, the rust of the conductor circuit can be prevented.

After applying a metal layer to the opening, a solder paste is printed in the opening to form a solder bump in the opening. Thereafter, the solder bumps are fixed in the openings through nitrogen reflow at a temperature of 250 ° C.

Thereafter, contamination of the surface of the solder bump and an oxide film on the surface of the solder resist were removed by oxygen plasma, and a roughened layer was formed. In a vacuum state, the plasma radiation amount was 500 to 1000 W, the oxygen supply amount was 100 to 500 sec./M, and the oxygen supply pressure was 0.1.
The test was performed at 5 MPa for a processing time of 1 to 15 minutes. In particular, the processing time is preferably less than 10 minutes. This is because the solder resist layer is not damaged and the printed characters do not peel or chip. By this treatment, the surface of the solder resist layer is reduced to a value close to 8 ° at a contact angle of 40 ° or less,
The maximum roughness (Rj) was set to 0.1 to 100 nm. In addition,
In this embodiment, oxygen, nitrogen,
It can be carried out with at least one kind selected from carbon dioxide gas and carbon tetrafluoride.

Character printing was performed on the surface of the solder resist layer. As the ink to be used, a product name, a lot number, a target mark, and the like were formed using a thermosetting resin. The letters were hardened by heat curing. Here, the wettability of the solder resist surface is improved by the plasma treatment, and the target mark can be printed clearly.

Then, the substrate is cut into individual pieces. Thereafter, a printed wiring board was obtained through a checker process for confirming a short circuit / break of the wiring.

After performing the plasma processing after the plasma processing, solder bump formation and character printing may be performed. In this method, the number of times of the plasma processing can be reduced.

The step of dividing into individual pieces and the checker step may be performed at any time after the formation of the solder bumps, but may be performed after the plasma step and the character printing step. The reason for this is that the productivity is good, and defects between steps (solder bump contamination, substrate contamination) and the like are unlikely to occur.

[0054]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. First, the configuration of the multilayer printed wiring board 10 according to the first embodiment of the present invention will be described with reference to FIGS. 7 is a sectional view of the multilayer printed wiring board 10, FIG. 8 is a plan view of the multilayer printed wiring board 10 shown in FIG. 7, and FIG.
The state in which the C chip 90 is attached and placed on the daughter board 94 is shown. Here, the AA section in FIG. 8 corresponds to the sectional view in FIG. As shown in FIG. 7, in the multilayer printed wiring board 10, conductor circuits 34, 34 are formed on the front and back surfaces of the core substrate 30, and further, the conductor circuits 34, 3
4, the build-up wiring layers 80A and 80B are formed. The built-up layers 80A and 80B include an interlayer resin insulation layer 50 having via holes 60 and conductor circuits 58 formed therein, and an interlayer resin insulation layer 150 having via holes 160 and conductor circuits 158 formed therein. A solder resist 70 is formed on the upper layer of the via hole 160 and the conductor circuit 158, and the via hole 160 and the conductor circuit 1 are formed through the opening 71 of the solder resist 70.
58 are formed with bumps 76U and 76D.

As shown in FIG. 9, the solder bumps 76U on the upper surface of the multilayer printed wiring board 10 are connected to the lands 92 of the IC chip 90. On the other hand, the lower solder bump 76
D is connected to a land 96 of the daughter board 94. Here, the multilayer printed wiring board 10 and the IC chip 90
And between the multilayer printed wiring board 10 and the daughter board 94 are filled with an underfill 88 and sealed with a resin.

As shown in FIG. 8, which is a plan view of the multilayer printed wiring board 10 in FIG. 7, the solder bump 76U is disposed at the center of the printed wiring board. The solder bump 76
On the outer periphery of U, a cross-shaped target mark 96A indicating a reference position for mounting the IC chip 90 on the solder bump 76U is formed by printing. Similarly, on the solder resist 70, a circular target mark 96B and a triangular target mark 96C indicating a reference position at the time of attachment to the daughter board 94 are printed. Further, on the solder resist 70, a bar code 98a, a product name (product recognition character: 218AHM) and a lot number (manufacturing recognition) for automatically recognizing a product by a mounting device for mounting the IC chip on the multilayer printed wiring board 10. Character information 98b consisting of characters: 3156) is printed.

The above-described cross-shaped target mark 96A
Are printed 5 mm apart from the solder bump 76U.
The character information 98b is printed at a distance of 8 mm from the solder bump 76U. That is, by printing away from the solder bumps 76U, ink is prevented from scattering to the solder bumps 76U during printing.

As will be described later, in the present embodiment, after the solder resist layer 70 is subjected to plasma treatment to increase the wettability,
Since the target marks 96A, 96B, 96C, the barcode 98a, and the character information 98b are printed, the character printing ink is hard to be repelled and can be formed clearly. Therefore, the IC chip 90 is mounted and the daughter board 9 is mounted on the basis of the target marks 96A, 96B, 96C.
4 can be mounted accurately. Further, since the wettability of the solder resist layer 70 is improved, the solder resist layer 70 can be firmly bonded to the IC chip 90 and the daughter board 94 by the underfill 88.

Next, a method of manufacturing the multilayer printed wiring board 10 will be described. Here, first, A. A. used in the method of manufacturing the multilayer printed wiring board of the first embodiment is described. Adhesive for electroless plating, B. Interlayer resin insulation, C.I. Resin filler,
D. The composition of the solder resist raw material composition will be described.

A. Raw material composition for preparation of adhesive for electroless plating (adhesive for upper layer) [Resin composition] 80 wt% of 25% acrylate of cresol novolak type epoxy resin (Nippon Kayaku, molecular weight 2500)
35% by weight of a resin solution dissolved in DMDG at a concentration of 3.15% and a photosensitive monomer (Toa Gosei Co., Aronix M315) 3.15
Parts by weight, 0.5 parts by weight of an antifoaming agent (manufactured by San Nopco, S-65)
3.6 parts by weight of NMP were obtained by stirring and mixing. [Resin composition] Polyether sulfone (PES) 12
Parts by weight, epoxy resin particles (manufactured by Sanyo Chemical Industries, polymer pole) with an average particle size of 1.0 μm, 7.2 parts by weight, average particle size
After mixing 0.59 μm of 3.09 parts by weight,
30 parts by weight of MP was added, and the mixture was stirred and mixed with a bead mill to obtain. [Curing agent composition] Imidazole curing agent (Shikoku Chemicals,
2E4MZ-CN), 2 parts by weight of a photoinitiator (Circa Geigy, Irgacure I-907), 0.2 parts by weight of a photosensitizer (Nippon Kayaku, DETX-S), and 1.5 parts by weight of NMP are stirred and mixed. I got it.

B. Raw material composition for preparing interlayer resin insulation agent (adhesive for lower layer) [Resin composition] 80 wt% of 25% acrylate of cresol novolak type epoxy resin (Nippon Kayaku, molecular weight 2500)
% Of a resin solution dissolved in DMDG at a concentration of 35%, 4 parts by weight of a photosensitive monomer (Alonix M315, manufactured by Toagosei Co., Ltd.), 0.5 parts by weight of an antifoaming agent (S-65, manufactured by San Nopco), N
3.6 parts by weight of MP were obtained by stirring and mixing. [Resin composition] Polyether sulfone (PES) 12
After mixing 14.49 parts by weight of an epoxy resin particle (manufactured by Sanyo Chemical Industries, polymer pole) having an average particle size of 0.5 μm, 30 parts by weight of NMP was further added, and the mixture was stirred and mixed with a bead mill. [Curing agent composition] Imidazole curing agent (Shikoku Chemicals,
2E4MZ-CN), 2 parts by weight of a photoinitiator (Circa Geigy, Irgacure I-907), 0.2 parts by weight of a photosensitizer (Nippon Kayaku, DETX-S), 1.5 parts by weight of NMP I got it.

C. Raw material composition for resin filler preparation [Resin composition] 100 parts by weight of bisphenol F type epoxy monomer (manufactured by Yuka Shell, molecular weight 310, YL983U), having an average particle diameter of 1.6 μm coated with a silane coupling agent on the surface SiO ₂ spherical particles (Admatech, CRS
1101-CE, where the maximum particle size is 170 parts by weight of the inner layer copper pattern described below (15 μm or less) and 1.5 parts by weight of a leveling agent (manufactured by San Nopco, Perenol S4) by stirring and mixing. The viscosity of the mixture is 23 ±
It was obtained by adjusting to 45,000 to 49,000 cps at 1 ° C. [Curing agent composition] Imidazole curing agent (Shikoku Chemicals,
2E4MZ-CN) 6.5 parts by weight.

D. Raw Material Composition of Solder Resist A 60% by weight cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in DMDG was sensitized with an oligomer (molecular weight 4000) having a 50% epoxy group acrylated.
6.67 g, 15.0 g of 80 wt% bisphenol A type epoxy resin (manufactured by Yuka Shell, Epicoat 1001) dissolved in methyl ethyl ketone, imidazole curing agent (manufactured by Shikoku Chemicals,
2E4MZ-CN) 1.6 g, photosensitive acrylic monomer (Nippon Kayaku, R604) 3 g, polyvalent acrylic monomer (Kyoeisha Chemical, DPE6A) 1.5 g, dispersion defoamer (Sannopco) , S-65), and 2 g of benzophenone (Kanto Chemical) as a photoinitiator and 0.2 g of Michler's ketone (Kanto Chemical) as a photosensitizer were added to the mixture. 2.0P at 25 ° C
A solder resist composition adjusted to a · s was obtained. The viscosity was measured using a B-type viscometer (Tokyo Keiki, DVL-B type).
Rotor No.4 for 60rpm, rotor for 6rpm
No.3.

Production of Printed Wiring Board (1) A substrate 1 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 1 mm
copper-clad laminate 30 on which copper foil 32 of μm is laminated
A was used as a starting material (step (A) in FIG. 1). First, this copper clad laminate is drilled and subjected to electroless plating.
The inner layer copper pattern 34 and the through-hole 36 were formed on both surfaces of the substrate by etching in a pattern (step (B)).

(2) The substrate 30 on which the inner layer copper pattern 34 and the through hole 36 are formed is washed with water and dried, and then used as an oxidation bath (blackening bath) as NaOH (10 g / l) and NaClO _2.
(40 g / l), Na ₃ PO ₄ (6 g / l), and an oxidation-reduction treatment using NaOH (10 g / l) and NaBH ₄ (6 g / l) as a reducing bath to form the inner layer copper pattern 34 and the through hole. A roughened layer 38 was provided on the surface of Step 36 (Step (C)).

(3) The raw material composition for preparing the resin filler C was mixed and kneaded to obtain a resin filler.

(4) After preparing the resin filler obtained in the above (3),
The coating and filling were performed between the conductor circuits or in the through holes 36 within 24 hours. The coating was performed by a printing method using a squeegee. In the first printing application, the inside of the through hole 36 was mainly filled and dried at 100 ° C. in a drying furnace for 20 minutes. In the second printing application, the recess formed mainly by the formation of the conductor circuit (inner layer copper pattern) 34 is filled, and the resin filler 40 is filled between the conductor circuit 34 and the conductor circuit 34 and in the through hole 36. After that, it was dried under the above-mentioned drying conditions (step (D)).

(5) The surface of the inner layer copper pattern 34 and the through holes 36 are polished on one side of the substrate 30 after the processing of the above (4) by belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku). Was polished so that the resin filler did not remain on the surface of the land 36a, and then buffed to remove the scratches caused by the belt sander polishing. Such a series of polishing was similarly performed on the other surface of the substrate (step (E) in FIG. 2). Then at 100 ° C for 1 hour, 1
Heat treatment was performed at 50 ° C. for 1 hour to cure the resin filler 40.

Thus, the surface portion of the resin filler 40 filled in the through holes 36 and the like and the inner conductor circuit 3
(4) The roughened layer 38 on the upper surface is removed to smooth both surfaces of the substrate, and the resin filler 40 and the side surfaces of the inner conductor circuit 34 are roughened.
To obtain a wiring board in which the inner wall surface of the through-hole 36 and the resin filler 40 are firmly adhered to each other through the roughened layer 38. That is, by this step, the surface of the resin filler 40 and the surface of the inner layer copper pattern 34 are flush with each other.

(6) The substrate 30 on which the conductor circuit 34 is formed is alkali-degreased and soft-etched, and then treated with a catalyst solution comprising palladium chloride and an organic acid to form Pd.
After applying the catalyst and activating the catalyst, copper sulfate 3.9
× 10 ⁻² mol / l, nickel sulfate 3.8 × 10 ⁻³
mol / l, sodium citrate 7.8 × 10 ⁻³ mo
1 / l, sodium hypophosphite 2.3 × 10 ⁻¹ mol
/ L, surfactant (Surfir 46, manufactured by Nissin Chemical Industry Co., Ltd.)
5) Immersion in an electroless plating solution consisting of 1.1 × 10 ⁻⁴ mol / l, PH = 9, 1 minute after immersion, vertical and horizontal vibrations once every 4 seconds, and A coating layer of a needle-like alloy made of Cu-Ni-P and a roughened layer 42 were provided on the surface of the land of the circuit and the through hole (step (F)). Furthermore, tin borofluoride 0.1 mol / l,
Thiourea 1.0 mol / l, temperature 35 ° C, PH = 1.2
Under the conditions described above, a 0.3 μm thick Sn layer (not shown) was provided on the surface of the roughened layer.

(7) The raw material composition for preparing the interlayer resin insulating agent B was stirred and mixed, and the viscosity was adjusted to 1.5 Pa · s to obtain an interlayer resin insulating agent (for lower layer). Next, the raw material composition for preparing the adhesive for electroless plating of A was stirred and mixed, and the viscosity was adjusted to 7 Pa · s to obtain an adhesive solution for electroless plating (for the upper layer).

(8) On both surfaces of the substrate 30 of (6),
The interlayer resin insulating agent (for lower layer) 44 having a viscosity of 1.5 Pa · s obtained in (7) was applied by a roll coater within 24 hours after preparation,
After standing for 20 minutes in a horizontal state, drying (prebaking) was performed at 60 ° C. for 30 minutes.
After preparing a Pa · s photosensitive adhesive solution (for upper layer) 46
Apply within 20 hours, leave it horizontal for 20 minutes, then
Drying (prebaking) was performed at 30 ° C. for 30 minutes to form an adhesive layer 50α having a thickness of 35 μm (step (G)).

(9) The substrate 3 on which the adhesive layer was formed in the above (8)
A photomask film 51 having a black circle 51a of 85 μmφ printed thereon is brought into close contact with both sides of
Exposure was performed at 00 mJ / cm ² (step (H)). This is DMT
G solution, and then exposed the substrate to 3000 mJ / cm ² with an ultra-high pressure mercury lamp,
Heat treatment (post-bake) at 120 ° C. for 1 hour and then at 150 ° C. for 3 hours to obtain an 85 μmφ opening (via hole forming opening) 48 with excellent dimensional accuracy equivalent to a photomask film A 35 μm interlayer resin insulating layer (two-layer structure) 50 was formed (step (I) in FIG. 3). Note that a tin plating layer (not shown) was partially exposed in the opening 48 serving as a via hole.

(10) The substrate 30 in which the openings 48 are formed is immersed in chromic acid for 19 minutes to dissolve and remove the epoxy resin particles present on the surface of the interlayer resin insulating layer. The surface was roughened, and then immersed in a neutralizing solution (manufactured by Shipley) and then washed with water (step (J)). Further, by applying a palladium catalyst (manufactured by Atotech) to the surface of the substrate subjected to the surface roughening treatment (roughening depth: 6 μm), the catalyst is formed on the surface of the interlayer resin insulating layer 50 and the inner wall surface of the via hole opening 48. Attach a nucleus.

(11) The substrate is immersed in an electroless copper plating aqueous solution having the following composition, and a thickness of 0.6 to 1.2 μm
Was formed (step (K)). [Electroless plating aqueous solution] EDTA 0.08 mol / l Copper sulfate 0.03 mol / l HCHO 0.05 mol / l NaOH 0.05 mol / l α, α'-bipyridyl 80 mg / l PEG 0.10 g / l [Electroless plating conditions] 65 ° C 20 minutes at liquid temperature

(12) A commercially available photosensitive dry film is stuck on the electroless copper plating film 52 formed in the above (11), a mask is placed on the film, exposed at 100 mJ / cm ² , and exposed to 0.8% sodium carbonate. Developed, 15μm thick plating resist 54
Was provided (step (L)).

(13) Next, electrolytic copper plating was performed on the non-resist-formed portion under the following conditions to form an electrolytic copper plating film 56 having a thickness of 15 μm (step (M) in FIG. 4). [Aqueous electrolytic plating solution] Sulfuric acid 2.24 mol / l Copper sulfate 0.26 mol / l Additive (captoside HL, manufactured by Atotech Japan) 19.5 ml / l [Electroplating conditions] Current density 1 A / dm ² hours 65 minutes Temperature 22 ± 2 ° C

(14) After stripping and removing the plating resist 54 with 5% KOH, the plating resist 54 is etched with a mixed solution of sulfuric acid and hydrogen peroxide.
Dissolve and remove the electroless plating film 52 under the plating resist,
A conductor circuit 58 and a via hole 60 each having a thickness of 18 μm (10 to 30 μm) composed of the electroless plating 52 and the electrolytic copper plating film 56 were obtained (step (N)).

The adhesive layer 5 for electroless plating between the conductor circuits 58 was immersed in chromic acid of 80 g / L at 70 ° C. for 3 minutes.
The surface of No. 0 was etched at 1 μm to remove the palladium catalyst on the surface.

(15) The same processing as in (6) is performed, and the conductor circuit 5
A roughened surface 62 made of Cu—Ni—P was formed on the surfaces of the via holes 60 and via holes 60, and the surfaces thereof were further substituted with Sn (step (O)).

(16) By repeating the steps (7) to (14), an interlayer resin insulating layer 160 as an upper layer, a via hole 160 and a conductor circuit 158 are further formed. Further, the roughened layer 16 is formed on the surface of the via hole 160 and the conductive circuit 158.
2 to complete a multilayer printed wiring board (step (P)). Note that, in the step of forming the upper conductive circuit, Sn substitution was not performed.

(17) The multilayer printed wiring board described above
To form solder bumps. Substrate 3 obtained in (16) above
0 on both sides. Solder resist composition explained in
The object 70α was applied in a thickness of 20 μm (step of FIG. 5).
(Q)). Then dry at 70 ° C for 20 minutes and 70 ° C for 30 minutes
After processing, a circular pattern (mask pattern) is drawn
5mm thick photomask film (not shown)
Placed in close contact, 1000mJ / cm ²Exposure with ultraviolet light
DMTG development processing was performed. And then at 80 ° C for 1 hour, 100
1 hour at 120 ° C, 1 hour at 120 ° C, 3 hours at 150 ° C
Heat the solder pad (via hole and its
(Including opening part) with opening 71 (opening diameter 200 μm)
Solder resist layer (thickness: 20 μm) 70 was formed.
(Step (R)).

(18) Then, nickel chloride 2.3 × 10 ⁻¹ m
ol / l, sodium hypophosphite 2.8 × 10 ⁻¹ mol /
l, sodium citrate 1.6 × 10 ⁻¹ mol / l, was immersed in an electroless nickel plating solution having a pH of 4.5 for 20 minutes to form a nickel plating layer 72 having a thickness of 5 μm in the opening 71. . Further, the substrate was washed with 7.6 × 10 ⁻³ mol / l of potassium potassium cyanide and 1.9 × 10 ³ ammonium chloride.
10 ^-1 mol / l, sodium citrate 1.2 × 10 ^-1 m
ol / l, sodium hypophosphite 1.7 × 10 ^-1 mol /
Then, the substrate was immersed in an electroless gold plating solution composed of 1 for 7.5 minutes at 80 ° C. to form a gold plating layer 74 having a thickness of 0.03 μm on the nickel plating layer 72 (step (S)).

(19) Then, solder paste is printed on the opening 71 of the solder resist layer 70 and reflowed at 200 ° C., so that the solder bumps (solder bodies) 76U, 76D
Was formed (step (T) in FIG. 6).

(20) Thereafter, the surface of the solder resist layer 70 was subjected to an oxygen plasma treatment (step (U)). For the oxygen plasma treatment, a plasma cleaning device manufactured by Kyushu Matsushita was used.
W, oxygen supply amount 300 sec./M, oxygen supply pressure 0.1
The test was performed at 5 MPa for a processing time of 10 minutes. With this process,
The surface of the solder resist layer was lowered to a contact angle of 20 °, and the maximum roughness (Rj) was set to 30 nm. At the same time, stains on the surfaces of the solder bumps 76U and 76D were removed.

(21) Character printing was performed on the solder resist (FIG. 7). The viscosity of the ink for character printing of the thermosetting resin is 50,000 cps, and the thickness of the target mark 96A, the circular target mark 96B, and the triangular target mark 9 is 30 μm as described above with reference to FIG.
6C, bar code 98a, and character information 98b were screen printed. After the printing, air bubbles are removed from the ink in a reduced pressure chamber (defoaming treatment), and the ink is dried (drying treatment).
The ink for character printing made of a thermosetting resin was cured by heating in a heating furnace at 100 ° / 30 minutes + 120 ° / 30 minutes (curing treatment). In this embodiment, the solder resist layer 7
Since the wettability is improved by performing a plasma treatment on 0, the ink is not repelled and clear printing can be performed.

(22) The substrate was divided and cut into a corresponding size by a device having a router. That is, since the substrates in the above-described process are for multiple-piece production, they were divided into individual multilayer printed wiring boards. Thereafter, a corresponding multilayer printed wiring board was obtained through a checker process for inspecting a short circuit / break of the multilayer printed wiring board.

Thereafter, the target mark 96A of the multilayer printed wiring board 10 is optically read by an image detection camera, and the solder bumps 76U on the multilayer printed wiring board side and the IC are read.
The solder bumps 76U and the lands 92 are joined by aligning the lands 92 of the chip 90 and performing reflow (see FIG. 9). Here, in the present embodiment, since the target mark 96A can be printed clearly, the IC chip 9
0 can be correctly adjusted to the solder bump 76U.
Also, since the stain on the solder bump 76U has been removed,
It can be appropriately connected to the pad 92 on the IC chip 90 side. Thereafter, an underfill 88 is filled between the IC chip 90 and the multilayer printed wiring board 10. As described above, since the plasma treatment is performed on the solder resist layer 70 to improve the wettability, the underfill 88 can be firmly connected to the multilayer printed wiring board 10 side. Therefore, moisture does not enter the interface between the underfill 88 and the multilayer printed wiring board 10.

Subsequently, the position, alignment, and the like are adjusted by the target marks 96B and 96C of the multilayer printed wiring board 10 by a device for attaching to the daughter board, and the solder bumps 76D of the printed wiring board are connected to the pads 96 on the daughter board 94 side. I do. Thereafter, an underfill 88 is filled between the multilayer printed wiring board 10 and the daughter board 94.

Next, a description will be given of a multilayer printed wiring board according to a comparative example which is configured to compare performance with the multilayer printed wiring board of the present embodiment. (Comparative Example 1) The multilayer printed wiring board of Comparative Example 1 was basically the same as the example, except that no plasma treatment was performed.

(Comparative Example 2) The multilayer printed wiring board of Comparative Example 2 was basically the same as the example, but was subjected to a plasma treatment for 20 minutes.

As described above, the printed wiring boards manufactured in Examples and Comparative Examples 1 and 2 have a contact angle, a maximum height, a character state, a connection failure rate with an IC chip, and a peel with an underfill after mounting. FIG. 10 shows the results of evaluation of a total of five items of the strength test and the reliability test by the PCT test. In the example, the contact angle and the maximum roughness were also good numerical values, there was no character loss, no connection failure at the time of mounting, the peel strength was stronger than the comparative example, and no reliability problem occurred. .

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a multilayer printed wiring board according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 4 is a manufacturing process diagram of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 5 is a manufacturing process diagram of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 6 is a manufacturing process diagram of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 7 is a sectional view of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 8 is a plan view of the multilayer printed wiring board 10 shown in FIG.

9 is a cross-sectional view showing a state where an IC chip is mounted on the multilayer printed wiring board shown in FIG. 7 and is mounted on a daughter board.

FIG. 10 is a table showing the results of tests on the multilayer printed wiring boards according to the first embodiment and Comparative Examples 1 and 2.

[Explanation of symbols]

Reference Signs List 30 core substrate 34 conductive circuit 36 through hole 50 interlayer resin insulating layer 58 conductive circuit 60 via hole 70 solder resist 72 nickel plated layer (metal layer) 74 gold plated layer (metal layer) 76U, 76D solder bump 71 opening 80A, 80B Build-up wiring layer 96A, 96B, 96D Target mark (positioning mark) 98a Barcode 98b Character information 150 Interlayer resin insulation layer 158 Conductor circuit (conductor) 162 Roughened layer (roughened surface)

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H05K 3/38 H05K 3/38 B (72) Inventor Kenji Shimizu 905 Kidocho, Ogaki-shi, Gifu IBIDEN F term in the Ogaki factory (reference) 5E314 AA27 BB06 CC02 DD07 FF01 GG18 5E319 AA03 AB05 BB05 CD26 5E343 AA15 AA17 AA23 DD33 EE36

Claims (9)

[Claims] 1. A method for manufacturing a printed wiring board, comprising at least the following steps (a) to (d): (a)
Forming a solder resist layer by providing an opening exposing at least a part of the conductor on a substrate on which a conductor to be a solder pad is formed; (b) forming a metal layer on the conductor, or A step of forming solder bumps directly on a conductor, (c) a step of performing gas plasma treatment on the surface of the solder resist, and (d) a step of printing on the solder resist layer provided with the solder bumps. 2. A method for manufacturing a printed wiring board, comprising at least the following steps (a) to (d): (a)
Forming a solder resist layer by providing an opening exposing at least a portion of the conductor on a substrate on which a conductor to be a solder pad is formed; (b) performing a gas plasma treatment on the solder resist surface; A) a step of forming a solder bump after forming a metal layer on the conductor or directly on the conductor; and (d) a step of printing on a solder resist layer provided with the solder bump. 3. The method according to claim 1, wherein the maximum height (Rj) of the solder resist surface is set to 0.1 to 100 nm by the gas plasma treatment. 4. The method for manufacturing a printed wiring board according to claim 1, wherein the contact angle of the solder resist layer surface is set to 8 to 40 ° by the gas plasma treatment. 5. The printed wiring board according to claim 1, wherein the plasma treatment is at least one kind selected from oxygen, nitrogen, carbon dioxide, and carbon tetrafluoride. Manufacturing method. 6. The method for manufacturing a printed wiring board according to claim 1, wherein the plasma treatment is performed with oxygen plasma at a radiation amount of 500 to 1000 W for 1 to 15 minutes. . 7. The method for manufacturing a printed wiring board according to claim 1, wherein the printing includes a positioning mark. 8. The printed wiring board according to claim 1, wherein in the step of forming a metal layer on the conductor, a nickel plating layer and a gold plating layer are formed as the metal layer. Manufacturing method. 9. The method according to claim 1, wherein a roughened surface is formed on the conductor surface.