JP2000223702A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent channeling in ion implantation, and to prevent any impurity from damaging an insulating film in a lower layer, and to reduce the increase of the crystal grain diameter of a crystallized amorphous semiconductor film. SOLUTION: A gate insulting film 5 and a multi-crystal Si film 6 are successively formed on an Si substrate 1. The surface of the multi-crystal Si film 6 is exposed by washing treatment, and then an amorphous Si film 7 is formed on the multi-crystal Si film 6. P is ion-implanted into the amorphous Si film 7 of an n channel MOS transistor part, and B is ion-implanted into the amorphous Si film 7 of a p channel MOS transistor part, and then heat treatment is carried out so that the amorphous Si film 7 can be crystallized, and impurity can be activated. A WSi film is formed on the amorphous Si film 7, and patterning is carried out so that a gate electrode can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method suitable for forming a gate electrode of a dual gate type CMOS transistor.

[0002]

2. Description of the Related Art Conventionally, polycrystalline Si doped with impurities has been used as a material for forming a gate electrode of a MOS transistor.
Is used. Polycrystalline S constituting this gate electrode
As the impurity contained in i, an n-type impurity such as phosphorus (P) or arsenic (As) has been used regardless of whether it is an n-channel MOS transistor or a p-channel MOS transistor.

[0003] In recent years, in a CMOS transistor, a low power supply voltage has been attempted to reduce power consumption. Therefore, the threshold voltages _Vth of the n-channel MOS transistor and the p-channel MOS transistor are required to be sufficiently low and symmetric with respect to the transistors. In order to cope with such a demand, in a p-channel MOS transistor, a polycrystalline S
A gate electrode formed of a polycrystalline Si film containing a p-type impurity has been used instead of a gate electrode formed of an i film. Note that a CMOS transistor composed of an n-channel MOS transistor having a gate electrode containing an n-type impurity and a p-channel MOS transistor having a gate electrode containing a p-type impurity as described above is a dual-gate CMOS transistor. Called.

In general, as a method of introducing impurities into a polycrystalline Si film, a thermal diffusion method, an ion implantation method, a method of adding impurities simultaneously with the formation of a polycrystalline Si film, and the like are known. Among these methods of introducing an impurity into a polycrystalline Si film, in forming a gate electrode of a dual gate type CMOS transistor, the conductivity type of the impurity added to the gate electrode differs between an n-channel MOS transistor and a p-channel MOS transistor. Therefore, an ion implantation method is often used. Specifically, a dual gate type CMOS
Of the transistors, n-type impurities such as P and As are ion-implanted into the polycrystalline Si film of the n-channel MOS transistor portion, and the polycrystalline Si film of the p-channel MOS transistor portion is
Generally, ions of a p-type impurity such as boron (B) or boron difluoride (BF ₂ ) are implanted into the film.

[0005]

However, when impurities are implanted into the polycrystalline Si film, there is a concern about channeling. That is, there is a known problem that a part of the impurity ions implanted into the polycrystalline Si film is channeled, so that the gate insulating film below the polycrystalline Si film is damaged (H.
Ito et al., IEDMTech. Digest, p.635 (1997), Reference 1). This problem becomes more remarkable as the thickness of the polycrystalline Si film becomes smaller, and the damage to the gate insulating film also becomes greater.

Therefore, use of an amorphous Si film has been considered as one of the means for solving the above-mentioned problem.
That is, it is considered that the problem of channeling can be avoided by ion-implanting impurities into the amorphous Si film instead of the polycrystalline Si film. However, the amorphous Si film must be subjected to a heat treatment for crystallization and activation of impurities after ion implantation to form a polycrystalline Si film.

However, it is known that a polycrystalline Si film obtained by performing a heat treatment on an amorphous Si film generally has a large crystal grain size (see Document 1 and S.M.
Shimizu et al., Symp.on VLSI Tech.Dig., P.107 (199
7), Reference 2).

According to Document 2, when the crystal grain size of the gate electrode is large, the variation of the threshold voltage _Vth in the MOS transistor increases. for that reason,
Even if a method using an amorphous Si film is adopted as a means for solving the above-described channeling problem, a new problem of variation in the threshold voltage _Vth occurs.

Therefore, an object of the present invention is to avoid channeling in ion implantation, prevent an ion-implanted impurity from damaging an insulating film, and provide a semiconductor device having a crystallized amorphous semiconductor film. An object of the present invention is to provide a method for manufacturing a semiconductor device which can suppress an increase in crystal grain size.

[0010]

In order to achieve the above object, a first aspect of the present invention is a process for forming an insulating film on a semiconductor substrate and a process for forming a polycrystalline semiconductor film on the insulating film. Removing a native oxide film present on the surface of the polycrystalline semiconductor film, forming an amorphous semiconductor film on the polycrystalline semiconductor film, and ion-implanting impurities into the amorphous semiconductor film. And a step of crystallizing the amorphous semiconductor film.

According to a second aspect of the present invention, a step of forming an insulating film on a semiconductor substrate, a step of forming a polycrystalline semiconductor film on the insulating film, and the step of forming a surface of the polycrystalline semiconductor film in an atmosphere containing oxygen Forming an amorphous semiconductor film on a polycrystalline semiconductor film without exposing the semiconductor device to a semiconductor, ion implanting impurities into the amorphous semiconductor film, and crystallizing the amorphous semiconductor film. A method for manufacturing a semiconductor device characterized by the following.

In the first and second inventions, in order to effectively avoid the problem of channeling in ion implantation, the thickness of the amorphous semiconductor film is preferably larger than the thickness of the polycrystalline semiconductor film. large.

According to a third aspect of the present invention, a step of forming an insulating film on a semiconductor substrate, a step of forming a first polycrystalline semiconductor film on the insulating film, and a step of forming a surface of the first polycrystalline semiconductor film Forming an amorphous semiconductor film on the first polycrystalline semiconductor film with the surface of the amorphous semiconductor film exposed, and forming a second polycrystalline semiconductor film on the amorphous semiconductor film with the surface of the amorphous semiconductor film exposed. A method for manufacturing a semiconductor device, comprising: a step of forming a crystalline semiconductor film; a step of implanting impurities into a second polycrystalline semiconductor film; and a step of crystallizing an amorphous semiconductor film. .

In the third invention, in order to expose the surface of the first polycrystalline semiconductor film,
Typically, between the step of forming the first polycrystalline semiconductor film and the step of forming the amorphous semiconductor film, whether a natural oxide film present on the surface of the first polycrystalline semiconductor film is removed or not. ,
Alternatively, the surface of the first polycrystalline semiconductor film is not exposed to the atmosphere or an atmosphere containing oxygen from the step of forming the first polycrystalline semiconductor film to the step of forming the amorphous semiconductor film.

In the third aspect of the present invention, in order to make the surface of the amorphous semiconductor film exposed, typically, the step of forming the amorphous semiconductor film is followed by the step of forming the second polycrystalline semiconductor film. A native oxide film existing on the surface of the amorphous semiconductor film is removed before the step of forming the film, or a second polycrystalline semiconductor film is formed from the step of forming the amorphous semiconductor film. Until the process, the surface of the amorphous semiconductor film is not exposed to the atmosphere or an atmosphere containing oxygen.

In the third aspect, in order to avoid the problem of channeling in ion implantation, preferably,
The thickness of the amorphous semiconductor film is larger than the total thickness of the first polycrystalline semiconductor film and the second polycrystalline semiconductor film.

In the present invention, typically, heat treatment is performed to crystallize the amorphous semiconductor film and activate the impurities. In the present invention,
The heat treatment is typically furnace annealing or rapid heat treatment (RTA), but may be laser annealing.

In the present invention, typically, the semiconductor material in the polycrystalline semiconductor film is Si, but other semiconductor materials may be used.
e may be used.

According to the method of manufacturing a semiconductor device according to the present invention having the above-described structure, after forming an amorphous semiconductor film on a polycrystalline semiconductor film, impurities are ion-implanted into the amorphous semiconductor film. Alternatively, after the amorphous semiconductor film and the second polycrystalline semiconductor film are sequentially formed on the first polycrystalline semiconductor film, impurities are ion-implanted into the second polycrystalline semiconductor film. Accordingly, channeling of impurities in ion implantation can be suppressed by the amorphous semiconductor film.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. In all the drawings of the following embodiments, the same or corresponding portions are denoted by the same reference numerals.

First, the method for fabricating the dual gate type CMOS transistor according to the first embodiment of the present invention will be described. 1 to 4 show a method of manufacturing the dual gate type CMOS transistor according to the first embodiment.

In the method of manufacturing the dual gate type CMOS transistor according to the first embodiment, FIG.
As shown in FIG. 1, first, for example, an LO
An element isolation region 2 made of a field oxide film is formed by the COS method. Next, an n-type well region 3 is formed by selectively ion-implanting an n-type impurity such as P into the Si substrate 1 of the p-channel MOS transistor portion. Next, a p-type well region 4 is formed by selectively ion-implanting a p-type impurity such as B into the Si substrate 1 of the n-channel MOS transistor portion.

Next, a gate insulating film 5 made of a SiO ₂ film is formed on the surface of the active region surrounded by the element isolation region 2 by, for example, a thermal oxidation method. The thickness of the gate insulating film 5 is, for example, 5 nm.

Next, as shown in FIG. 1B, a polycrystalline Si film 6 is formed on the entire surface of the Si substrate 1 by, for example, a chemical vapor deposition (CVD) method. The thickness of the polycrystalline Si film 6 is, for example, 10 nm, and the polycrystalline Si film 6 is formed so that the average crystal grain size is 100 nm or less. In the first embodiment, the average crystal grain size of the polycrystalline Si film 6 is about 30 nm. Here, the CV in the formation of the polycrystalline Si film 6
As an example of the D condition, a monosilane (SiH ₄ ) gas is used as a reaction gas, the substrate heating temperature is 630 ° C., and the pressure is 0.375 Torr (50 Pa).

Next, for example, by performing a cleaning process using a dilute hydrofluoric acid (HF) aqueous solution, the surface of the polycrystalline Si film 6 is formed by contacting the atmosphere with the polycrystalline Si film.
The native oxide film (not shown) on the surface of the film 6 is removed, and the polycrystalline S
Expose i. Here, as an example of the cleaning treatment conditions, the hydrofluoric acid concentration of the dilute hydrofluoric acid aqueous solution is 0.5%, and the cleaning time is 100 seconds.

Next, as shown in FIG. 1C, an amorphous Si (amorphous Si) film 7 is formed on the polycrystalline Si film 6 by, for example, a plasma CVD method. This amorphous Si film 7
Is made larger than the film thickness of the polycrystalline Si film 6, specifically, for example, 50 nm. Here, as an example of CVD conditions for forming the amorphous Si film 7, SiH ₄ gas is used as a reaction gas, the substrate heating temperature is 525 ° C., and the pressure is 0.750 Torr (100 Pa).

Next, as shown in FIG. 2A, a resist pattern 8 is formed by a lithography process so as to cover the p-channel MOS transistor portion. Then, using this resist pattern 8 as a mask, the entire surface of the n-channel MOS transistor portion is formed. Then, an n-type impurity such as P is ion-implanted. Here, as an example of the P ion implantation conditions, the energy is 10 keV and the dose is 2 × 10 4
¹⁵ cm ^-2 . After that, the resist pattern 8 is removed.

Next, as shown in FIG. 2B, a resist pattern 9 is formed by a lithography process so as to cover the n-channel MOS transistor portion, and using this resist pattern 9 as a mask, the entire surface of the p-channel MOS transistor portion is formed. Then, a p-type impurity such as B is ion-implanted. Here, as an example of the ion implantation conditions for B, the energy is 3 keV and the dose is 1 × 10 ^15.
cm ^-2 . After that, the resist pattern 9 is removed.

In the above-described ion implantation of impurities such as P and B, the impurity is ion-implanted into the amorphous Si film 7, so that the channeling problem does not occur and the impurity damages the gate insulating film 5. Never.

Next, by performing a heat treatment, the amorphous S
The crystallization of the i-film 7 and the activation of the ion-implanted impurities are performed. Here, as an example of the heat treatment conditions, a nitrogen (N ₂ ) gas is used as an atmosphere gas, a heating temperature is 1050 ° C., and a heating time is 5 seconds. In the crystallization of the amorphous Si film 7 by this heat treatment, since the natural oxide film does not exist at the interface between the polycrystalline Si film 6 and the amorphous Si film 7 by the above-described cleaning treatment, the amorphous Si film 7 Crystallization is promoted at the interface between silicon and polycrystalline Si film 6. The amorphous Si film 7 is affected by the polycrystalline Si film 6, and the crystal grain size of the crystallized amorphous Si film 7 is reduced.

Next, as shown in FIG.
A tungsten silicide (WSi) film 10 is formed on the crystallized amorphous Si film 7 by a method. This WSi film 1
0 is for lowering the wiring resistance, and its film thickness is, for example, 60 nm. Here, as an example of CVD conditions for forming the WSi film 10, SiH ₄ gas, tungsten hexafluoride (WF ₆ ) gas, and argon (Ar) gas are used as process gases, and the flow rates thereof are 400 sccm and 4 sccm, respectively. And 300scc
m, the substrate heating temperature is 400 ° C., and the pressure is 1 Torr (1.
3 × 10 ² Pa). Thereafter, the WSi film 10, the crystallized amorphous Si film 7, and the polycrystalline Si film 6 are patterned by a lithography process and an etching process. Thereby, the WSi films 10 as wirings are respectively provided on the gate insulating films 5 of the n-channel MOS transistor portion and the p-channel MOS transistor portion.
An n ⁺ type gate electrode 11 and a p ⁺ type gate electrode 12 are formed.

Next, a resist pattern (not shown) is formed by a lithography process so as to cover the p-channel MOS transistor portion. Then, using this resist pattern and the n ⁺ type gate electrode 11 as a mask, for example, An n-type impurity such as As is ion-implanted. Thereby, the n ⁺ -type gate electrode 11 is formed above the p-type well region 4.
In a self-alignment manner, a low concentration source / drain region n with respect to ^- -type semiconductor region 13a is formed. here,
As an example of the ion implantation conditions for As, the energy is 15 keV and the dose is 6 × 10 ¹³ cm ⁻² . After that, the resist pattern is removed.

Next, a resist pattern (not shown) is formed by a lithography process so as to cover the n-channel MOS transistor portion. Then, using this resist pattern and the p ⁺ type gate electrode 12 as a mask, for example, P-type impurities such as BF ₂ are ion-implanted. Thereby, the p ⁺ -type gate electrode 12 is formed above the n-type well region 3.
A p ^- type semiconductor region 14a serving as a low concentration source / drain region is formed in a self-aligned manner. Where B
As an example of conditions for ion implantation of F ₂ , the energy is 10 keV and the dose is 1 × 10 ¹⁴ cm ⁻² . After that, the resist pattern is removed.

Next, as shown in FIG.
After a SiO ₂ film having a thickness of, for example, 100 nm is formed on the entire surface by etching, the SiO ₂ film is etched back to form sidewalls 15 on the side walls of the n ⁺ -type gate electrode 11 and the p ⁺ -type gate electrode 12, respectively. , 16 are formed.

Next, a resist pattern (not shown) is formed by a lithography process so as to cover the p-channel MOS transistor portion, and the resist pattern, the n ⁺ type gate electrode 11 and the side wall 15 are used as a mask. For example, an n-type impurity such as As is ion-implanted into the p-type well region 4. Thereby, as shown in FIG. 4, an n ⁺ type semiconductor region 13 serving as a high concentration source / drain region is formed. Here, as an example of the ion implantation conditions for As, the energy is 30 keV and the dose is 4 × 10 ¹⁵ cm ⁻² . After that, the resist pattern is removed.

Next, a resist pattern (not shown) is formed by a lithography process so as to cover the n-channel MOS transistor portion, and this resist pattern, p ⁺ -type gate electrode 12 and side wall 16 are used as a mask. For example, a p-type impurity such as B is ion-implanted into the n-type well region 3. As a result, ap ⁺ type semiconductor region 13 serving as a high concentration source / drain region is formed. Here, as an example of the ion implantation conditions for B, the energy is 5 keV and the dose is 2 × 10 ¹⁵ cm ⁻² . After that, the resist pattern is removed.

Next, the Si substrate 1 is heated by, for example, the RTA method. Here, as an example of the RTA condition, the substrate heating temperature is 1000 ° C., and the heating time is 10 seconds. Thereby, the impurities in all the diffusion layers are activated.

As described above, the dual gate type CMOS transistor according to the first embodiment is manufactured.

As described above, according to the method of manufacturing the dual gate type CMOS transistor according to the first embodiment, after forming the amorphous Si film 7 on the polycrystalline Si film 6, By implanting predetermined impurities into the Si film 7, channeling problems in the ion implantation method can be avoided, and deterioration of the film quality of the gate insulating film 5 can be prevented. Further, since the amorphous Si film 7 is crystallized without a natural oxide film at the interface between the polycrystalline Si film 6 and the amorphous Si film 7, polycrystalline S
Amorphous Si crystallized due to the influence of the film quality of the i film 6
The crystal grain size of the film 7 can be prevented from increasing. Therefore, the polycrystalline Si film 6 and the crystallized amorphous Si film 7
In a dual gate CMOS transistor having an n ⁺ -type gate electrode 11 and a p ⁺ -type gate electrode 12 formed by stacking
The variation in _th can be prevented, and the reliability thereof can be improved.

Next, a method of manufacturing a dual gate type CMOS transistor according to the second embodiment of the present invention will be described. 5 to 8 show a method of manufacturing the dual gate type CMOS transistor according to the second embodiment.

In the dual gate type CMOS transistor according to the second embodiment, as shown in FIG. 5A, first, an element isolation region 2 made of a field oxide film is formed on a p-type Si substrate 1 by, for example, a LOCOS method. I do. Next, an n-type well region 3 is formed by selectively ion-implanting an n-type impurity such as P into the Si substrate 1 of the p-channel MOS transistor portion. next,
A p-type well region 4 is formed by selectively ion-implanting a p-type impurity such as B into the Si substrate 1 of the n-channel MOS transistor portion.

Next, a gate insulating film 5 made of a SiO ₂ film is formed on the surface of the active region surrounded by the element isolation region 2 by, for example, a thermal oxidation method. The thickness of the gate insulating film 5 is, for example, 5 nm.

Next, as shown in FIG.
A polycrystalline Si film 6 is formed on the entire surface of the Si substrate 1 by the method. The thickness of the polycrystalline Si film 6 is, for example, 10 nm, and the average crystal grain size is about 30 nm. Here, as an example of the CVD conditions for forming the polycrystalline Si film 6, SiH ₄ gas is used as a reaction gas, the substrate heating temperature is 630 ° C., and the pressure is 0.375 Torr (50 Pa).

Next, by performing a cleaning process using, for example, a dilute hydrofluoric acid aqueous solution, a natural oxide film on the surface of the polycrystalline Si film 6 formed by contacting the surface of the polycrystalline Si film 6 with the atmosphere ( (Not shown). Here, as an example of the cleaning treatment conditions, the hydrofluoric acid concentration of the dilute hydrofluoric acid aqueous solution is 0.5%, and the cleaning time is 100 seconds.

Next, as shown in FIG. 5C, an amorphous Si film 7 is formed on the polycrystalline Si film 6 by, for example, a plasma CVD method.
To form The film thickness of the amorphous Si film 7 is
The total thickness of the thickness of the film 6 and the thickness of the polycrystalline Si film to be formed later is made larger, specifically, for example, 40 nm. Here, as an example of the CVD conditions for the amorphous Si film 7, SiH ₄ gas is used as a reaction gas, the substrate heating temperature is 525 ° C., and the pressure is 0.750 Torr (100 P).
a).

Thereafter, the surface of the amorphous Si film 7 is exposed to the atmosphere by performing a cleaning process using, for example, a diluted hydrofluoric acid aqueous solution, thereby removing the natural oxide film formed on the surface. Here, as an example of the conditions of the cleaning treatment, the hydrofluoric acid concentration is 0.5% and the cleaning time is 100 seconds.

Next, as shown in FIG.
A polycrystalline Si film 21 is formed on the amorphous Si film 7 by a method. The thickness of the polycrystalline Si film 21 is, for example, 10 nm. Here, as an example of the CVD conditions for the polycrystalline Si film 21, SiH ₄ gas is used as a reaction gas, the substrate heating temperature is 630 ° C., and the pressure is 0.375 Torr (50 P).
a).

Next, as shown in FIG. 6B, a resist pattern 22 is formed by a lithography process so as to cover the p-channel MOS transistor portion. Then, using the resist pattern 22 as a mask, the n-channel MOS
An n-type impurity such as P is ion-implanted over the entire surface of the transistor portion. Here, as an example of P ion implantation conditions, the energy is 10 keV and the dose is 2 × 1.
0 ¹⁵ cm ^-2 . After that, the resist pattern 22 is removed.

Next, as shown in FIG. 7A, a resist pattern 23 is formed by a lithography process so as to cover the n-channel MOS transistor portion, and using this resist pattern 23 as a mask, the entire surface of the p-channel MOS transistor portion is formed. Then, a p-type impurity such as B is ion-implanted. Here, as an example of ion implantation conditions, the energy is 3 keV and the dose is 1 × 10 ¹⁵ cm.
^-2 .

In the above-described ion implantation of impurities such as P and B, since the amorphous Si film 7 is provided below the polycrystalline Si film 21, the impurities are implanted into the amorphous Si film 7. In addition, the problem of channeling does not occur, and the impurity does not damage the gate insulating film 5.

Next, the amorphous Si film 7 is crystallized by, for example, heat treatment, and the ion-implanted impurities are activated. Here, as an example of the RTA conditions, N ₂ gas is used as the atmosphere gas, the heating temperature is 1050 ° C., and the heating time is 5 seconds. In the crystallization of the amorphous Si film 7 by this heat treatment, the interface between the polycrystalline Si film 6 and the amorphous Si film 7 and the amorphous Si film 7 and the polycrystalline Si film 21 Since no natural oxide film exists at any of the interfaces, crystallization of amorphous Si is promoted at those interfaces. The amorphous Si film 7 is affected by the crystal grains of the lower polycrystalline Si film 6 and the crystal grains of the upper polycrystalline Si film 21, and the crystal grain size is reduced.

Next, as shown in FIG.
The WSi film 10 is formed on the polycrystalline Si film 21 by the method. The formation of the WSi film 10 is for lowering the wiring resistance, and its thickness is, for example, 70 nm. Here, as an example of the CVD conditions in forming the WSi film 10, SiH ₄ gas, WF ₆ gas, and Ar gas are used as process gases, and the flow rates thereof are 400
sccm, 4 sccm, and 300 sccm, the substrate heating temperature was 400 ° C., and the pressure was 1 Torr (1.3 × 10 ² P
a). Thereafter, the WSi film 10, the polycrystalline Si film 21, the crystallized amorphous Si film 7, and the polycrystalline Si film 4 are sequentially patterned by a lithography process and an etching process. As a result, the WSi films 10 as wirings are respectively formed on the gate insulating films 5 of the n-channel MOS transistor portion and the p-channel MOS transistor portion.
The n ⁺ -type gate electrode 24 and the p ⁺ -type gate electrode 25 are formed.

Next, a resist pattern (not shown) is formed by a lithography process so as to cover the p-channel MOS transistor portion. Then, using this resist pattern and the n ⁺ type gate electrode 24 as a mask, the entire surface is formed. For example, an n-type impurity such as As is ion-implanted. Thereby, the n ⁺ -type gate electrode 24 is provided above the p-type well region 4.
In a self-alignment manner, a low concentration source / drain region n with respect to ^- -type semiconductor region 13a is formed. here,
As an example of the ion implantation conditions for As, the energy is 15 keV and the dose is 6 × 10 ¹³ cm ⁻² . After that, the resist pattern is removed.

Next, a resist pattern (not shown) is formed by a lithography process so as to cover the n-channel MOS transistor portion. Then, using this resist pattern and the p ⁺ type gate electrode 25 as a mask, for example, P-type impurities such as BF ₂ are ion-implanted. Thereby, the p ⁺ -type gate electrode 25 is formed above the n-type well region 3.
, Ap ⁻ type semiconductor region 14 a to be a low concentration source / drain region is formed in a self-aligned manner. here,
As an example of BF ₂ ion implantation conditions, the energy is 10 keV and the dose is 1 × 10 ¹⁴ cm ⁻² . After that, the resist pattern is removed.

Next, as shown in FIG.
After a SiO ₂ film having a thickness of, for example, 100 nm is formed on the entire surface by etching, the SiO ₂ film is etched back to form sidewalls 26 on the side walls of the n ⁺ -type gate electrode 24 and the p ⁺ -type gate electrode 25, respectively. , 27 are formed.

Next, as shown in FIG. 8B, a resist pattern (not shown) is formed by a lithography process so as to cover the p-channel MOS transistor portion.
Using this resist pattern, n ⁺ -type gate electrode 24 and sidewall 26 as a mask, n such as As
Type impurities are ion-implanted into the p-type well region 4. As a result, an n ⁺ type semiconductor region 13 serving as a high concentration source / drain region is formed. Here, as an example of the ion implantation conditions for As, the energy is 30 keV and the dose is 4 × 10 ¹⁵ cm ⁻² . After that, the resist pattern is removed.

Next, a resist pattern (not shown) is formed by a lithography process so as to cover the n-channel MOS transistor portion, and this resist pattern, p ⁺ -type gate electrode 25 and side wall 27 are used as a mask. For example, a p-type impurity such as B is ion-implanted into the n-type well region 3. As a result, ap ⁺ type semiconductor region 14 serving as a high concentration source / drain region is formed. Here, as an example of the ion implantation conditions for B, the energy is 5 keV and the dose is 2 × 10 ¹⁵ cm ⁻² . After that, the resist pattern is removed.

Next, the Si substrate 1 is heated by, for example, the RTA method. Here, as an example of the RTA condition, the substrate heating temperature is 1000 ° C., and the heating time is 10 seconds. Thereby, the impurities in all the diffusion layers are activated.

As described above, the dual gate type CMOS transistor according to the second embodiment is manufactured.

According to the method of manufacturing the dual gate type CMOS transistor according to the second embodiment, the polycrystalline S
After the amorphous Si film 7 is formed on the i film 6 and the polycrystalline Si film 21 is further formed thereon, ion implantation of impurities is performed, and the amorphous Si film 7 is subsequently crystallized. Thereby, the same effect as in the first embodiment can be obtained.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above embodiments, and various modifications based on the technical concept of the present invention are possible.

For example, the numerical values, materials, CVD conditions, ion implantation conditions, and heat treatment conditions given in the above-described embodiments are merely examples, and different numerical values, materials, CVD conditions, ion implantation conditions, Heat treatment conditions may be used.

In the first and second embodiments, for example, the removal of the natural oxide film on the surface of the polycrystalline Si film or the amorphous Si film is performed by a cleaning process using a diluted hydrofluoric acid aqueous solution. However, the formation of a polycrystalline Si film or an amorphous Si film is performed in an atmosphere of an inert gas such as N ₂ gas or Ar gas.
Alternatively, it is possible to prevent a natural oxide film from being formed on the surface of the polycrystalline Si film or the surface of the amorphous Si film by performing the treatment continuously in an atmosphere in which the oxygen partial pressure is suppressed by reducing the pressure. Occasionally, it is not necessary to perform the above-described cleaning process.

In the first and second embodiments, for example, a dilute hydrofluoric acid aqueous solution is used for the cleaning process for removing the natural oxide film. However, an ammonium fluoride solution, anhydrous hydrofluoric acid, or the like is used. It is also possible to use.

In the first and second embodiments, for example, the WSi film 10 is formed on the polycrystalline Si film for the purpose of lowering the wiring resistance of the gate electrode. A metal such as W may be formed, and if necessary, the gate electrode can be formed without forming a silicide film (silicide film) or a metal film on the polycrystalline Si film. .

In the first and second embodiments, for example, the present invention is applied to a dual gate type CMOS.
Although the present invention has been applied to the manufacture of a transistor, it can be applied to the manufacture of a single-gate type CMOS transistor, an n-channel MOS transistor, or a p-channel MOS transistor.

[0067]

As described above, according to the first and second aspects of the present invention, a polycrystalline semiconductor film is formed on an insulating film, and the polycrystalline semiconductor film is formed on the polycrystalline semiconductor film with its surface exposed. An amorphous semiconductor film is formed, and after the impurity is ion-implanted into the amorphous semiconductor film, the amorphous semiconductor film is crystallized. It is possible to prevent the ion-implanted impurities from damaging the insulating film below the polycrystalline semiconductor film, and to increase the crystal grain size of the crystallized amorphous semiconductor film. The diameter can be suppressed.

According to the third aspect, the first film is formed on the insulating film.
Forming an amorphous semiconductor film on the first polycrystalline semiconductor film in a state where the surface of the first polycrystalline semiconductor film is exposed; A second polycrystalline semiconductor film is formed over the amorphous semiconductor film in an exposed state, and after the impurity is ion-implanted into the second polycrystalline semiconductor film, the amorphous semiconductor film is crystallized. Thereby, channeling in the ion implantation can be avoided by the amorphous semiconductor, and the ion-implanted impurity can be prevented from damaging the insulating film below the first polycrystalline semiconductor film. An increase in the crystal grain size of the crystallized amorphous semiconductor film can be suppressed.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a method for manufacturing a dual gate type CMOS transistor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing a dual-gate CMOS transistor according to the first embodiment of the present invention.

FIG. 3 is a sectional view showing the method of manufacturing the dual gate type CMOS transistor according to the first embodiment of the present invention;

FIG. 4 is a sectional view showing the method of manufacturing the dual gate type CMOS transistor according to the first embodiment of the present invention;

FIG. 5 is a sectional view showing a method for manufacturing a dual-gate CMOS transistor according to a second embodiment of the present invention.

FIG. 6 is a sectional view illustrating the method of manufacturing the dual-gate CMOS transistor according to the second embodiment of the present invention.

FIG. 7 is a sectional view illustrating a method for manufacturing a dual-gate CMOS transistor according to a second embodiment of the present invention.

FIG. 8 is a sectional view illustrating a method for manufacturing a dual-gate CMOS transistor according to a second embodiment of the present invention.

[Explanation of symbols]

1 ... Si substrate, 5 ... Gate insulating film, 6, 21
..Polycrystalline Si film, 7 ... Amorphous Si film, 10 ...
WSi film, 11, 24... N ⁺ type gate electrode, 12,
25 ... p ⁺ type gate electrode

Continued on the front page F-term (reference) 4M104 AA01 BB01 BB37 BB40 CC05 DD04 DD23 DD43 DD45 DD55 DD80 DD99 FF14 GG10 HH04 HH07 5F040 DA06 DA28 DB03 DC01 EC01 EC04 EC06 EC13 EF02 EF11 EK01 FA03 FA05 FA15 FA19 FB02 FB04 FC03 FC04 BB06 BB07 BB08 BB12 BC06 BE03 BG12 DA17 DA25

Claims (13)

[Claims] A step of forming an insulating film on a semiconductor substrate; a step of forming a polycrystalline semiconductor film on the insulating film; and a step of removing a natural oxide film present on a surface of the polycrystalline semiconductor film. A step of forming an amorphous semiconductor film on the polycrystalline semiconductor film; a step of ion-implanting impurities into the amorphous semiconductor film; and a step of crystallizing the amorphous semiconductor film. A method for manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the heat treatment is performed to crystallize the amorphous semiconductor film and activate the impurities. 3. The semiconductor device according to claim 1, wherein the thickness of the amorphous semiconductor film is larger than the thickness of the polycrystalline semiconductor film.
The manufacturing method of the semiconductor device described in the above. A step of forming an insulating film on the semiconductor substrate, a step of forming a polycrystalline semiconductor film on the insulating film, and exposing a surface of the polycrystalline semiconductor film to an atmosphere containing oxygen. Forming an amorphous semiconductor film on the polycrystalline semiconductor film, ion-implanting impurities into the amorphous semiconductor film, and crystallizing the amorphous semiconductor film. Manufacturing method of a semiconductor device. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the heat treatment is performed to crystallize the amorphous semiconductor film and activate the impurities. 6. The semiconductor device according to claim 4, wherein a thickness of said amorphous semiconductor film is larger than a thickness of said polycrystalline semiconductor film.
The manufacturing method of the semiconductor device described in the above. 7. A step of forming an insulating film on a semiconductor substrate, a step of forming a first polycrystalline semiconductor film on the insulating film, and a step of exposing a surface of the first polycrystalline semiconductor film. Forming an amorphous semiconductor film on the first polycrystalline semiconductor film; and forming a second polycrystalline semiconductor on the amorphous semiconductor film with the surface of the amorphous semiconductor film exposed. A method for manufacturing a semiconductor device, comprising: forming a film; ion-implanting impurities into the second polycrystalline semiconductor film; and crystallizing the amorphous semiconductor film. 8. The method according to claim 7, wherein the amorphous semiconductor film is crystallized and the impurities are activated by performing a heat treatment. 9. A method according to claim 1, wherein a step of forming the first polycrystalline semiconductor film and a step of forming the amorphous semiconductor film are performed.
8. The method according to claim 7, wherein a surface of said first polycrystalline semiconductor film is exposed by removing a natural oxide film present on a surface of said first polycrystalline semiconductor film. Of manufacturing a semiconductor device. 10. A natural oxide film present on a surface of the amorphous semiconductor film is removed between a step of forming the amorphous semiconductor film and a step of forming the second polycrystalline semiconductor film. 8. The method according to claim 7, wherein a surface of the amorphous semiconductor film is exposed. 11. During a period from a step of forming the first polycrystalline semiconductor film to a step of forming the amorphous semiconductor film,
8. The method according to claim 7, wherein a surface of the first polycrystalline semiconductor film is exposed by not exposing the first polycrystalline semiconductor film to an atmosphere containing oxygen. The manufacturing method of the semiconductor device described in the above. 12. During the period from the step of forming the amorphous semiconductor film to the step of forming the second polycrystalline semiconductor film,
8. The semiconductor device according to claim 7, wherein a surface of the amorphous semiconductor film is exposed by not exposing the amorphous semiconductor film to an atmosphere containing oxygen.
The manufacturing method of the semiconductor device described in the above. 13. The film thickness of the amorphous semiconductor film is larger than the sum of the film thickness of the first polycrystalline semiconductor film and the film thickness of the second polycrystalline semiconductor film. The method for manufacturing a semiconductor device according to claim 7, wherein