JP2000236241A - Semiconductor integrated circuit - Google Patents

Abstract

(57) Abstract: An inexpensive semiconductor integrated circuit capable of performing pulse width modulation stably with high accuracy even at a high frequency. A plurality of delay elements are connected in series, and two signals are selectively output from an input signal to each delay element and an output signal from each delay element, and the two signals are selectively output. Generating a first voltage level of the pulse width modulated digital signal by one of the two signals and generating a second voltage level of the pulse width modulated digital signal by the other signal Solves the above problem.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to pulse width modulation (P
The present invention relates to a semiconductor integrated circuit that varies the duty ratio of a digital signal having a fixed period by WM (Pulse Width Modulation).

[0002]

2. Description of the Related Art Conventionally, circuits for performing pulse width modulation include both an analog system and a digital system.

First, an analog pulse width modulator is:
A sawtooth signal generator generates a sawtooth waveform from a digital signal of a predetermined period, a digital (analog-to-analog) converter converts the digital signal for determining the duty ratio into a voltage level corresponding thereto, and a comparator, By comparing the sawtooth waveform output from the sawtooth signal generator with the voltage level output from the DA converter, a digital signal having a different duty ratio is generated at a predetermined cycle.

As such an analog pulse width modulator, for example, a model number AD956 manufactured by Analog Devices, Inc.
One example is a semiconductor integrated circuit.

On the other hand, a digital pulse width modulator is
For example, a digital signal having a frequency n times the frequency of the pulse width modulated digital signal is divided by 1 to n to generate a digital signal having a frequency of 1/2 to 1 / n times the frequency. By combining digital signals having a frequency of 1 to n times the frequency of the modulated digital signal, it is possible to generate a digital signal having a predetermined frequency and an arbitrary width having a duty ratio of 0 to 1 / n.

However, in the pulse width modulator using the analog method, the accuracy of each component or the whole as a whole utilizing the analog technology determines the accuracy of the pulse width modulation.
In order to improve the performance, advanced techniques and adjustments such as trimming are required, and therefore, there is a problem that the yield of products is reduced. In addition, components using analog technology have a problem that the layout area is large and the product cost is increased.

On the other hand, in a pulse width modulator using a digital method, an original clock having a frequency n times the frequency of a digital signal after pulse width modulation and a frequency divider are provided according to the required pulse width modulation resolution. Since it is necessary, it is naturally unsuitable for high-frequency signals.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to provide an inexpensive semiconductor integrated circuit capable of performing stable and accurate pulse width modulation even at a high frequency, in consideration of the problems based on the prior art. It is to provide a circuit.

[0009]

In order to achieve the above object, the present invention provides a plurality of delay elements connected in series, an input signal to each of the delay elements, and an output signal from each of the delay elements. And a selector for selectively outputting two signals from among the two signals, and generating a first voltage level of the digital signal after pulse width modulation by one of the two signals selectively output from the selector. And a pulse signal generator for generating a second voltage level of the digital signal after the pulse width modulation by the other signal.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor integrated circuit according to the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.

FIG. 1 is a conceptual diagram showing the configuration of an embodiment of a semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit 10 of the present invention shown in FIG. 1 performs pulse width modulation to vary the duty ratio of a digital signal having a fixed period. In the case of this embodiment, four delay elements d1, d2, d3, d4, a selector 12, and a pulse signal generator 14.

In the illustrated semiconductor integrated circuit 10, first, the delay elements d1 to d4 delay input signals by a predetermined fixed time corresponding to the delay times of the delay elements d1 to d4, and output the delayed signals. , In this order. The delay times of the delay elements d1 to d4 do not necessarily have to be the same, but it is preferable that the delay times of the delay elements d1 to d4 are equalized. In this embodiment, for the sake of simplicity, the delay times of the delay elements d1 to d4 are assumed to be equal.

In the example shown in FIG. 1, a signal f of a predetermined frequency
Are input to the selector 12 together with the delay element d1. The signals fd1 and fd are output from the delay elements d1 to d4, respectively.
2, fd3, fd4 are output, and the delay elements d1
Signals fd1 to fd3 output from d3 are input to delay elements d2 to d4 at the next stage, respectively.
Is also entered. The signal fd4 output from the delay element d4 is input only to the selector 12.

As shown in the timing chart of FIG.
The signals fd1 to fd4 are a signal f and a signal fd, respectively.
As described above, in the present embodiment, the output is delayed by the same amount of time corresponding to the delay time of the delay elements d1 to d4 with respect to 1 to fd3. That is, the respective delay elements d1 to d4 output signals fd1 to fd4 whose frequency is equal to the signal f and whose phases are different from each other by a time corresponding to the delay time of the delay elements d1 to d4.

In this embodiment, it is assumed that the signal f is inputted from outside the semiconductor integrated circuit 10 of the present invention, and the frequency of the signal f is the pulse width modulated digital signal generated by the semiconductor integrated circuit 10. It shall be equal to the frequency. Further, as the delay element, for example, an inverter, a buffer, or the like can be used, but other delay elements may be used. Alternatively, the output signal of the last-stage delay element may be used as the first-stage input signal and connected in a ring to form a ring oscillator.

Subsequently, the selector 12 outputs signals S0 and S1.
Selects two signals from the signal f input to the first-stage delay element d1 and the signals fd1 to fd4 delayed and output from the respective delay elements d1 to d4,
This is output as signal fR and signal fF. At this time, the same one signal may be selected and output as the signal fR and the signal fF. Note that any conventionally known selector can be applied to the selector 12.

In the present embodiment, as shown in the timing chart of FIG.
1 and the delay elements d1 to d1
From the signals fd1 to fd4 delayed and output from d4,
It is assumed that the signal f is selectively output as the signal fR and the signal fd3 is selectively output as the signal fF. Selector 12
Both the signal fR and the signal fF selectively output from are input to the pulse signal generator 14 described below.

The pulse signal generator 14 generates a first voltage level of the digital signal fO after pulse width modulation by one of the two signals fR and fF selectively output from the selector 12. And the second signal generates a second voltage level of the digital signal after the pulse width modulation. In the present embodiment, as shown in the timing chart of FIG. 2, the high level of the digital signal after pulse width modulation is generated by the signal fR (f), and the signal fF
A low level is generated by (fd3).

The configuration of the pulse signal generator 14 is not limited. For example, various types of latches such as an SR latch, and as shown in FIG. To the signal fF,
A circuit or the like having a configuration in which the data input terminal is connected to a high level may be used. In the present embodiment, the digital signal after pulse width modulation is set to the high level by the signal fR and is set to the low level by the signal fF, but may be set to the opposite.

It is well known to those skilled in the art that obtaining a uniform delay time among a plurality of delay elements is relatively easy due to the similarity of semiconductor elements. That is, by flowing the same current through transistors having the same shape and the same direction, elements that operate at the same speed can be configured. Further, by using a PLL (Phase Lock Loop) technique, it is possible to control the delay time of each delay element and variably control the frequency of the digital signal after pulse width modulation.

FIG. 4 is a conceptual diagram showing the configuration of an embodiment of the semiconductor integrated circuit according to the present invention when the above-mentioned PLL technology is used. The illustrated semiconductor integrated circuit 18 includes a phase comparator 20, an integrator 22, and a VCO (Voltage Control).
rolled Oscillator: 24, frequency divider 2
6, a selector 28 and a pulse signal generating circuit 30.

In this semiconductor integrated circuit 18, first,
The phase comparator 20 outputs a reference signal R of a predetermined frequency.
A phase error between ef and the feedback signal fB supplied from the frequency divider 26 is detected, and a phase error signal for correcting the phase difference is output. The phase error signal output from the phase comparator 20 is input to the integrator 22 and integrated, and the integrator 22 outputs a control voltage having a voltage level corresponding to the pulse width of the phase error signal.

The control voltage output from the integrator 22 is input to the VCO 24, and the VCO 24 changes the oscillation frequency of the output signal according to the control voltage. Here, the VCO 24 is generally configured by connecting an odd number of inverters in a ring shape, and changing a power supply level and a ground level supplied to the odd number of inverters according to a control voltage. By
The oscillation frequency of the output signal is variable.

In the semiconductor integrated circuit 18 of the present invention, as the plurality of delay elements connected in series as shown in FIG. Out of the inputs and outputs of the odd number of inverters forming the signals f0 to f7 having the same frequency and differing, for example, by a time corresponding to the delay time of each inverter forming the VCO 24. I do.

The output signals f0 to f0 output from the VCO 24
One of the signals f0 out of f7 is input to the frequency divider 26, which divides the frequency of the input signal f0 by 1 / n and supplies the frequency to the phase comparator 20 as the feedback signal fB. Thus, the reference signal Ref
And the feedback signal fB from the frequency divider 26 whose oscillation frequency has been changed is repeatedly compared, and the phase and frequency of the reference signal Ref and the feedback signal fB are synchronized (locked).

In the frequency divider 26, the frequency of the signals f0 to f7 output from the VCO 24 is changed by changing the frequency division ratio n of the signal f0 supplied from the VCO 24 to the frequency of the reference signal Ref to n thereof. It can be variable up to twice the frequency.

On the other hand, the output signals f0 to f7 whose oscillation frequencies have been changed by the VCO 24 are all input to the selector 28. The selector 28 controls VC by controlling the signal S.
Two signals are selected from the signals f0 to f7 supplied from O24 and output as signals fR and fF, respectively. The signal fR and the signal fF output from the selector 28 are input to the pulse signal generator 30, and the digital signal fO after the pulse width modulation is generated as described above.

As described above, according to the semiconductor integrated circuit of the present invention, unlike the conventional analog system, there is no need for advanced and high-precision adjustment technology and manufacturing technology, and the conventional digital system does not require the same. Since a high-frequency original clock is not required, a high-precision signal having a stable phase difference can be easily generated using the delay time of one delay element as a minimum unit even at a high frequency. It is possible to obtain a digital signal. Further, the layout area is smaller than that of the analog circuit, and the product cost is lower.

The semiconductor integrated circuit of the present invention is basically as described above. As described above, the semiconductor integrated circuit of the present invention has been described in detail. However, the present invention is not limited to the above embodiment, and various modifications and changes may be made without departing from the gist of the present invention. is there.

[0030]

As described above in detail, in the semiconductor integrated circuit of the present invention, a plurality of delay elements are connected in series, and an input signal to each delay element and an output signal from each delay element are selected. Selectively outputting two signals, and generating a first voltage level of the pulse width modulated digital signal by one of the two selectively output signals;
In addition, the second signal generates the second voltage level of the digital signal after the pulse width modulation by the other signal. Therefore, according to the semiconductor integrated circuit of the present invention, since an original clock having a frequency higher than the frequency after the pulse width modulation is not required, even at a high frequency, the delay time of one delay element can be easily set as a minimum unit. It is possible to generate a highly accurate signal having a specific phase difference and obtain a digital signal having an arbitrary duty ratio. Further, according to the semiconductor integrated circuit of the present invention, since it is a digital circuit, there is an advantage that the layout area is small and the product cost is low as compared with the analog circuit.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram illustrating a configuration of an embodiment of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a timing chart of one embodiment showing the operation of the semiconductor integrated circuit of the present invention.

FIG. 3 is a configuration circuit diagram of an embodiment of a pulse signal generation circuit.

FIG. 4 is a conceptual diagram illustrating a configuration of a semiconductor integrated circuit according to an embodiment of the present invention when a PLL technology is used;

[Explanation of symbols]

 10, 18 semiconductor integrated circuit 12, 28 selector 14, 30 pulse signal generator 16 flip-flop 20 phase comparator 22 integrator 24 VCO 26 frequency divider d1, d2, d3, d4 delay element

Claims (1)

[Claims] A plurality of delay elements connected in series; a selector for selectively outputting two signals from an input signal to each of the delay elements and an output signal from each of the delay elements; The above 2 selectively output from the selector
One of the two signals generates a first voltage level of the pulse width modulated digital signal, and the other signal generates a second voltage level of the pulse width modulated digital signal.
And a pulse signal generator for generating a voltage level of the same.