JP2000340653A - Semiconductor device - Google Patents

Abstract

(57) Abstract: In a multilayer wiring structure including a low dielectric constant interlayer insulating film, H ₂ O is introduced from an opening into the low dielectric constant interlayer insulating film.
Suppress intrusion. SOLUTION: The side wall of the opening is protected by a side wall film having a structure in which a first side wall insulating film and a second side wall insulating film having a lower density than the first side wall insulating film are stacked.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a semiconductor device, and more particularly to a semiconductor device having a low dielectric constant multilayer wiring structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art With the advance of miniaturization technology, the number of elements included in a large-scale integrated circuit is increasing year by year. Along with this, connection patterns for connecting these elements in an integrated circuit have become complicated, and in recent advanced semiconductor integrated circuits, a multilayer wiring structure has been used for interconnection between elements. In the multilayer wiring structure, the wiring pattern
A plurality of layers are formed with an interlayer insulating film interposed therebetween.

In a multilayer wiring structure including such a complicated pattern, a problem of signal delay due to a capacitance of an interlayer insulating film occurs with an increase in wiring length. This is a serious problem particularly in a logic integrated circuit that requires high-speed operation. Further, the capacity of the interlayer insulating film has a great influence on the power consumption of the semiconductor device. Therefore, an increase in the capacity of the interlayer insulating film causes problems such as an increase in capacitor leak current and an increase in junction leak current in a DRAM.

Therefore, in recent large-scale integrated circuits, a low dielectric constant insulating film such as an organic insulating film or an F-doped SiO ₂ film is used as an interlayer insulating film constituting a multilayer wiring structure. Generally, since these low dielectric constant insulating films have a hygroscopic property, a protective film having excellent moisture resistance is formed on the multilayer wiring structure.

[0005]

FIG. 1 (A) and FIG. 1 (B)
Is a conventional semiconductor device having a multilayer wiring structure,
5 shows a step of forming an opening for power supply in a multilayer wiring structure. Referring to FIG. 1A, a wiring pattern 13 made of Al is provided on an Si substrate 11 on which an active element (not shown) such as a MOS transistor is formed via an insulating film 12.
A and a power supply pad 13B are formed, and the wiring pattern 13A and the power supply pad 13B
It is covered with a low dielectric constant interlayer insulating film 14 such as an F-doped SiO ₂ film or an organic insulating film formed by the VD method. Further, the low dielectric constant interlayer insulating film 14 is covered with a SiO ₂ film 15 and a SiN film 16 deposited by a CVD method.

Next, in the step of FIG.
N film 16, SiO ₂ film 15, and low dielectric constant interlayer insulating film 1
4 is patterned by dry etching to form an opening 14A exposing the power supply pad 13B.
In such a structure, even if the interlayer insulating film 14 is protected by the SiO ₂ film 15 and the SiN film 16, it is possible to avoid exposing the interlayer insulating film 14 to the atmosphere in the opening 14A. If the semiconductor device is placed in a high-temperature and high-humidity environment, even if the opening 14A is covered with a conductive pattern,
It is difficult to block the intrusion of H ₂ O along the side wall surface of 4A. Especially when such dry etching is performed,
Even if the interlayer insulating film 14 itself has a hydrophobic surface, the surface may be modified to be hydrophilic as a result of the dry etching, and the H ₂ invading along the side wall surface may be formed. O is easily absorbed. Further, since such an interlayer insulating film 14 generally has a low density,
Moisture resistance is inferior to that of an O ₂ film or the like. As a result, problems occur such as cracks occurring in the interlayer insulating film 14 and an increase in leak current between wirings.

FIG. 2 shows the results of a moisture resistance test performed by the inventor on the structure shown in FIG. 1B in the research on which the present invention is based. In this moisture resistance test, FIG.
The structure (B) was maintained for 160 hours in an environment at a temperature of 121 ° C. and a humidity of 100%, and the change in the leak current between the wiring patterns 13A was measured. Referring to FIG. 2, immediately after the start of the moisture resistance test, the value of the leak current was 10 ⁻¹² to 10 ^−13.
It was about A, but it can be seen that the value of this leak current increased by two digits after the end of the moisture resistance test.

On the other hand, a structure in which the side wall of the opening is covered with a SiON film 16a as shown in FIG. 3 has been proposed. However, in FIG. 3, portions corresponding to the portions described above are denoted by the same reference numerals, and description thereof will be omitted. FIG.
In this configuration, the interlayer insulating film 14 is made of Si
After being covered with the O ₂ film 15, the opening 14A is
The power supply pad 13B is formed so as to expose the power supply pad 13B through the O ₂ film 15 and the interlayer insulating film 14 thereunder. Further, the SiON film 16a replaces the SiN film 16 with the surface of the SiO ₂ film 15 and It is formed by a CVD method so as to cover the side wall surface of the opening 14A.

FIG. 4 shows the results of a moisture resistance test performed by the inventor of the present invention on the conventional structure shown in FIG. Referring to FIG. 4, the moisture resistance test is performed in the same manner as in FIG. 2, but the leakage current between the wiring patterns 13A increases by two digits after the moisture resistance test, as in FIG. It can be seen that In other words, the opening 1 shown in FIG.
The structure in which the 4A side wall surface is covered with the SiON film 16a does not substantially solve the problem of an increase in leakage current in the interlayer insulating film 14, and therefore, the problem of moisture absorption through the opening 14A side wall surface of the interlayer insulating film 14. It can be seen that it is.

On the other hand, FIG. 5 shows a two-layer organic insulating film 1.
7 shows a multilayer wiring structure having a structure in which layers 7 and 18 are stacked.
However, in FIG. 5, portions corresponding to the portions described above are denoted by the same reference numerals, and description thereof will be omitted. Referring to FIG. 5, a first organic insulating film 17 is formed on the insulating film 12 so as to cover the wiring pattern 13A and the power supply pad 13B.
Is formed, and an opening 17A exposing the power supply pad 13B is formed in the organic insulating film 17. Further, a second organic insulating film 18 is formed on the organic insulating film 17 so as to cover the opening 17A. In the organic interlayer insulating film 18, the second organic insulating film 18 is formed so as to be included in the opening 17A. An opening 18A exposing the power supply pad 13B is formed. In the illustrated example, a wiring pattern 17B is formed on the organic insulating film 17 by plating, and another wiring pattern 18B is similarly formed on the organic insulating film 18 by plating.

In such a multilayer wiring structure, since the side wall of the opening 17A in the organic insulating film 17 is covered with the organic insulating film 18, H is introduced into the insulating film 17 through the side wall of the opening 17A. It is believed that the penetration of ₂ O can be minimized. However, in a study performed by the inventor of the present invention on which the present invention is based, as shown in FIG.
When the moisture resistance test was performed on the structure of FIG. 2 under the same conditions as in FIG. 2 or FIG. 4, it was recognized that the leakage current between the wiring patterns 13A increased by two digits or more before and after the moisture resistance test. This is because no matter how the side wall surface of the opening 17A is covered with the organic insulating film 18, the density of the organic insulating films 17 and 18 is so low that H ₂ O penetrating into the film cannot be sufficiently blocked. it is conceivable that.

FIG. 7 shows still another conventional multilayer wiring structure. However, in FIG. 7, portions corresponding to the portions described above are denoted by the same reference numerals, and description thereof will be omitted. In the structure of FIG. 7, after the opening 14A is formed on the low dielectric constant interlayer insulating film 14 made of F-doped SiO ₂ or the like, the SiN
The film 16 is directly deposited so as to cover the side wall surface of the opening 14A. Further, a SiO ₂ film 19 is deposited on the SiN film 16 so as to cover the opening 14A, and a wiring groove 19A is formed using a resist pattern (not shown) so as to include the opening 14A. The wiring groove 19A
Is etched back by RIE until the power supply pad 13B is exposed. As a result of the etch back, a SiN sidewall film 14B is formed so as to cover the sidewall of the opening 14A. Since the side wall of the opening 14A is covered with the side wall film 14B, it is considered that H ₂ O penetrating into the interlayer insulating film 14 from the opening 14A can be minimized.

On the other hand, in the basic research of the present invention conducted by the inventor of the present invention with respect to the structure shown in FIG. 7, as shown in FIG. It was confirmed to show a two-digit increase as in the case of. In other words, it is concluded that in the structure of FIG. 7, even if the side wall surface of the opening 14A is covered with the SiN side wall film 14B, penetration of H ₂ O into the interlayer insulating film 14 cannot be effectively prevented.

Accordingly, it is a general object of the present invention to provide a new and useful semiconductor device which solves the above-mentioned problems, and a method of manufacturing the same. More specific objects of the present invention are:
In a semiconductor device having a multilayer wiring structure, it is an object to minimize a ratio of H ₂ O penetrating into an interlayer insulating film constituting the multilayer wiring structure from an opening formed in the multilayer wiring structure.

[0015]

According to the present invention, there is provided a semiconductor device comprising: a substrate; a multilayer wiring structure including an interlayer insulating film formed on the substrate; An opening extending through the interlayer insulating film in the wiring structure, a first sidewall insulating film covering a sidewall of the interlayer insulating film in the opening, and a first sidewall insulating film in the opening; A second sidewall insulating film covering the sidewall insulating film, wherein the first and second sidewall insulating films have densities different from each other, and each of the first and second sidewall insulating films is According to a semiconductor device having a higher density than an interlayer insulating film, or as described in claim 2, the interlayer insulating film has a density smaller than a density of a SiO ₂ film deposited by a plasma CVD method. 2. The semiconductor device according to claim 1, comprising: More or as described in claim 3, wherein the first sidewall insulating film, according to claim 1, characterized in that it has a greater density than said second sidewall insulation films
4. The semiconductor device according to claim 2, wherein the first sidewall insulating film is made of a material which can serve as an etching stopper for the second sidewall insulating film. The semiconductor device according to any one of Items 1 to 3, or as described in Claim 5, wherein the multilayer wiring structure further includes a protective film covering the interlayer insulating film in addition to the interlayer insulating film. Wherein the opening extends through the protective film in addition to the interlayer insulating film, and the first sidewall insulating film also covers a side wall of the protective film exposed at the opening. Claims 1-4
The problem is solved by the semiconductor device according to any one of the above.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] FIGS.
0 (D) shows the multilayer wiring structure according to the first embodiment of the present invention.
1 shows a manufacturing process of a semiconductor device having the same. See FIG. 9 (A)
However, on the Si substrate 21 covered with the insulating film 22, Al
Wiring pattern 23A and power supply pad 23B
The wiring pattern 23A and the power supply
The pad 23B is covered with the low dielectric constant interlayer insulating film 24.
As the low dielectric constant interlayer insulating film 24, plasma CVD
SiO deposited by the method_TwoFilm density (2.2 g / cm
^Three), For example F-doped SiO _TwoMembrane, yes
SOG film, allyl ether-based insulating film, porous SiO_Two
Film, porous allyl ether-based insulating film, or hydrroge
An nsilsesquieoxane (HSQ) -based insulating film may be used.

Further, the interlayer insulating film 24 is made of plasma C
The SiO ₂ film 25 and the SiN film 26 deposited by the VD method provide about 200 nm and about 500 nm, respectively.
9B, and in the step of FIG.
N film 26, SiO ₂ film 25 and interlayer insulating film 2 thereunder
4 is dry-etched using a resist pattern 27 formed on the SiN film 26 as a mask, and an opening 24A exposing the power supply pad 23B is formed in the SiN film 2
6, formed through the SiO ₂ film 25 and the interlayer insulating film 24.

Further, the resist pattern 27 is removed in the step of FIG.
By performing a heat treatment at 350 ° C. for 5 minutes in an atmosphere of ₂ or NH _3, the side wall surface of the opening 24A that has been modified by the dry etching process of FIG. 9B is stabilized. Further, after the heat treatment step, the SiN
On the film 26, a SiN film 28 is formed to a thickness of typically about 200 nm by a plasma CVD method so as to continuously cover the side wall surface and the bottom surface of the opening 24A. SiO ₂ film is, plasma CVD
The method typically deposits to a thickness of about 200 nm. As a result of such deposition, the SiN film 28 has a thickness of about 70 nm on the side wall surface of the opening 24A, and the SiO ₂ film 29 has a thickness of about 50 nm on the side wall surface of the opening 24A. become.

Further, in the step shown in FIG. 10D, the SiO ₂ film 29 is etched back by dry etching until the SiN film 28 is exposed at the bottom of the opening 24A.
However, by changing the etching gas, the power supply pad 23B
Etch back until is exposed. As a result, the SiN sidewall insulating film 28A has a thickness of about 50 nm in the opening 24A.
The thickness of the SiO ₂ side wall insulating film 29A is about 50
It is formed to a thickness of nm.

FIG. 11 shows the result of measuring the leakage current between the wiring patterns 23A before and after the moisture resistance test for the structure having the two-layered side wall insulating films 28A and 29A on the side wall surface of the opening 24A. Shown in However, the moisture resistance test was conducted at a humidity of 100% and a temperature of 12 as in the previous case.
The test was performed in an environment of 1 ° C. for 160 minutes. Referring to FIG. 11, it can be seen that in the device of FIG. 10D, the leak current hardly changes before and after the moisture resistance test and is suppressed to 10 ⁻¹² to 10 ⁻¹³ A or less. [Second Embodiment] FIG. 12 is a diagram showing a D according to a second embodiment of the present invention.
2 shows a configuration of a RAM 40.

Referring to FIG. 12, a peripheral circuit area 41A and a memory cell area 41B are formed on a p-type Si substrate 41. In the peripheral circuit area 41A, STI element isolation structures 42A and 42B are formed. And 42C, an n-type well (41A) ₁ and a p-type well (41A) _{2 are} defined. Further, wherein the memory cell region _41B, element isolation structures 42D is formed.

In the peripheral circuit area 41A, the n-type wafer
(41A)₁A gate supporting a pair of sidewall insulating films
The gate electrode 43A is formed via the gate insulating film.
The p-type well (41A)_TwoA pair of sidewall insulating films is
Gate electrode 43B is held by a corresponding gate insulating film.
Formed. Further, the n-type well (41A) ₁
Inside, a so-called LD is provided on both sides of the gate electrode 43A.
P forming the D structure^-Diffusion regions 41a, 41c and
p⁺Diffusion regions 41b and 41d are provided in the p-type well.
(41A)_TwoInside, on both sides of the gate electrode 43B,
N to form a similar LDD structure^-Mold diffusion regions 41e, 4
1g and n⁺Mold diffusion regions 41j and 41l are formed.
ing.

Further, in the memory cell region 41B, a gate electrode 43C constituting a word line WL is formed on the Si substrate 41 via a gate insulating film, and a similar word line WL is formed on the element isolation structure 42D. Is formed. The gate electrode 43C and the polysilicon pattern 43D both carry a pair of side wall insulating films, and the Si substrate 41
In the middle, the gate electrode 43 is provided in the memory cell region 41B.
On both sides of C, n ⁻ -type diffusion regions 41 forming an LDD structure
i, 41k and n ⁺ type diffusion regions 41j, 41l are formed.

The gate electrodes 43A to 43C and the polysilicon pattern 43D are covered with a first interlayer insulating film 44. On the interlayer insulating film 44, a bit line pattern BL in the memory cell region 41B is formed with the n ⁺ It is formed in a state of being electrically connected to the mold diffusion region 41j via a contact hole 44A formed in the interlayer insulating film 44.

Further, a second interlayer insulating film 45 is formed on the interlayer insulating film 44 so as to cover the bit line pattern BL, and is formed in the interlayer insulating film 45 in the memory cell region 41B. A polysilicon storage electrode 45A is formed so as to cover the recessed portion so as to contact the n ⁺ -type diffusion region 411 via a contact hole 44B penetrating through the interlayer insulating film 45 and the interlayer insulating film 44. Although FIG. 12 shows that the polysilicon storage electrode 45A crosses the bit line BL in the contact hole 44B, the bit line BL does not actually contact the storage electrode 45A.

A capacitor dielectric film 45B is formed on the storage electrode 45A.
A counter electrode 45C is formed thereon. Further, a third layer is formed on the interlayer insulating film 45 so as to cover the counter electrode 45C.
Is formed, and the third interlayer insulating film 4 is formed.
6, contact holes 46A-4A exposing the p ⁺ -type diffusion regions 41b and 41d and the n ⁺ -type diffusion regions 41f and 41g in the peripheral circuit region 41A.
6D is formed. The contact holes 46A to 46A
D, respective conductor plugs are formed, and the contact holes 46A to 46A are formed on the interlayer insulating film 46.
Wiring patterns 47A to 47D are formed corresponding to 6D. Further, also in the memory cell region 41B, wiring patterns 47E and 47F are formed on the interlayer insulating film 46.

A fourth interlayer insulating film 48 is further formed on the interlayer insulating film 46, and a wiring pattern 49 is formed on the interlayer insulating film 48 in the peripheral circuit region 41A.
A to 49C, and a wiring pattern 49D in the memory cell region 41B. Of these, in the illustrated example, the wiring pattern 49A is the wiring pattern 47A.
Is electrically connected via a contact hole 48A formed in the interlayer insulating film 48.

Further, a fifth interlayer insulating film 50 is formed on the interlayer insulating film 48 so as to cover the wiring patterns 49A to 49D, and a fifth interlayer insulating film 50 is formed on the interlayer insulating film 50 so as to correspond to the peripheral circuit region 41A. Thus, wiring patterns 51A and 51B are formed, and wiring patterns 51C and 51D are formed corresponding to the memory cell region 41B. The wiring patterns 51A and 51B are electrically connected to the wiring patterns 49A and 49C via contact holes 50A and 50B formed in the interlayer insulating film 50, respectively, and the wiring patterns 51A to 51D are F-doped SiO2. ₂ or a low dielectric constant interlayer insulating film 52 made of an organic insulating film. Further, the low dielectric constant interlayer insulating film 52 is protected by a passivation film in which a SiO film 53 and a SiN film 54 are laminated, and an opening 51 exposing the wiring pattern 51A is formed in the passivation film.
A is formed. As the low dielectric constant interlayer insulating film 52, an allyl ether based insulating film, a porous SiO ₂ film, HS
A Q film or the like is possible.

In this embodiment, a high-density sidewall insulating film 52a made of SiN or SiON is formed on the side wall surface of the opening 52A.
A low-density sidewall insulating film 52b of SiO ₂ formed by a plasma CVD method is formed thereon. At this time, as in the previous embodiment, the average thickness of the films 52a and 52b is about 50.
It is preferably at least nm.

The wiring pattern 51A is typically a power supply.
Pad, for example, by wire bonding,
It is electrically connected to the device. With this configuration, the opening
H penetrating into the interlayer insulating film 52 through the opening 51A _TwoO
12, and as a result, the DRAM 40 shown in FIG.
The same effect of reducing the leak current as described in FIG.
It is. Accordingly, the refresh characteristics of the DRAM and
Access speed is also greatly improved as shown in Table 1 below.
Is done.

[0031]

[Table 1]

As described above, the present invention is effective for improving the operating characteristics of a semiconductor memory device such as a DRAM. Third Embodiment FIG. 13 shows a structure of a logic semiconductor device 60 according to a third embodiment of the present invention. Referring to FIG.
A first region 61A and a second region 61B are formed on a p-type Si substrate 61. In the first region 61A, S
The n-type well (61A) ₁ and the p-type well (61A) _{2 are formed} by the TI element isolation structures 62A, 62B and 62C.
Is defined. Also, on the second area 61B _,
STI type element isolation structures 62D, 62E and 6
2F is formed, and the region 6 is formed by the element isolation structure.
1B includes an n-type well (61B) ₁ and a p-type well (61B).
B) ₂ is formed.

In the first region 61A, a gate electrode 63A carrying a pair of sidewall insulating films is formed on the n-type well (61A) ₁ via a gate insulating film, and the p-type well (61A) is formed. ) ₂ gate electrode 63B carrying a pair of sidewall insulation films on is formed through a corresponding gate insulating film. Further, in the n-type well (61A) ₁ , so-called LDDs are provided on both sides of the gate electrode 63A.
P ⁻ type diffusion regions 61a, 61c and p
⁺ -Type diffusion regions 61b and 61d are provided in the p-type well (61A) ₂ on both sides of the gate electrode 63B.
N ⁻ -type diffusion regions 61e, 6 forming a similar LDD structure
1g and n ⁺ type diffusion regions 61j and 61l are formed.

Further, in the memory cell region 61B, a gate electrode 63C is provided via a gate insulating film corresponding to the n-type well (61B) ₁ and a gate corresponding to the p-type well (61B) ₂ is provided. A gate electrode 63D is formed via an insulating film. The gate electrode 63C
Both 63D carry a pair of sidewall insulating films, and in the Si substrate 61, the second region 46B is provided on both sides of the gate electrode 63C with n ⁻ -type diffusion regions 61i and 61k forming an LDD structure. And n ⁺ type diffusion regions 61j and 61
1 and n ⁻ -type diffusion regions 61m and 61n and n ⁺ -type diffusion regions 61o and 61p forming an LDD structure are formed on both sides of the gate electrode 63D.

The gate electrodes 63A to 63D are covered with a first interlayer insulating film 64. On the interlayer insulating film 64, a wiring pattern 65A is formed in the first region 61A.
To 65D correspond to the n ⁺ type diffusion regions 61b and 61b, respectively.
d, and p ⁺ -type diffusion regions 61f and 61h, and contact holes 64A formed in interlayer insulating film 64
It is formed in a state where it is electrically connected via ６４64D. Similarly, on the interlayer insulating film 64, in the second region 61B, wiring patterns 65E to 65H are provided respectively with the p ⁺ -type diffusion regions 61j and 611 and the n ⁺ -type diffusion regions 61f and 61h, and It is formed in a state where it is electrically connected through contact holes 64A to 64D formed in insulating film 64.

The wiring patterns 65A to 65H are covered with an interlayer insulating film 66 formed on the interlayer insulating film 64. On the interlayer insulating film 66, wiring patterns 67A to 67C are formed in the first region A. Further, a wiring pattern 67D is formed in the second region B. In the illustrated example, the wiring pattern 67A is electrically connected to the wiring pattern 65A via a contact hole formed in the interlayer insulating film 66.

The wiring patterns 67A to 67D are covered with another interlayer insulating film 68 formed on the interlayer insulating film 66. On the interlayer insulating film 68, wiring patterns 69A and 69B in the region A are formed. The area B
The wiring pattern 69C is covered with a low dielectric constant interlayer insulating film 70 such as F-doped SiO ₂ or an organic insulating film, and an SiO ₂ film 72 is formed on the low dielectric constant interlayer insulating film 70.
And a passivation film including SiN film 73 is formed. As the low dielectric constant interlayer insulating film 70, an F-doped SiO ₂ film, an allyl ether-based organic insulating film, a porous Si
An O ₂ film or an HSQ film can be used.

An opening 70A is formed in the passivation films 72, 73 and the interlayer insulating film 70 so as to expose the wiring pattern 69A.
A high-density sidewall insulating film 70a made of SiN or SiON and a lower-density low-density sidewall insulating film 70b made of SiO ₂ formed by a plasma CVD method are formed on the side wall surface. . At this time, it is preferable that the average thickness of each of the films 70a and 70b is set to about 50 nm or more on the side wall surface of the opening 70A, as in the previous embodiment.

The wiring pattern 69A is typically a power supply pad of the semiconductor device 60, and is electrically connected to an external device by wire bonding or the like. According to the present embodiment, the characteristics of the low dielectric constant interlayer insulating film are stabilized, and the leakage current is reduced. Therefore, even if the integration density is further improved, problems such as unstable operation of the integrated circuit do not occur. . The present invention is also effective for improving the operation speed of a logic integrated circuit. See the access characteristics in Table 1 above.

Although the present invention has been described with reference to preferred embodiments, the present invention is not limited to such specific embodiments, and various modifications and alterations are possible within the scope of the appended claims. .

[0041]

According to the present invention, in a multilayer wiring structure using a low dielectric constant interlayer insulating film, an insulating film having a high density and a low density insulating film, such as a side wall surface of a contact hole, are exposed to the outside air. Since the structure is protected by the side wall film, the characteristics of the interlayer insulating film are stabilized, the leak current is reduced, and when applied to a DRAM, the refresh characteristics and the access characteristics are improved. A similar increase in operating speed
The present invention is also obtained when the present invention is applied to a logic integrated circuit.

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams showing a manufacturing process of a conventional semiconductor device.

FIG. 2 is a diagram illustrating a problem found in the conventional semiconductor device of FIG. 1;

FIGS. 3A and 3B are diagrams showing a process of manufacturing another conventional semiconductor device. FIGS.

FIG. 4 is a diagram illustrating a problem found in the conventional semiconductor device of FIG. 3;

FIGS. 5A and 5B are diagrams showing a manufacturing process of still another conventional semiconductor device.

FIG. 6 is a diagram for explaining a problem found in the conventional semiconductor device of FIG. 5;

FIGS. 7A and 7B are diagrams showing still another conventional semiconductor device manufacturing process.

FIG. 8 is a diagram illustrating a problem found in the conventional semiconductor device of FIG. 7;

FIGS. 9A and 9B are diagrams (part 1) illustrating the steps of manufacturing the semiconductor device according to the first embodiment of the present invention;

FIGS. 10C and 10D are diagrams (part 2) illustrating the steps of manufacturing the semiconductor device according to the first embodiment of the present invention; FIGS.

FIG. 11 is a diagram illustrating the effect of the first embodiment of the present invention.

FIG. 12 is a diagram showing a configuration of a DRAM according to a second embodiment of the present invention.

FIG. 13 is a diagram showing a configuration of a logic integrated circuit according to a third embodiment of the present invention.

[Explanation of symbols]

11, 21, 41, 61 Substrate 12, 22 Insulating film 13A, 17B, 18B, 23A Wiring pattern 13B, 23B Power pad 14, 24, 44, 45, 46, 48, 50, 52, 6
4, 66, 68, 70 interlayer insulating film 14A, 17A, 17B, 19A, 24A, 52A Opening 15, 19, 25, 29, 53, 72 SiO ₂ film 16, 16a, 26, 28, 54, 73 SiN film 17, 18 Organic insulating film 28A, 52a, 70a SiN side wall insulating film 29A, 52b, 70b SiO ₂ side wall insulating film 41A Peripheral circuit area 41B Memory cell area 41a-411, 61a-61p Diffusion area 42A-42D Element isolation area 43A- 43D Gate electrode 44A, 44B Contact hole 45A Storage electrode 45B Capacitor dielectric film 45C Counter electrode 46A-46D, 48A, 50A-50B Contact hole 47A-47F, 49A-49D, 51A-51D, 6
5A-65H, 67A-67D, 69A-69C Wiring pattern

Continued on the front page F-term (reference) 5F033 QQ09 QQ11 QQ23 QQ31 QQ37 RR04 RR06 RR11 RR25 SS15 TT01 TT07 VV16 XX18 XX27 5F058 BA07 BA20 BD02 BD04 BD06 BD10 BD19 BF07 BJ01 BJ02 5F083 AD45 PR09PR03PR

Claims (5)

[Claims] A multilayer wiring structure including an interlayer insulating film formed on the substrate; an opening extending through the interlayer insulating film in the multilayer wiring structure; A first side wall insulating film covering a side wall of the interlayer insulating film, and a second side wall insulating film covering the first side wall insulating film in the opening; A semiconductor device, wherein sidewall insulating films have different densities, and each of the first and second sidewall insulating films has a higher density than the interlayer insulating film. 2. The method according to claim 1, wherein the interlayer insulating film is formed by a plasma CVD method.
Deposited SiO _TwoHas a density lower than the density of the film
The semiconductor device according to claim 1, wherein: 3. The semiconductor device according to claim 1, wherein said first sidewall insulating film has a higher density than said second sidewall insulating film. 4. The device according to claim 1, wherein the first sidewall insulating film is made of a material that can serve as an etching stopper for the second sidewall insulating film. Semiconductor device. 5. The multilayer wiring structure includes a protective film covering the interlayer insulating film in addition to the interlayer insulating film, and the opening extends through the protective film in addition to the interlayer insulating film. And
The first sidewall insulating film also covers sidewalls of the protective film exposed in the opening.
5. The semiconductor device according to any one of the items 4.