JP2000347712A - Programmable controller - Google Patents

Abstract

(57) [Summary] In a programmable controller in which a plurality of CPU modules share one output module, each CPU module needs a new input module in order to know the output state of the output module. did. SOLUTION: A CPU module 2 transmits a frame of shared mask data to a DO module 3 together with output data. At this time, a data transfer mode control bit is provided in the transmission frame, and when sharing and contention control are not performed, a frame configuration that does not include shared mask data can be adopted. The DO module 3 obtains a new output from the logical result of the shared mask data and output data from each CPU module 2 and its current output state. The reference output notifying the new output is transmitted to each CPU module 2, and the CPU module 2 obtains a DO from the reference output and the shared mask data.
Reference data indicating an output state of the module 3 is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a programmable controller, and more particularly to data output sharing and contention control in a programmable controller.

[0002]

2. Description of the Related Art A plurality of CPU modules 102 and DOs are connected to a bus 101 such as a serial link bus as shown in FIG.
A programmable controller having a multi-CPU configuration in which an (output) module 103 and a DI (input) module 104 are connected is known.

In such a programmable controller, a plurality of CPU modules 102-1 to 102-m
Perform the output by sharing the output point of one DO module 103, the CPU modules 102 sharing this output point determine whether the output state of the DO module 103 is currently ON (= "1"). It is not possible to know whether the state is OFF (= "0"). For example, in FIG.
Even if the PU 102-1 turns off the output state of one output point of the DO module 103-1, the other CPU modules 102-2 to 102-m cannot know this. This means that, for example, the shared DO module 103
-1 is used as the emergency stop signal,
The U module 102-1 is the DO module 103-
1, an emergency stop signal is set in the other CPU modules 102-2 to 102-m, and the emergency stop signal is reset in an application that resets the emergency stop signal after performing an appropriate process. C set
The PU module 102-1 then responds to this emergency stop signal with the other CPU modules 102-2 to 102-m
Does not know whether the emergency stop state has been avoided by performing any countermeasure processing, which is a problem.

For this reason, a DI module 106 is separately added for monitoring the output of the DO module 103 as shown in FIG.
In this case, the output of No. 3 is inputted back. And D
The CPU module 102-1 that outputs “0” to the O module 103-1 is replaced with the other CPU modules 102-2 to
Whether the output is set to "1" by 102-m,
Each of the CPU modules 102-1 to 102-m needs to know the current output state of the DO module 103-1.
The output of the DI module 106 was referred to.

[0005] FIG.
It is an example of the return input of the output of the module 103. In FIG. 17, the station number 0 is used as the station address on the bus 101.
Is output from each output point 105 of the DO module 103-1 to which the station number 1 is set, and is returned to the input point 107 of the DI module 106 to which the station number 1 is set.
The tasks on each CPU module 102 sharing the DO module 103-1 are
When the data is output to the DO module 103-1, the DO module of the station number 0 is specified and output. When the output state of the DO module 103-1 is to be obtained, the DI module of the station number 1 is specified and the data from the DI module 106 is output. Get.

FIG. 18 shows the state of output data on each module and bus in the configuration of FIG. Data transfer by the programmable controller is performed at a constant interval of the same speed as the transfer speed on the serial link bus 1. Also, the operation execution unit in the CPU module 102
An interrupt is input in the same cycle as this data transfer. This cycle is called a tact cycle and is indicated by a vertical dotted line in FIG. Each module performs processing in synchronization with the tact cycle.

The operation execution unit 20 of the CPU module 102
DO module 1 generated by the arithmetic processing performed in step 1
03 is output from the I / O
The data is stored in the address area corresponding to the / O area. Then, this data is transmitted and output as frame data on the bus 101 via the output buffer.

[0010] The DO module 103 of the station number 0 receiving this frame changes the output state of each output point based on the received data. Since the output of the DO module 103 is fed back to the DI module 106 having the station number 1, the output state of the DO module 103 is transmitted and output as frame data on the bus 101 by the DI module 106. 1
02 is stored in the address area corresponding to the station number 1 in the I / O area 02.

FIG. 19 shows a functional block diagram for input / output processing of the CPU module. In the CPU module 102, an operation execution unit 201, an I / O area 202, an output buffer 2
03, input buffer 204, serial link control unit 20
5, an output data transfer table 206 and an input data transfer table 207 are provided.

[0010] The serial link control unit 205
Data necessary for the own station out of the frames transmitted from 1 is taken into the input buffer 204 and sent to the downstream station module. The data taken into the input buffer 204 transfers the data required by the task to the I / O area 202 with reference to the input data transfer table 207 corresponding to the task when the task is activated.

An I / O area 202 is a memory area that can be directly accessed by each task of a plurality of application programs executed in the local station. Reads the data required by itself.

When outputting data to the DO module, the arithmetic execution unit 201 writes the output data to an address area corresponding to the I / O area 202. Then, when the task processing is performed, only the data allocated to the task is transferred from the I / O area 202 to the output buffer 203 based on the output data transfer table 206 during the output processing. Then, the serial link control unit 205 outputs this to the bus 101 as frame data.

[0013]

When the output of the DO module 103-1 is looped back by the DI module 106 as shown in FIG. 17, a separate DI module must be added for this purpose.

An application program executed by each CPU module 102 must use an address different from the station address of the DO module 103-1 in order to know the output state of the DO module 103-1. Therefore, the processing of application programming is complicated.

In each CPU module 102, I
The station address of the DI module 106 for monitoring the output of the DO module 103-1 must be set on the / O area 202. In a programmable controller,
Since the size of the I / O area 202, that is, the total number of connectable modules is limited, the DO module 103-
If the DI module 106 is used to monitor the output state of one, two addresses will be used for one DO module, and resource utilization efficiency will be poor.

In the CPU module 102, the bus 1
01 in the input data from the input buffer 204 in accordance with the input data transfer table 207.
The input data is copied to the area 202, and in the output processing, the output data is copied from the I / O area 202 to the output buffer 203 according to the output data transfer table 206. Therefore, the transfer source address of the output data set in the DO module 103-1 of the station number 0 in the output data transfer table 206 and the input data transfer destination set in the DI module 106 of the station number 1 in the input data transfer table 207 By making the addresses the same, the output state of the DO module 103-1 via the DI module 106 can be input to the same address area as the output destination to the DO module 103-1 of the I / O area 202. However, when the same address area of the I / O area 202 is assigned to input data and output data to the DO module 103-1, there is a problem shown in FIG.

FIG. 20 shows a table 20 in the output data transfer table.
No. 6, the timing indicating the status of input / output on each module and bus when the source address of output data to the DO module and the destination address of input data from the DI module in the input data transfer table 207 in the input data transfer table are the same FIG.

Assume that the operation execution unit 201 outputs OUT2 to the I / O area 202 as output data to the DO module 103 in the tact cycle A of FIG. However, in the next tact cycle B, OUT1 which is the previous output state enters before the return output by the output of OUT2 is transferred to the I / O area 202. If OUT2
Is "1" output from the CPU module as an emergency stop signal, and when OUT1 is "0", referring to the I / O area 202 to obtain the output state of the DO module in the next tact cycle B, OUT1 (“0”), the application program erroneously recognizes that the output of the DO module has been reset to “0” by another CPU.

In general, in a programmable controller having a multi-CPU configuration, in a configuration in which resources assigned to each CPU are completely separated and functions are distributed, input / output sharing and contention do not occur. However, when a multi-CPU is adopted for reasons such as an increase in program capacity and an improvement in processing performance by parallel processing, one input / output module is shared by a plurality of CPUs. In this case, there is a case where a plurality of CPUs perform a competing write for one input / output module. In the development of the program in such a case, there is an annoyance that the user creates and changes the program source while being aware of the conflict control. Further, when the conflict writing is performed, the program of the plurality of CPU modules writes to the same address of the same output module. Whether the address duplication is caused by the conflict writing or an error in the program operation, etc. It is required that it can be easily checked.

The present invention has been made in view of the above problems, and has been developed in consideration of a plurality of CPs.
When the U module shares the DO module, the DO module shared by each CPU module is provided without providing the DI module for monitoring the output of the DO module.
It is an object to provide a programmable controller and an application program development device capable of knowing the output state of a module.

[0021]

SUMMARY OF THE INVENTION A programmable controller according to the present invention is provided with a plurality of CPU modules and at least one output module.

Each of the CPU modules includes a shared mask generation unit and an output data transmission unit. The shared mask generation means generates a shared mask for instructing the output module whether to change the output state.

The output data transmitting means transmits the output data to the output module together with the shared mask. The output module includes an output data receiving unit and a sharing and contention control unit.

The output data receiving means receives the output data from the CPU module together with the shared mask. The sharing and contention control means determines an output state from the output data from the CPU module, for example, from a plurality of CPU modules sharing the same and the shared mask.

The output module includes reference output transmitting means for transmitting a reference output indicating the output state to the plurality of CPU modules sharing the same.
The module includes: a shared mask storage unit that stores the shared mask generated by the shared mask generation unit; and a shared mask stored in the shared mask storage unit and an output state of the output module based on the reference output from the output module. An output state reference data generating means for generating the indicated reference data may be further provided.

Further, when the output data transmitting means does not need to perform sharing and conflict control with the output data from another CPU module in the output module which transmits the output data, the output module transmits the output data. At the time of transmission, the shared mask may be configured not to transmit the output data. In this case, for example, the CPU module further includes data transfer mode control bit generation means for generating a data transfer mode control bit for notifying whether or not the shared mask has been transmitted together with the output data. A data transfer mode control bit is transmitted together with the output data, and the sharing and contention control means of the receiving output module determines when the data transfer mode control bit indicates that the shared mask is not transmitted with the output data. , The output state is determined only from the output data.

Further, the application program development apparatus for a programmable controller according to the present invention includes a program reference unit and a conflict write instruction generation unit.
The program reference means refers to programs of all CPU modules constituting the programmable controller having the multi-CPU configuration.

When the plurality of CPU modules include an instruction indicating the output of the same output module to the same output point, as a result of the reference, the conflicting write instruction generating means converts the instruction into a conflicting write instruction. . The application program development device further includes a warning notifying unit for notifying the user of a part to be converted into the contention writing instruction.

According to the present invention, each CPU module comprises:
The shared mask is transmitted to the output module together with the output data, and the output module performs output sharing and contention control based on the content of the shared mask.

Each of the CPU modules generates the reference data from the reference output transmitted by the reference output transmitting means of the output module and the shared mask stored in the shared mask storage means by the output state reference data generating means. The output state of the output module can be known from.

Further, since the reference data is generated from the reference output from the output module and the shared mask stored in the shared mask storage means, the CPU module stores the output information to the output module and the reference data in the same address area. I can do it.

When the sharing and contention control are not required, if the CPU module does not transmit the shared mask to the output module together with the output data, the amount of traffic can be reduced.

Further, according to the application program development device of the present invention, a write command that causes a conflict write without the user's awareness is converted into a conflict write command. Further, the part converted into the conflict write instruction is notified to the user.

[0034]

FIG. 1 is a diagram schematically showing a programmable controller according to this embodiment. In the programmable controller according to the present embodiment, three CPU modules of CPU modules 2-1 to 2-3 are connected to one D module.
It is assumed that the O module 3 is shared.

When the DO module 3 receives output data transmitted from each CPU module 2 via the serial link bus 1, the DO module 3 controls the output state from the output point based on the received data by the sharing and contention control circuit 10. And transmits data indicating the current output state to each CPU module 2 as a reference output.

In the present embodiment, the data transfer between the CPU module 2 and the DO module 3 is performed by the total frame method and the multicast method disclosed in Japanese Patent Application No. 10-148648 filed by the present applicant. Shall be performed.

FIG. 2 is an explanatory diagram of data communication by the total frame method. In this embodiment, one of the stations of the serial link bus 1 is a ring master station, and the ring master station manages data transfer by a total frame method and a multicast method described later.
In FIG. 2, a ring master station,
Assume that stations A, B, C, and D are connected in this order.

In the total frame method, an REQ frame indicating a request for total frame transmission is transmitted by a ring master station existing only on the network. In FIG. 2, the REQ frame at this time is represented as req0.

In this REQ frame, data indicating that this frame is a REQ frame is set in the delimiter part (start delimiter (SD) part) of the frame, and the receiving station of this frame checks the SD part. Recognizes that this frame is a REQ frame.

The station that has received the REQ frame adds its own data to the end of the frame and transmits it to the adjacent downstream station. In the case of FIG. 2, when the station A receives the REQ frame,
Its own output data Da is added to the end of the
Send to the station. When receiving this frame, the B station adds its own output data Db to the end and outputs it. Thereafter, when each station receives the frame in order, it adds its own data to the end of the frame and transmits it to the downstream station. Note that the present embodiment is a multi-CPU using a plurality of CPU modules 2.
The DO module also outputs its own data so that the CPU module 2 can refer to the data that the other CPU module 2 has output to the DO module. However, in the case of a configuration of a programmable controller having only one CPU module,
There is no need for this.

When the REQ frame goes around the serial link bus 1 and is received by the ring master station, the ring master station starts the start delimiter (S
The data set in section D) is changed to data indicating that it is the second REQ frame, and its own data is added to the end of the frame and transmitted to the next downstream station, station A. .

Upon receiving this frame, the station A checks the SD part of the received frame, and recognizes that this is the second REQ frame, and then finds the next one in the frame following the SD part.
At the round, the own station data added by itself is deleted and relayed to the downstream station. In the case of FIG. 2, when the station A receives the second REQ frame, the station A deletes the data Da of the own station added by itself in the first cycle and transmits the data Da to the downstream station B. It deletes its own output data Db next to the SD section and transmits it to the next downstream station, station C. Thereafter, when each station receives the frame in order, it deletes its own data added in the first round from the frame and transmits it to the downstream station.

When the second REQ frame circulates on the serial link bus 1 and returns to the ring master station, the ring master station removes the frame from the serial link bus 1. This completes the total frame communication.

Next, data transfer by the multicast method will be described. The multicast method is a data transfer method used when outputting data from the CPU module 2 to the DO module 3.

In the multicast system, transmission data for circulating a free token for multicast communication on the serial link bus 1 and outputting data to a station requesting data transmission (output to the DO module is prepared. The station for which transmission permission is set) secures the free token and transmits a multicast frame instead. The multicast frame circulates on the serial link bus 1, and the station on the network that has received the multicast frame relays it downstream and circulates, and also takes in data based on the setting contents of the output data in the frame. .

FIG. 3 is an explanatory diagram of communication by the multicast system. In communication by the multicast method, first, a ring master station that manages only one network on the serial link bus 1 generates a free token for controlling the authority of data transfer and releases the token on the serial link bus 1. With the release of the free token, multicast communication is started.

The released free token is sequentially relayed by each station to downstream stations, and circulates on the serial link bus 1. When receiving the free token, the CPU module 2 that wants to output data secures the free token from the serial link bus 1 and becomes a master station.

The master station sends the prepared transmission data on the serial link bus 1 as a multicast frame in which data indicating that the frame is a multicast communication frame is set in the SD section. In FIG. 3, in place of the held free token, the master station outputs the output data to the two stations, that is, the output data to the station A (M → Da) and the output data to the station B (M → Db) as a multicast frame. B.

The station that has received the multicast frame refers to the station number of the storage destination of the output data set in the output data in the frame, and if the output data is for its own station, takes it in. At the same time, the frame is directly transmitted to the downstream station. In FIG. 3, the stations A and B that have received the multicast frame respectively apply to their own stations and output data (M → Da, M →
Db) is fetched, and the received frame is transmitted as it is to the next downstream station, the ring master station and the master station.

When a frame makes one round, the master station that first transmitted the frame transmits the frame to the serial link bus 1.
And a free token is generated and released on the serial link bus 1 instead.

When the free token returns after making a round of the serial link bus 1, the ring master station checks whether there is a data transmission request, and if there is a request, transmits the transmission data [output data (RM →→ Da) and output data (RM → Db)] to station B. Thereafter, the ring master station removes the free token from the serial link when the data frame transmitted by the own station returns to the own station after making a round of the serial link, thereby ending the multicast communication.

Hereinafter, data transmission when data is transmitted from the DO module 3 to the CPU module 2 is performed by a total frame method. The data transfer when outputting data from the CPU module 2 to the DO module 3 is performed by a multicast method. In the present invention, data transfer between the modules is not limited to the total frame system and the multicast system. The data transfer by the total frame method and the multicast method is based on the premise that each module is connected by a bus of a ring-type transmission topology, but a bus connecting each module in a programmable controller to which the present invention is applied. The configuration is not limited to a serial bus having a ring topology, but may be a configuration in which modules are connected to each other by another topology or a parallel bus.

FIG. 4 shows the sharing and conflict control circuit 10 of the DO module 3 in detail. In the figure, the bottom row shows a frame transmitted on the serial link bus 1, and the DO module 3 sends the frames from the CPU modules 2-1 to 2-1 during one tact cycle.
A frame according to the multicast method from the CPU modules 2-1, 2-2 and 2-3 follows the frame according to the total frame method for 2-3. Note that “message” in the figure indicates a time band for message transfer performed between the CPU modules 2 or between the CPU module 2 and the communication module.

Each of the CPU modules 2-1 to 2-3 has a D
The shared mask is stored in the transmission frame together with the output data to the O module 3, and the DO
Send to module 3. This shared mask specifies, for each output point, whether or not each CPU module 2 changes the output state with respect to the DO module 3.
The module 2 sets “1” to a bit of a shared mask corresponding to an output point whose output state is desired to be changed and “0” to a bit corresponding to an output point not to be changed among a plurality of output points of the DO module 3. Then, the data is transmitted to the DO module together with the output data.

When the DO module 3 receives a multicast frame from all of the CPU modules 2-1 to 2-3 sharing the same, it receives the shared mask data 11 and the output data 12 in the frame and the reference output latch. A new output is obtained from a logical result of the current output state in the device 16 and its own.

In the DO module 3, the shared mask 11 and the output data 12 are extracted from the frame from the CPU module 2.
Are extracted, and these are set to AN for each CPU module 2.
The AND circuit 13 takes an AND value. Further, an AND value of the inversion value of each of the shared masks 11-1 to 11-3 and the output of the reference output latch 16 is obtained by the AND circuit 14.

Then, the OR value of the output of each of the AND circuits 13-1 to 13-3 and the output of the AND circuit 14 is obtained by the OR circuit 15, and this is set as a new output at the output point. Also O
The output of the R circuit 15 is stored in the reference output latch 16 and used for determining the next output, and is output on the serial link bus in a total frame manner, and the output state is sent to each of the CPU modules 2-1 to 2-3. Notice. Thus, for example, the output points corresponding to the bits for which the shared mask data 11-1 to 11-3 from all the CPU modules 2 are “0” retain the previous output state. Also multiple C
The shared mask data 11 from the PU module 2 is "1"
When there are both "1" and "0" as the output data 12, "1" has priority and "1" is output from the corresponding output point.

FIG. 5 is a functional block diagram showing components for input / output processing of the CPU module 2. In the CPU module 2, an operation execution unit 21, an I / O area 22, an output buffer 23, an input buffer 24, a serial link control unit 2
5, an output data transfer table 26, an input data transfer table 27, and a shared mask data area 28.

The arithmetic execution unit 21 for performing the program processing includes:
When it becomes necessary to output data to the DO module from the operation result, the output data is written to an address area of the I / O area 22 corresponding to the DO module. This output data is transferred only from the I / O area 22 to the output buffer 23 based on the output data transfer table 26 when the task processing is performed, based on the output data transfer table 26. Is output to the serial link bus 1 as frame data.

The I / O area 22 is a memory area that can be directly accessed by each task of a plurality of application programs executed in the own station, and is configured on the internal memory of the CPU module. The operation execution unit 21 transfers data required by itself from another module to this I / O
When data is read from the corresponding address area in the O area 22 and output to another module, the output data is written to the corresponding address area. In each CPU module 2, the input module and the output module corresponding to the
In the output data transfer table 26 and the input data transfer table 27, each address area in the I / O area 22 has:
It is associated with 1. Therefore, for example, when the I / O area 22 has an address from 0H to FFH,
Module 2 can exchange data with 256 input / output modules. The position of each bit in each address area is 1: 1 to the input / output point of each input / output module.
For example, when one word is 8 bits, data exchange corresponding to eight input / output points can be performed in one address area.

The output buffer 23 is a buffer for storing output data together with the station number of the output destination, the data size, and the shared mask for each output station. When the task processing is completed, at the time of output processing, output data generated in the task processing is transferred from the I / O area 22 to the output buffer 23 based on the output data transfer table 26. Then, the data in the output buffer 23 is output to the serial link bus 1 by the serial link control unit 25 at a tact cycle irrespective of the processing by the arithmetic execution unit 21. Through such a series of operations, each module connected to the serial link bus 1 can operate using common data during a fixed cycle (tact cycle).

The input buffer 24 is a buffer for taking in data necessary for the local station from data flowing from the upstream station. Data received from the serial link bus 1 is stored in the input buffer 24 from the serial link control unit 25 at the same tact cycle as the transfer cycle of the serial link bus 1. Then, when the task is started, the input data transfer table 27 corresponding to the task is referred to, and the data required by the task is transferred from the input buffer 24 to the I / O area 22.

The serial link control unit 25 fetches the frame transmitted from the serial link bus 1 into its own receiving buffer, sends it to the downstream station if it is not for its own station, and if it is for its own station, It is taken into the input buffer 24 and passed to the downstream station module. Thus, the frame data circulates on the serial link bus 1 in a certain direction. Further, upon receiving the multicast token, the serial link control unit 25
The data in the output buffer 23 is DMA-transferred to the serial link bus 1 as a multicast frame.

The output data transfer table 26 is for associating a station address on the bus 1 of an output destination module with an address of the I / O area 22. The output data transfer table 26 exists for each task, and is referred to when the operation execution unit 21 transfers output data to be output to the DO module from the I / O area 22 to the output buffer 23 by the task processing. When one task process is completed, the arithmetic execution unit 21 refers to the output data transfer table 26 during the output process and transfers only the data assigned to the task from the I / O area 22 to the output buffer 23.

The input data transfer table 27 is for associating the station address on the bus of the module to be input with the address of the I / O area 22, and is used to transfer data from the input buffer 24 to the I / O area 22. This is referred to when performing transfer. The input data transfer table 27
A plurality of addresses exist for each task, and the address of the data used by the task in the input buffer 24, the address of the I / O area 22, and the data size are stored. When data is transferred from the input buffer 24 to the I / O area 22 when the task is activated, the input buffer is used before the task is activated using the input data transfer table 27 corresponding to the task. Only the data used by the task is transferred from 24 to the I / O area 22.

The shared mask data area 28 is a storage area having the same configuration as the I / O area 22, and is formed on the internal memory of the CPU module. The operation execution unit 21 generates a shared mask in the shared mask data area 28. The shared mask is transferred to the output buffer 23 together with the output data of the same address in the I / O area 22 and transmitted to the corresponding DO module 3.

This shared mask is held in the shared mask data area 28 even after transmission to the DO module. When receiving a reference output for notifying its own output state from the DO module 3, the input buffer 2 based on the shared mask in the address area corresponding to the DO module.
4 to the I / O area 22. Also this I / O
When the transfer input processing to the area 22 is completed, the corresponding shared mask is reset to “0”. This will be described later.

FIG. 6 is a diagram showing an example of a shared mask made by the CPU module. When it is necessary to change the output state of the DO module from the result of the task processing, the operation execution unit 21 outputs the shared mask data area 28 together with the output data.
To generate shared mask data. This shared mask data is a plurality of bits of mask data in which each bit corresponds one-to-one with the output point of the DO module, and “1” is assigned to the bit corresponding to the output point of the output point of the DO module that changes the output state. "0" is set to the bit corresponding to the output point not to be changed.
Is set.

The shared mask of FIG. 6 is an example of an 8-bit configuration.
The sharing and competition control for the eight output points are performed by the data of the shared mask. In FIG. 6, based on the operation result of the task processing, the output data to be output to the DO module is such that bit 0 changes from “1” to “0” and bit 4 changes to “0”.
From “1” to “1”, the shared mask data is generated such that bits 0 and 4 whose output states are changed are set to “1” and bits that are not changed are set to “0”, It is stored in the shared mask data area 28.

When the CPU module 2 receives the reference output based on the total frame from the DO module 3, the reference output is stored in the input buffer 24, and then, based on the input data reference table 27, the corresponding address area of the I / O area 22. , But at this time, all data is
The I / O area 22 is not transferred to the
With reference to the shared mask in the shared mask area 28 in the same address area as described above, it is determined whether or not to perform transfer for each bit, and data is exclusively transferred.

The reference output of the bit for which "1" is set in the shared mask indicates the output state of the output point at which it has instructed the DO module to change the output, such as bit 0 or bit 4 in FIG. However, the data received this time has not yet reflected this change. Therefore, if this is directly transferred from the input buffer 24 to the I / O area 22 as the current output state of the DO module, the problem shown in FIG. 20 occurs. Therefore, the reference output of the bit for which the “1” is set in the shared mask is not transferred, the output data value is left as it is as the value indicating the output state of the DO module, and the reference of the bit for which the “0” is set is referred to. Only the output is transferred from the input buffer 24 to the I / O area 22.

After the transfer of the data indicating the output state to the I / O area 22 is completed, the shared mask of the corresponding address area in the shared mask area 28 is reset to “0” to prepare for the generation of the next output data. .

The reset of the shared mask in the shared mask area 28 may be performed at any time when the reference data is rewritten to the I / O area 22, or may be reset in the I / O area 22 before performing the operation by the task processing. A configuration may be adopted in which the copied data and the data in the I / O area 22 after the operation are compared with respect to all the address areas, and all the shared masks are generated collectively.

FIG. 7 shows an example of the structure of a multicast frame transmitted on the serial link bus 1 in order to transmit output data from the CPU module 2 to the DO module 3.

Each CPU module 2 sends out a multicast frame addressed to the DO module 3 for sending output data. The multicast method can transmit data to a plurality of modules in one tact cycle,
Data for a plurality of DO modules can be included in a frame.

In FIG. 7, the multicast frame includes
Output data for a plurality of DO modules is included, and the output data is stored for each DO module together with a station number indicating an output partner station, data size, and mask information.

When receiving the multicast frame, the DO module 3 compares the station number assigned to each output data in the received frame with its own station number information,
If there is a match, the corresponding output data is taken into the input buffer.

FIG. 8 shows two CPUs, CPU0 and CPU1.
FIG. 4 is a timing chart illustrating an example of input / output states on each module and a bus when modules share a DO module. The figure shows that CPU0 sets one output point of the DO module to "1",
Is an example of resetting this to “0”. Note that, for simplification of the description, the figure and the following description show one output point of the DO module, that is, the input and output of 1-bit data.

In FIG. 8, first, the DO shared by CPU 0 is calculated based on the operation result of the task processing in the tact cycle A.
Assume that it is necessary to change the output state from “0” to “1” for one output point of the module. Arithmetic execution unit 2
1 sets “1” as output data in an address area corresponding to the DO module and the output point in the I / O area 22, and corresponds to the same address area as the address of the I / O area 22 in the shared mask area 28. A shared mask with the bit set to "1" is generated and stored.

The output data and the shared mask are transmitted to the DO module as a multicast frame 32-1. In the DO module, based on the CPU0 and the output data from the CPU0 and the shared mask, at the tact cycle B,
The DO module changes the output state. In this case CPU
Since the shared mask of 0 is "1" and the shared mask of CPU1 is "0", the output state reflects the output data from CPU0, and the output state at the output point changes from "0" to "1".

During this time, the reference output for notifying the output state of the DO module is transmitted from the DO module to the total frame 31.
-1 is notified to CPU0 and CPU1. Since the reference output based on the total frame 31-1 does not reflect the output data from the CPU 0 based on the multicast frame 32-1, this is output to the I / O area 22 of the CPU 0 as the output state of the DO module. Is the output “1” set by the CPU
It is erroneously determined that 1 has been reset to "0". However, in the CPU 0, since the shared mask stored in the shared mask area 28 is “1”, the reference output by the total frame 31-1 is not transferred to the I / O area, and the reference data indicating the output state is It remains at “1” set in the tact cycle A. This allows CPU0
Even when the operation execution unit 21 reads out the reference data indicating the output state of the DO module from the I / O area 22 in the operation processing in the tact cycle B, the output set in the tact cycle A is reset by another CPU module. There is no misunderstanding.

When input processing of data to the I / O area 22 by the total frame is completed, the shared mask area 28
The shared mask in the same address area is cleared to "0". As a result, it becomes necessary to newly change the output state of the DO module by the arithmetic processing, and until the shared mask is generated, the reference output from the DO module in the total frame is directly used as the reference data as I / O data.
/ O area 22 is input. In FIG. 8, the reference output of the total frames 31-2, 31-3, and 31-4 is directly input to the I / O area 22 as reference data indicating the output state of the DO module.

In the CPU 1, the reference output from the DO module based on the total frames 31-1 and 31-2 is directly input to the I / O area 22 as reference data. When the CPU 1 detects that the output state of the DO module has changed from “0” to “1” in the tact cycle C, the CPU 1 instructs the DO module to reset the output state from “1” to “0”. Data is generated and stored in the I / O area, and a shared mask in which the corresponding bit is "1" is generated and stored in the shared mask area. These are notified to the DO module as a multicast frame 32-3. In the DO module, the multicast frame 3
If the shared mask in 2-3 is from CPU0, "0",
Since the data from the CPU 1 is “1”, the output state is changed from “1” to “0” by reflecting the output data “0” from the CPU 1. The changed output state is used as a reference output by the total frame 31-4 by the CPU.
0 and the CPU 1 are notified.

As described above, in the programmable controller according to the present embodiment, in the DO module, the contention control of the output from each CPU module can be performed by the shared mask transmitted from the CPU module together with the output data.

When the CPU module receives the reference output from the DO module, it transfers the data to the I / O area with reference to the corresponding shared mask in the shared mask area. No problem occurs even if the same address is set. Next, a second embodiment of the present invention will be described.

In the conventional programmable controller, not only the DO module which is shared with other CPU modules and needs to be controlled in competition but also the D module which is not shared
Even for the O module, the CPU module always sends a frame having a size including the shared mask data onto the serial link bus 1, so that the transmission efficiency on the serial link bus 1 is reduced.

The programmable controller according to the second embodiment takes this point into consideration, and has a configuration in which a transmission frame is changed depending on whether or not a destination requires contention control.

FIG. 9 is a diagram showing a configuration example of a multicast frame according to the second embodiment of the present invention, which corresponds to the frame configuration diagram of the first embodiment in FIG. Second
In the frame configuration according to the embodiment, the data transfer mode control bit is provided in the frame. In this case, the upper reserved bits of the station number part of the input / output module indicating the transmission destination, which is the head part of the frame, are used as the data transfer mode control bits. The data transfer mode control bit is not limited to the position shown in the figure, but may be provided at another position in the frame if it is a specific position, or may be provided independently.

The data transfer mode control bit indicates whether or not to perform data transfer control using a shared mask. When sharing and contention control are performed during data transfer, this bit is set to “1”, and the sharing and contention control is performed. If there is no need to perform control, a frame with this bit set to "0" is transmitted.

(1) in FIG. 9 shows a frame configuration when sharing and contention control are not performed by the DO module of the transmission destination. The data transfer mode control bit at the head of the frame is set to "0". This frame does not include shared mask data, but is composed of station numbers, sizes, and output data. FIG. 2B shows a frame configuration when sharing and contention control are performed. The data transfer mode control bit is set to “1”, and the frame configuration according to the first embodiment shown in FIG. Similarly, it has a configuration having shared mask data together with output data.

The CPU module that performs data transmission selectively uses these two frames depending on whether the transmission destination is shared and whether contention control is required.
When transmitting output data to an output module shared with another CPU, the output data is transmitted to an output module not shared with another CPU using a frame having a configuration as shown in FIG. 9 (2). In this case, a frame having a configuration as shown in FIG. By using different frames in this way, when it is not necessary to share data output with other CPUs and to perform contention control, extra shared mask data is not included in the frame, so the traffic volume is reduced accordingly and the serial link The data transfer efficiency on the bus 1 is improved.

FIG. 10 is a diagram showing details of the sharing and contention control circuit 40 for determining output data on the DO module side in the second embodiment. FIG. 10 corresponds to the configuration in FIG. 4 of the first embodiment, and the same components are denoted by the same reference numerals.

The sharing and contention control circuit 40 of FIG. 10 is based on the configuration of FIG.
1. A new reception storage register 42, a NOT circuit 43, and an OR circuit 44 are added for each CPU module, and the AND circuit is changed to a three-input AND circuit.
Among these, the value of the data transfer mode control bit in the received multicast frame is set in the shared mask valid mode storage register 41, and the shared and contention control circuit 40 uses the shared mask to perform the shared and contention control according to this value. The mode is switched between the presence mode and the non-shared mask mode in which sharing and conflict control are not performed. The new reception storage register 42 is a register indicating that a new multicast frame has been received. When a new multicast frame is received from a CPU module, the new reception storage register 42 is set to “1” in the new reception storage register 42 corresponding to the CPU module. Is done. When the output of the OR circuit 15 is output from the DO output point and is latched by the reference output latch 16, the output is reset to "0".

The value of the shared mask valid mode storage register 41 is inverted by the NOT circuit 43 and then the OR circuit 44
, An OR value with the shared mask data 11 is obtained. Therefore, when “0” is set in the shared mask valid mode storage register 41, “1” is output from the OR circuit 44,
When “1” is set, the value of the shared mask data 11 is output, and the output data 12
Then, the value in the storage register with new reception 42 and the AND value are taken. For example, when a frame without contention control as shown in FIG. 9A is received, “0” is set to the corresponding shared mask effective mode storage register 41. Also, while there are no newly received multicast frames,
Since the values of the new reception presence storage registers 42-1 to 42-3 are still reset to "0", each AND circuit 45
The outputs from -1 to 45-3 become "0", and the output from the DO output point continues to be the value latched in the reference output latch 16 via the AND circuit 14 and the OR circuit 15.

Next, a shared mask module mode in which each CPU module determines whether to use a frame having no shared mask data (the frame shown in FIG. 9A) or a frame having the shared mask data (the frame shown in FIG. 9B). The method of determination will be described.

FIG. 11 is a diagram showing the logic for determining the shared mask mode. FIG. 11A shows a mode in which a plurality of CPU modules share and conflict with the output point, that is, a mode with a shared mask. ) Shows an example in the case where there is no sharing and contention, that is, in the mode without shared mask data. FIG. 11A shows an example of determining a mode with a sharing mask when sharing data when three CPU modules of CPUs 0 to 2 transmit data to the output modules DO0 and DO1, and 16 points. 16-bit shared mask data for one DO module having an output point
Are used as bits.

In the case of the output module DO0 of FIG. 11A, bit 0 is the CPU1 and CPU2, and bit 10 is the CP.
U0 and CPU2, bit 13 is set to CPU1 and CPU2, and bit 15 is set to "1" in the shared mask by CPU0 and CPU1. It can be seen that the output points of DO0 corresponding to these are competing. Therefore, CPU module C
PU0, CPU1 and CPU2 are output modules DO0
To change the output state of the output point by sending data to
As a sharing mode, a frame including the sharing mask data as shown in FIG. 9B is transmitted as a multicast frame.

Also, in FIG.
In the case of O1, CPU0 uses bits 13, 14, and 15 and CPU1 uses bits 10, 1 and
1 and 12, the CPU 2 uses bits 0, 1, and 2 and is shared by three CPUs. And each C
When transmitting data to the output module DO1, the PU module sends the shared mask data corresponding to the CPU use bit together with the output data in the shared mask mode.

In the case of DO2 in FIG.
Only uses all bits of DO2,
PU2 does not use DO2 at all. That is, DO2
Is an output module controlled only by CPU0, and CP
U0 transmits to the output module DO2 as a multicast frame a frame that does not include the shared mask data as shown in FIG.

FIG. 12 is a diagram showing an example of controlling shared mask data by the CPU module according to the second embodiment. This figure shows an example of the control operation of the common mask when the CPU 0 controls the output of DO 0 under the output conditions of FIG.

In the CPU module CPU0, a fixed shared mask register 51 and an output condition shared mask register 52 are provided to the output module DO0 as shown in FIG.
Are connected to the input of an OR circuit 53 and the output thereof is connected to a serial link output sharing mask register 54. The fixed shared mask register 51 is operated by the OS running on the CPU module, and “1” is set to a bit corresponding to an output point used only by the CPU 0 without competing with another CPU module. The value of the fixed shared mask register 51 remains fixed unless the sharing state of the output point of the DO module is changed. The output condition sharing mask register 52 is a register for setting an output point at which the CPU module changes the output to the DO module. The output condition determination unit 55 sets “1” to a bit corresponding to the output point where the output condition is satisfied. You. The serial link output shared mask register 54 is a register for storing shared mask data to be stored in a multicast frame and transmitted.

The control operation processing for generating the shared mask data when the CPU 0 controls the output of DO0 will be described below. C
PU0 uses bits 1 and 2 of DO0 without conflicting with other CPU modules.
"1" is set in bits 1 and 2 of the fixed shared mask register for O0. The CPU 0 performs an output condition determination for the competitive output point, and when the output condition is satisfied, the output condition determination unit 55 sets “1” to a corresponding bit of the DO0 output condition satisfaction shared mask register 52. In the case of the figure, since the output condition is satisfied at the output point corresponding to the bit 15, "1" is set to the bit 15. An OR value of the values of the fixed shared mask register 51 for DO0 and the shared mask register 52 satisfying the output condition is taken, and the result is set in the serial link output shared mask register 54 for DO0.
In this case, a value in which bits 1, 2, and 15 are set to "1" is set in the serial link output sharing mask register 54. The data in the serial link output shared mask register 54 is transmitted to DO0 together with the output data by multicast frame as shared mask data. In DO0, the output of the output point corresponding to bits 1, 2, and 15 is output from the shared mask data as C and C by the sharing and contention control circuit 40 shown in FIG.
Change based on output data from PU0. Although the output point corresponding to the bit 10 is also controlled by the CPU 0, the output is maintained at the previous value because the output condition was not satisfied this time.

In general, in a programmable controller of a multi-CPU system, when resources assigned to each CPU are completely divided and functions are distributed, input / output sharing and contention do not occur.
In the case where the system control is performed by the PU, the input / output module is shared by a plurality of CPUs when a multi-CPU is adopted for reasons such as coping with an increase in program capacity and improving processing performance by parallel processing. In this case, a conflict WT (write) in which a plurality of CPUs perform write processing may be performed on one input / output module. In the program development in such a case, the user must not have the trouble of creating and changing the program source in consideration of the conflict control. Further, when the conflict WT is performed, writing to the same address of the same DO module is performed by the programs of a plurality of CPUs. Whether the address duplication is caused by the conflict writing or the error of the program work is performed. It is required that checking can be done easily.

To cope with this, in the present invention, a plurality of C
There is a contention WT instruction that performs contention control for writing to the output point shared by the PU, and the user
Even if the application program development device (hereinafter referred to as a loader) does not use the T instruction,
A mechanism for generating a T instruction is provided.

FIG. 13 shows an example of a basic contention WT instruction.
In the figure, a basic WT is used as an example of a user-written program.
Ladder display of instructions, S (set), R (reset), W (write), which are the normal instruction displays that code them
And a corresponding WT instruction KS (contention set), KR (contention reset), and KW (contention write) corresponding thereto.

The basic operation of each WT instruction is described below. (a) LD A; read input A SX; when A = 1 ---> output X = 1 (set) When A = 0 ---> no processing (NOP) (b) LD B; read B R Y; B = 1, output Y = 0 (reset) B = 0, no processing (NOP) (c) LD C; read C W Z; output Z = C unconditionally In the corresponding conflicting WT instruction, the above (a) to (c) are as follows: (a) LD A; read A KS X; if A = 1-> output X = 1 (set) Shared mask bit of output X = 1 (set) When A = 0-> no processing (NOP) (b) LD B; read B KR Y; when B = 1-> output Y = 0 (reset ) Shared mask bit of output Y = 1 (set) When B = 0 ---> No processing (NOP) (c) LD C; read C KW Z; unconditionally output Z = A shared mask bit = 1 in the read value output Z (set) from.

FIG. 14 shows an example of a conflict WT instruction generation process by the loader. As shown in FIG. 14A, when the loader generates an execution object of each CPU module as the loader process, the loader executes all the CPU modules (CPU0, CPU1,
Refer to the source program of CPU 2) and select a different CPU.
Output to the same output point of the same input / output module,
That is, a portion where writing to the same output address is performed is checked. When a location where a plurality of CPUs are writing to the same address is detected, a WT instruction in the source program of the CPU is determined as a conflict W as shown in FIG.
After being converted into a T instruction, an execution object is generated.

In the case of FIG. 14B, CPU0 and CPU1
During the program of, the loader conflicts with the write to bit 15 of the output module DO0,
And the WT instruction for bit 15 in the source program of the CPU 1 is replaced with a competitive WT instruction (KW). still,
Since the writing of the CPU 0 to the DO0 bit 2 and the writing of the CPU 1 to the DO0 bit 10 do not compete with other CPUs, they remain the normal WT instruction (W).

The writing to the same address occurs when the output point is used by a plurality of CPU modules in conflict, and when the writing occurs due to a factor that is not recognized by the user due to an error in the programming operation or the like. Conceivable. Therefore, to eliminate the latter factor,
The loader issues a warning of a conflicting WT to warn the user of address duplication before replacing with the conflicting WT instruction.

FIG. 15 is a diagram showing an example of a warning notification of a conflict WT by the loader. As a method of this warning notification, as shown in FIG. 7A, the output instruction portion in which the conflict occurs is displayed in a different color from that of the other display portions, or is blinked, as shown in FIG. There is a way to emphasize. In the case of the figure, while the normal display portion is displayed in white, the write command portion in which the conflict has occurred is displayed in red to notify the user.

As another method of the warning notification, there is a method in which the contention control location is indicated by a program line number and an instruction type in a list format as shown in FIG. The user can detect a program error from these warning notifications. In the above description, the digital output module (DO module) has been described as an example of the output module. However, the analog output module (AO module) has exactly the same concept of sharing and contention control. This can be realized by supporting one bit of data, for example, one word. For example, in a 4-word AO module,
The first word is used by CPU0 and the second word is used by CPU1.
In the case where the third and fourth words are used by the CPU 2, sharing is performed and a mode with a shared mask is set, and 4-word data is controlled by 4-bit shared mask data. The sharing and contention control circuit in the output module can be realized not by a simple AND and OR circuit but by a selector and a circuit for generating intermediate value data and an average value data.

[0112]

According to the programmable controller according to the present invention, it is not necessary to newly provide an input module to inform the CPU module of the output state of the output module.

In the output module, the output data can be shared and the contention can be controlled by each CPU module by using the shared mask transmitted together with the output data from each CPU module.

Further, in the CPU module, the same address can be set for the output data for the output module and the reference output without causing a problem such as the CPU module erroneously recognizing the output state of the output module. Therefore, the same address can be used when outputting data to the output module and when referring to the output state, so that programming is not confused. This simplifies data input / output processing based on application programming, and realizes simplification of a program and improvement in processing speed.

In the case of output data that does not require sharing and contention control, if the shared mask is not transmitted to the output module together with the output data, a single CPU
The communication load becomes the same as that of the system, and the system performance can be improved. That is, even in a single CPU system, the present invention can be used as it is in the above-mentioned mode without shared mask.

Further, in the program development of the multi-CPU programmable controller, even if the user performs a conflict control, if the user writes a normal write command to the input / output module, the loader refers to the programs of the plurality of CPUs. Automatically converts it into an instruction dedicated to conflict control. In addition, since this conversion part is notified to the user, the user can easily confirm whether the address has been duplicated in consideration of the conflict or whether the address has been duplicated by mistake. Program quality can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram schematically illustrating a DO module according to an embodiment.

FIG. 2 is an explanatory diagram of communication by a total frame method.

FIG. 3 is an explanatory diagram of communication by a multicast method.

FIG. 4 is a diagram showing the contention control circuit of the DO module in detail.

FIG. 5 is a functional block diagram showing components for input / output processing of a CPU module.

FIG. 6 is a diagram illustrating an example of a shared mask created by a CPU module.

FIG. 7 is a diagram illustrating a configuration example of a multicast frame.

FIG. 8 is a timing chart showing an example of input / output states on each module and a bus when two CPU modules share a DO module.

FIG. 9 is a diagram illustrating a configuration example of a multicast frame according to the second embodiment.

FIG. 10 is a diagram illustrating in detail a contention control circuit according to the second embodiment.

FIG. 11 is a diagram illustrating a shared mask mode determination logic performed in each CPU module.

FIG. 12 is a diagram illustrating an example of control of shared mask data by a CPU module according to the second embodiment.

FIG. 13 is a diagram showing an example of a basic contention WT (write) instruction.

FIG. 14 is a diagram illustrating an example of a competitive WT instruction generation process by a loader.

FIG. 15 is a diagram illustrating an example of a warning notification of a conflict WT.

FIG. 16 is a diagram showing a programmable controller having a multi-CPU configuration in which a plurality of CPU modules, DI modules, and DO modules are connected to a bus.

FIG. 17 is a diagram illustrating an example of a return input of a DO module output by a DI module.

FIG. 18 is a timing chart showing a state of output data on each module and a bus.

FIG. 19 is a functional block diagram for input / output processing of a conventional CPU module.

FIG. 20 is a timing chart showing the state of input / output on each module and bus when the transfer source address of output data to the DO module and the transfer destination address of input data from the DI module are the same.

[Explanation of symbols]

 1, 101 Serial link bus 2, 102 CPU module 3, 103 DO module 10, 40 Shared and conflict control circuit 11 Shared mask 12 Output data 13, 14, 45 AND circuit 15, 44, 53 OR circuit 16 Reference output latch 21 Operation Execution unit 22 I / O area 23 Output buffer 24 Input buffer 25 Serial link control unit 26 Input buffer transfer table 27 Input data transfer table 28 Shared mask data area 41 Shared mask valid mode storage register 42 New reception presence storage register 43 NOT circuit 51 Fixed shared mask register 52 Output condition shared mask register 54 Serial link output shared mask register

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)

Claims (19)

[Claims] A plurality of CPU modules and at least one
A programmable controller including two output modules, wherein each of the CPU modules generates a shared mask for instructing whether to change an output state of the output module; Output data transmitting means for transmitting the output data from the CPU module together with the shared mask, and output data receiving means for receiving the output data from the CPU module together with the shared mask; and determining an output state from the output data and the shared mask. And a sharing and contention control means. 2. The sharing and contention control means determines the output state based on the output data and the sharing mask from a plurality of CPU modules sharing the same and a current output state of the own. The programmable controller according to claim 1, wherein 3. The output module further includes a reference output transmitting unit that transmits a reference output indicating the output state to the plurality of CPU modules sharing the self.
The U module includes a shared mask storage unit that stores the shared mask generated by the shared mask generation unit, and an output state of the output module based on the shared mask stored in the shared mask storage unit and the reference output from the output module. 3. The programmable controller according to claim 1, further comprising: output state reference data generating means for generating reference data indicating the following. 4. A reference data storage means for storing reference data indicating an output state of the output module generated by the output state reference data generation means in the same area as an address area for storing the output data for the output module. The programmable controller according to claim 3, further comprising: 5. The CPU module and the output module are connected by a bus having a configuration on a ring, and the CPU module and the output module circulate a frame on the bus to transfer data with another module. The programmable controller according to claim 1, wherein: 6. The CPU module transmits data to the output module by a multicast method, and the output module transmits data to the CPU module by a total frame method. The programmable controller according to claim 5, wherein 7. The output data transmitting means, when the output module for transmitting the output data does not need to share the output data with output data from another CPU module and perform conflict control. 7. The programmable controller according to claim 1, wherein the shared mask is not transmitted at the time of transmitting. 8. The output data transmitting means, further comprising: a data transfer mode control bit generating means for generating a data transfer mode control bit for notifying whether or not the shared mask has been transmitted together with the output data. Transmits the data transfer mode control bit with the output data, and the sharing and contention control means outputs the data when the data transfer mode control bit indicates that the shared mask is not transmitted with the output data. 8. The output state is determined from only data.
The programmable controller as described. 9. The output data transmitting means includes another CPU.
8. The programmable controller according to claim 7, wherein, when transmitting an output instruction to an output module having an output point shared and competing with a module as the output data, the shared mask is transmitted together with the output data. 10. The shared mask generating means always sets a bit corresponding to an output point not conflicting with another CPU module of the output module, and sets a bit corresponding to a conflicting output point when an output condition is satisfied. 10. The shared mask is generated by resetting when the output data transmitting means transmits output data.
The programmable controller according to any one of the above. 11. The CPU module may include another CPU.
11. A contention write command for rewriting a corresponding shared mask when writing data to an output point that conflicts with the output data is provided. 4. The programmable controller according to 1. 12. An output data receiving means for receiving output data from a CPU module together with a shared mask indicating whether to change its own output state, and sharing and competition for determining an output state from the output data and the shared mask. An output module of a programmable controller, comprising: a control unit. 13. The sharing and contention control means, when the shared mask is not transmitted together with the output data,
13. The output module according to claim 12, wherein an output state is determined from the output data. 14. A shared mask generating means for generating a shared mask for instructing an output module whether to change an output state, and output data transmitting means for transmitting the shared mask to the output module together with the output data. A CPU module of a programmable controller, comprising: 15. The output data transmitting means, when the output module for transmitting the output data does not need to share the output data with the output data from another CPU module and to control the contention of the output data, The CPU module of a programmable controller according to claim 14, wherein the transmission does not transmit the shared mask. 16. A program reference means for referring to programs of all CPU modules constituting a programmable controller having a multi-CPU configuration, wherein the reference result is such that a plurality of CPU modules output the same output module to the same output point in the program. And a competing write command generating means for converting the command into a competing write command when the command includes a command indicating: 17. The programmable controller application program development apparatus according to claim 16, further comprising a warning notifying unit for notifying a user of a part to be converted into the conflicting write instruction. 18. A method for controlling data output sharing and competition in a programmable controller having a plurality of CPU modules and at least one output module, wherein each of the CPU modules changes an output state with respect to an output module. Generating a shared mask instructing the output module and transmitting output data to the output module together with the shared mask; the output module receiving the output data from the CPU module together with the shared mask; A method of controlling data output sharing and competition in a programmable controller, comprising: 19. The CPU module determines whether the output module of the transmission destination needs sharing and conflict control with output data from another CPU module for the output data. If not,
The method of claim 18, wherein the sharing mask is not transmitted to the output module.